| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf548/defBF549.h |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: |
| 7 | * Description: |
| 8 | * |
| 9 | * Rev: |
| 10 | * |
| 11 | * Modified: |
| 12 | * |
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License as published by |
| 17 | * the Free Software Foundation; either version 2, or (at your option) |
| 18 | * any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; see the file COPYING. |
| 27 | * If not, write to the Free Software Foundation, |
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 29 | */ |
| 30 | |
| 31 | #ifndef _DEF_BF549_H |
| 32 | #define _DEF_BF549_H |
| 33 | |
| 34 | /* Include all Core registers and bit definitions */ |
| 35 | #include <asm/mach-common/def_LPBlackfin.h> |
| 36 | |
| 37 | |
| 38 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ |
| 39 | |
| 40 | /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ |
| 41 | #include "defBF54x_base.h" |
| 42 | |
| 43 | /* The following are the #defines needed by ADSP-BF549 that are not in the common header */ |
| 44 | |
| 45 | /* Timer Registers */ |
| 46 | |
| 47 | #define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ |
| 48 | #define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ |
| 49 | #define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ |
| 50 | #define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ |
| 51 | #define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ |
| 52 | #define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ |
| 53 | #define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ |
| 54 | #define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ |
| 55 | #define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ |
| 56 | #define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ |
| 57 | #define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ |
| 58 | #define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ |
| 59 | |
| 60 | /* Timer Group of 3 Registers */ |
| 61 | |
| 62 | #define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ |
| 63 | #define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ |
| 64 | #define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ |
| 65 | |
| 66 | /* SPORT0 Registers */ |
| 67 | |
| 68 | #define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ |
| 69 | #define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ |
| 70 | #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ |
| 71 | #define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ |
| 72 | #define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ |
| 73 | #define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ |
| 74 | #define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ |
| 75 | #define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ |
| 76 | #define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ |
| 77 | #define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ |
| 78 | #define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ |
| 79 | #define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ |
| 80 | #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ |
| 81 | #define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ |
| 82 | #define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ |
| 83 | #define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ |
| 84 | #define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ |
| 85 | #define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ |
| 86 | #define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ |
| 87 | #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ |
| 88 | #define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ |
| 89 | #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ |
| 90 | |
| 91 | /* EPPI0 Registers */ |
| 92 | |
| 93 | #define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ |
| 94 | #define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ |
| 95 | #define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ |
| 96 | #define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ |
| 97 | #define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ |
| 98 | #define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ |
| 99 | #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ |
| 100 | #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ |
| 101 | #define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ |
| 102 | #define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ |
| 103 | #define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ |
| 104 | #define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ |
| 105 | #define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ |
| 106 | #define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ |
| 107 | |
| 108 | /* UART2 Registers */ |
| 109 | |
| 110 | #define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ |
| 111 | #define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ |
| 112 | #define UART2_GCTL 0xffc02108 /* Global Control Register */ |
| 113 | #define UART2_LCR 0xffc0210c /* Line Control Register */ |
| 114 | #define UART2_MCR 0xffc02110 /* Modem Control Register */ |
| 115 | #define UART2_LSR 0xffc02114 /* Line Status Register */ |
| 116 | #define UART2_MSR 0xffc02118 /* Modem Status Register */ |
| 117 | #define UART2_SCR 0xffc0211c /* Scratch Register */ |
| 118 | #define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ |
| 119 | #define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ |
| 120 | #define UART2_RBR 0xffc0212c /* Receive Buffer Register */ |
| 121 | |
| 122 | /* Two Wire Interface Registers (TWI1) */ |
| 123 | |
| 124 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
| 125 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
| 126 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ |
| 127 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ |
| 128 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ |
| 129 | #define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ |
| 130 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ |
| 131 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ |
| 132 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ |
| 133 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ |
| 134 | #define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ |
| 135 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ |
| 136 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ |
| 137 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ |
| 138 | #define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ |
| 139 | #define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ |
| 140 | |
| 141 | /* SPI2 Registers */ |
| 142 | |
| 143 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ |
| 144 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ |
| 145 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ |
| 146 | #define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ |
| 147 | #define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ |
| 148 | #define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ |
| 149 | #define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ |
| 150 | |
| 151 | /* MXVR Registers */ |
| 152 | |
| 153 | #define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */ |
| 154 | #define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */ |
| 155 | #define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */ |
| 156 | #define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */ |
| 157 | #define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */ |
| 158 | #define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */ |
| 159 | #define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */ |
| 160 | #define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */ |
| 161 | #define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */ |
| 162 | #define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */ |
| 163 | #define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */ |
| 164 | #define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */ |
| 165 | #define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */ |
| 166 | #define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */ |
| 167 | |
| 168 | /* MXVR Allocation Table Registers */ |
| 169 | |
| 170 | #define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */ |
| 171 | #define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */ |
| 172 | #define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */ |
| 173 | #define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */ |
| 174 | #define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */ |
| 175 | #define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */ |
| 176 | #define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */ |
| 177 | #define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */ |
| 178 | #define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */ |
| 179 | #define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */ |
| 180 | #define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */ |
| 181 | #define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */ |
| 182 | #define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */ |
| 183 | #define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */ |
| 184 | #define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */ |
| 185 | |
| 186 | /* MXVR Channel Assign Registers */ |
| 187 | |
| 188 | #define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ |
| 189 | #define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */ |
| 190 | #define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ |
| 191 | #define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ |
| 192 | #define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ |
| 193 | #define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */ |
| 194 | #define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ |
| 195 | #define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ |
| 196 | |
| 197 | /* MXVR DMA0 Registers */ |
| 198 | |
| 199 | #define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */ |
| 200 | #define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */ |
| 201 | #define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */ |
| 202 | #define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */ |
| 203 | #define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */ |
| 204 | |
| 205 | /* MXVR DMA1 Registers */ |
| 206 | |
| 207 | #define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */ |
| 208 | #define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */ |
| 209 | #define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */ |
| 210 | #define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */ |
| 211 | #define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */ |
| 212 | |
| 213 | /* MXVR DMA2 Registers */ |
| 214 | |
| 215 | #define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */ |
| 216 | #define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */ |
| 217 | #define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */ |
| 218 | #define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ |
| 219 | #define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */ |
| 220 | |
| 221 | /* MXVR DMA3 Registers */ |
| 222 | |
| 223 | #define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */ |
| 224 | #define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */ |
| 225 | #define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */ |
| 226 | #define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ |
| 227 | #define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */ |
| 228 | |
| 229 | /* MXVR DMA4 Registers */ |
| 230 | |
| 231 | #define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */ |
| 232 | #define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */ |
| 233 | #define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */ |
| 234 | #define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */ |
| 235 | #define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */ |
| 236 | |
| 237 | /* MXVR DMA5 Registers */ |
| 238 | |
| 239 | #define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */ |
| 240 | #define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */ |
| 241 | #define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */ |
| 242 | #define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */ |
| 243 | #define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */ |
| 244 | |
| 245 | /* MXVR DMA6 Registers */ |
| 246 | |
| 247 | #define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */ |
| 248 | #define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */ |
| 249 | #define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */ |
| 250 | #define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */ |
| 251 | #define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */ |
| 252 | |
| 253 | /* MXVR DMA7 Registers */ |
| 254 | |
| 255 | #define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */ |
| 256 | #define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */ |
| 257 | #define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */ |
| 258 | #define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */ |
| 259 | #define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */ |
| 260 | |
| 261 | /* MXVR Asynch Packet Registers */ |
| 262 | |
| 263 | #define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */ |
| 264 | #define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */ |
| 265 | #define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */ |
| 266 | #define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */ |
| 267 | #define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */ |
| 268 | |
| 269 | /* MXVR Control Message Registers */ |
| 270 | |
| 271 | #define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */ |
| 272 | #define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */ |
| 273 | #define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */ |
| 274 | #define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */ |
| 275 | #define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */ |
| 276 | |
| 277 | /* MXVR Remote Read Registers */ |
| 278 | |
| 279 | #define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */ |
| 280 | #define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */ |
| 281 | |
| 282 | /* MXVR Pattern Data Registers */ |
| 283 | |
| 284 | #define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */ |
| 285 | #define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */ |
| 286 | #define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */ |
| 287 | #define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */ |
| 288 | |
| 289 | /* MXVR Frame Counter Registers */ |
| 290 | |
| 291 | #define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */ |
| 292 | #define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */ |
| 293 | |
| 294 | /* MXVR Routing Table Registers */ |
| 295 | |
| 296 | #define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */ |
| 297 | #define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */ |
| 298 | #define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */ |
| 299 | #define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */ |
| 300 | #define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */ |
| 301 | #define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */ |
| 302 | #define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */ |
| 303 | #define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */ |
| 304 | #define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */ |
| 305 | #define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */ |
| 306 | #define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */ |
| 307 | #define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */ |
| 308 | #define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */ |
| 309 | #define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */ |
| 310 | #define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */ |
| 311 | |
| 312 | /* MXVR Counter-Clock-Control Registers */ |
| 313 | |
| 314 | #define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */ |
| 315 | #define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ |
| 316 | #define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */ |
| 317 | #define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */ |
| 318 | #define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ |
| 319 | #define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ |
| 320 | |
| 321 | /* CAN Controller 1 Config 1 Registers */ |
| 322 | |
| 323 | #define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ |
| 324 | #define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ |
| 325 | #define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ |
| 326 | #define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ |
| 327 | #define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ |
| 328 | #define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ |
| 329 | #define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ |
| 330 | #define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ |
| 331 | #define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ |
| 332 | #define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ |
| 333 | #define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ |
| 334 | #define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ |
| 335 | #define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ |
| 336 | |
| 337 | /* CAN Controller 1 Config 2 Registers */ |
| 338 | |
| 339 | #define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ |
| 340 | #define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ |
| 341 | #define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ |
| 342 | #define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ |
| 343 | #define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ |
| 344 | #define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ |
| 345 | #define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ |
| 346 | #define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ |
| 347 | #define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ |
| 348 | #define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ |
| 349 | #define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ |
| 350 | #define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ |
| 351 | #define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ |
| 352 | |
| 353 | /* CAN Controller 1 Clock/Interrupt/Counter Registers */ |
| 354 | |
| 355 | #define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ |
| 356 | #define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ |
| 357 | #define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ |
| 358 | #define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ |
| 359 | #define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ |
| 360 | #define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ |
| 361 | #define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ |
| 362 | #define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ |
| 363 | #define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ |
| 364 | #define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ |
| 365 | #define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ |
| 366 | #define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ |
| 367 | #define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ |
| 368 | #define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ |
| 369 | #define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ |
| 370 | #define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ |
| 371 | |
| 372 | /* CAN Controller 1 Mailbox Acceptance Registers */ |
| 373 | |
| 374 | #define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ |
| 375 | #define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ |
| 376 | #define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ |
| 377 | #define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ |
| 378 | #define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ |
| 379 | #define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ |
| 380 | #define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ |
| 381 | #define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ |
| 382 | #define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ |
| 383 | #define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ |
| 384 | #define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ |
| 385 | #define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ |
| 386 | #define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ |
| 387 | #define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ |
| 388 | #define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ |
| 389 | #define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ |
| 390 | #define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ |
| 391 | #define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ |
| 392 | #define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ |
| 393 | #define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ |
| 394 | #define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ |
| 395 | #define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ |
| 396 | #define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ |
| 397 | #define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ |
| 398 | #define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ |
| 399 | #define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ |
| 400 | #define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ |
| 401 | #define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ |
| 402 | #define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ |
| 403 | #define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ |
| 404 | #define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ |
| 405 | #define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ |
| 406 | |
| 407 | /* CAN Controller 1 Mailbox Acceptance Registers */ |
| 408 | |
| 409 | #define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ |
| 410 | #define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ |
| 411 | #define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ |
| 412 | #define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ |
| 413 | #define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ |
| 414 | #define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ |
| 415 | #define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ |
| 416 | #define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ |
| 417 | #define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ |
| 418 | #define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ |
| 419 | #define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ |
| 420 | #define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ |
| 421 | #define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ |
| 422 | #define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ |
| 423 | #define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ |
| 424 | #define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ |
| 425 | #define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ |
| 426 | #define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ |
| 427 | #define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ |
| 428 | #define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ |
| 429 | #define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ |
| 430 | #define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ |
| 431 | #define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ |
| 432 | #define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ |
| 433 | #define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ |
| 434 | #define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ |
| 435 | #define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ |
| 436 | #define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ |
| 437 | #define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ |
| 438 | #define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ |
| 439 | #define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ |
| 440 | #define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ |
| 441 | |
| 442 | /* CAN Controller 1 Mailbox Data Registers */ |
| 443 | |
| 444 | #define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ |
| 445 | #define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ |
| 446 | #define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ |
| 447 | #define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ |
| 448 | #define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ |
| 449 | #define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ |
| 450 | #define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ |
| 451 | #define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ |
| 452 | #define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ |
| 453 | #define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ |
| 454 | #define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ |
| 455 | #define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ |
| 456 | #define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ |
| 457 | #define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ |
| 458 | #define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ |
| 459 | #define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ |
| 460 | #define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ |
| 461 | #define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ |
| 462 | #define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ |
| 463 | #define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ |
| 464 | #define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ |
| 465 | #define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ |
| 466 | #define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ |
| 467 | #define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ |
| 468 | #define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ |
| 469 | #define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ |
| 470 | #define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ |
| 471 | #define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ |
| 472 | #define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ |
| 473 | #define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ |
| 474 | #define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ |
| 475 | #define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ |
| 476 | #define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ |
| 477 | #define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ |
| 478 | #define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ |
| 479 | #define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ |
| 480 | #define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ |
| 481 | #define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ |
| 482 | #define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ |
| 483 | #define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ |
| 484 | #define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ |
| 485 | #define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ |
| 486 | #define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ |
| 487 | #define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ |
| 488 | #define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ |
| 489 | #define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ |
| 490 | #define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ |
| 491 | #define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ |
| 492 | #define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ |
| 493 | #define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ |
| 494 | #define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ |
| 495 | #define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ |
| 496 | #define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ |
| 497 | #define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ |
| 498 | #define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ |
| 499 | #define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ |
| 500 | #define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ |
| 501 | #define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ |
| 502 | #define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ |
| 503 | #define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ |
| 504 | #define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ |
| 505 | #define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ |
| 506 | #define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ |
| 507 | #define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ |
| 508 | #define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ |
| 509 | #define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ |
| 510 | #define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ |
| 511 | #define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ |
| 512 | #define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ |
| 513 | #define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ |
| 514 | #define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ |
| 515 | #define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ |
| 516 | #define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ |
| 517 | #define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ |
| 518 | #define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ |
| 519 | #define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ |
| 520 | #define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ |
| 521 | #define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ |
| 522 | #define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ |
| 523 | #define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ |
| 524 | #define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ |
| 525 | #define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ |
| 526 | #define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ |
| 527 | #define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ |
| 528 | #define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ |
| 529 | #define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ |
| 530 | #define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ |
| 531 | #define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ |
| 532 | #define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ |
| 533 | #define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ |
| 534 | #define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ |
| 535 | #define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ |
| 536 | #define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ |
| 537 | #define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ |
| 538 | #define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ |
| 539 | #define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ |
| 540 | #define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ |
| 541 | #define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ |
| 542 | #define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ |
| 543 | #define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ |
| 544 | #define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ |
| 545 | #define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ |
| 546 | #define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ |
| 547 | #define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ |
| 548 | #define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ |
| 549 | #define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ |
| 550 | #define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ |
| 551 | #define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ |
| 552 | #define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ |
| 553 | #define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ |
| 554 | #define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ |
| 555 | #define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ |
| 556 | #define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ |
| 557 | #define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ |
| 558 | #define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ |
| 559 | #define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ |
| 560 | #define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ |
| 561 | #define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ |
| 562 | #define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ |
| 563 | #define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ |
| 564 | #define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ |
| 565 | #define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ |
| 566 | #define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ |
| 567 | #define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ |
| 568 | #define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ |
| 569 | #define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ |
| 570 | #define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ |
| 571 | #define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ |
| 572 | |
| 573 | /* CAN Controller 1 Mailbox Data Registers */ |
| 574 | |
| 575 | #define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ |
| 576 | #define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ |
| 577 | #define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ |
| 578 | #define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ |
| 579 | #define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ |
| 580 | #define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ |
| 581 | #define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ |
| 582 | #define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ |
| 583 | #define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ |
| 584 | #define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ |
| 585 | #define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ |
| 586 | #define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ |
| 587 | #define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ |
| 588 | #define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ |
| 589 | #define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ |
| 590 | #define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ |
| 591 | #define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ |
| 592 | #define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ |
| 593 | #define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ |
| 594 | #define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ |
| 595 | #define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ |
| 596 | #define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ |
| 597 | #define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ |
| 598 | #define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ |
| 599 | #define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ |
| 600 | #define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ |
| 601 | #define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ |
| 602 | #define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ |
| 603 | #define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ |
| 604 | #define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ |
| 605 | #define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ |
| 606 | #define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ |
| 607 | #define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ |
| 608 | #define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ |
| 609 | #define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ |
| 610 | #define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ |
| 611 | #define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ |
| 612 | #define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ |
| 613 | #define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ |
| 614 | #define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ |
| 615 | #define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ |
| 616 | #define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ |
| 617 | #define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ |
| 618 | #define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ |
| 619 | #define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ |
| 620 | #define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ |
| 621 | #define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ |
| 622 | #define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ |
| 623 | #define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ |
| 624 | #define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ |
| 625 | #define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ |
| 626 | #define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ |
| 627 | #define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ |
| 628 | #define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ |
| 629 | #define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ |
| 630 | #define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ |
| 631 | #define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ |
| 632 | #define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ |
| 633 | #define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ |
| 634 | #define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ |
| 635 | #define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ |
| 636 | #define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ |
| 637 | #define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ |
| 638 | #define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ |
| 639 | #define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ |
| 640 | #define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ |
| 641 | #define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ |
| 642 | #define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ |
| 643 | #define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ |
| 644 | #define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ |
| 645 | #define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ |
| 646 | #define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ |
| 647 | #define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ |
| 648 | #define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ |
| 649 | #define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ |
| 650 | #define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ |
| 651 | #define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ |
| 652 | #define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ |
| 653 | #define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ |
| 654 | #define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ |
| 655 | #define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ |
| 656 | #define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ |
| 657 | #define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ |
| 658 | #define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ |
| 659 | #define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ |
| 660 | #define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ |
| 661 | #define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ |
| 662 | #define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ |
| 663 | #define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ |
| 664 | #define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ |
| 665 | #define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ |
| 666 | #define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ |
| 667 | #define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ |
| 668 | #define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ |
| 669 | #define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ |
| 670 | #define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ |
| 671 | #define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ |
| 672 | #define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ |
| 673 | #define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ |
| 674 | #define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ |
| 675 | #define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ |
| 676 | #define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ |
| 677 | #define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ |
| 678 | #define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ |
| 679 | #define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ |
| 680 | #define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ |
| 681 | #define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ |
| 682 | #define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ |
| 683 | #define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ |
| 684 | #define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ |
| 685 | #define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ |
| 686 | #define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ |
| 687 | #define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ |
| 688 | #define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ |
| 689 | #define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ |
| 690 | #define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ |
| 691 | #define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ |
| 692 | #define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ |
| 693 | #define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ |
| 694 | #define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ |
| 695 | #define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ |
| 696 | #define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ |
| 697 | #define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ |
| 698 | #define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ |
| 699 | #define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ |
| 700 | #define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ |
| 701 | #define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ |
| 702 | #define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ |
| 703 | |
| 704 | /* ATAPI Registers */ |
| 705 | |
| 706 | #define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ |
| 707 | #define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ |
| 708 | #define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ |
| 709 | #define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ |
| 710 | #define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ |
| 711 | #define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ |
| 712 | #define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ |
| 713 | #define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ |
| 714 | #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ |
| 715 | #define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ |
| 716 | #define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ |
| 717 | #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ |
| 718 | #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ |
| 719 | #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ |
| 720 | #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ |
| 721 | #define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ |
| 722 | #define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ |
| 723 | #define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ |
| 724 | #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ |
| 725 | #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ |
| 726 | #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ |
| 727 | #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ |
| 728 | #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ |
| 729 | #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ |
| 730 | #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ |
| 731 | |
| 732 | /* SDH Registers */ |
| 733 | |
| 734 | #define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ |
| 735 | #define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ |
| 736 | #define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ |
| 737 | #define SDH_COMMAND 0xffc0390c /* SDH Command */ |
| 738 | #define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ |
| 739 | #define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ |
| 740 | #define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ |
| 741 | #define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ |
| 742 | #define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ |
| 743 | #define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ |
| 744 | #define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ |
| 745 | #define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ |
| 746 | #define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ |
| 747 | #define SDH_STATUS 0xffc03934 /* SDH Status */ |
| 748 | #define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ |
| 749 | #define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ |
| 750 | #define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ |
| 751 | #define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ |
| 752 | #define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ |
| 753 | #define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ |
| 754 | #define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ |
| 755 | #define SDH_CFG 0xffc039c8 /* SDH Configuration */ |
| 756 | #define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ |
| 757 | #define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ |
| 758 | #define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ |
| 759 | #define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ |
| 760 | #define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ |
| 761 | #define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ |
| 762 | #define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ |
| 763 | #define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ |
| 764 | #define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ |
| 765 | |
| 766 | /* HOST Port Registers */ |
| 767 | |
| 768 | #define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ |
| 769 | #define HOST_STATUS 0xffc03a04 /* HOST Status Register */ |
| 770 | #define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ |
| 771 | |
| 772 | /* USB Control Registers */ |
| 773 | |
| 774 | #define USB_FADDR 0xffc03c00 /* Function address register */ |
| 775 | #define USB_POWER 0xffc03c04 /* Power management register */ |
| 776 | #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ |
| 777 | #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ |
| 778 | #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ |
| 779 | #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ |
| 780 | #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ |
| 781 | #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ |
| 782 | #define USB_FRAME 0xffc03c20 /* USB frame number */ |
| 783 | #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ |
| 784 | #define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ |
| 785 | #define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ |
| 786 | #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ |
| 787 | |
| 788 | /* USB Packet Control Registers */ |
| 789 | |
| 790 | #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ |
| 791 | #define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| 792 | #define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| 793 | #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ |
| 794 | #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ |
| 795 | #define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| 796 | #define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| 797 | #define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ |
| 798 | #define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| 799 | #define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| 800 | #define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ |
| 801 | #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ |
| 802 | #define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
| 803 | |
| 804 | /* USB Endpoint FIFO Registers */ |
| 805 | |
| 806 | #define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ |
| 807 | #define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ |
| 808 | #define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ |
| 809 | #define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ |
| 810 | #define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ |
| 811 | #define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ |
| 812 | #define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ |
| 813 | #define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ |
| 814 | |
| 815 | /* USB OTG Control Registers */ |
| 816 | |
| 817 | #define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ |
| 818 | #define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ |
| 819 | #define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ |
| 820 | |
| 821 | /* USB Phy Control Registers */ |
| 822 | |
| 823 | #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ |
| 824 | #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ |
| 825 | #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ |
| 826 | #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ |
| 827 | #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ |
| 828 | |
| 829 | /* (APHY_CNTRL is for ADI usage only) */ |
| 830 | |
| 831 | #define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ |
| 832 | |
| 833 | /* (APHY_CALIB is for ADI usage only) */ |
| 834 | |
| 835 | #define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ |
| 836 | #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ |
| 837 | |
| 838 | /* (PHY_TEST is for ADI usage only) */ |
| 839 | |
| 840 | #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ |
| 841 | #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ |
| 842 | #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ |
| 843 | |
| 844 | /* USB Endpoint 0 Control Registers */ |
| 845 | |
| 846 | #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ |
| 847 | #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ |
| 848 | #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ |
| 849 | #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ |
| 850 | #define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ |
| 851 | #define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ |
| 852 | #define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ |
| 853 | #define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ |
| 854 | #define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ |
| 855 | |
| 856 | /* USB Endpoint 1 Control Registers */ |
| 857 | |
| 858 | #define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ |
| 859 | #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ |
| 860 | #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ |
| 861 | #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ |
| 862 | #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ |
| 863 | #define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ |
| 864 | #define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ |
| 865 | #define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ |
| 866 | #define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ |
| 867 | #define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ |
| 868 | |
| 869 | /* USB Endpoint 2 Control Registers */ |
| 870 | |
| 871 | #define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ |
| 872 | #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ |
| 873 | #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ |
| 874 | #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ |
| 875 | #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ |
| 876 | #define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ |
| 877 | #define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ |
| 878 | #define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ |
| 879 | #define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ |
| 880 | #define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ |
| 881 | |
| 882 | /* USB Endpoint 3 Control Registers */ |
| 883 | |
| 884 | #define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ |
| 885 | #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ |
| 886 | #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ |
| 887 | #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ |
| 888 | #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ |
| 889 | #define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ |
| 890 | #define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ |
| 891 | #define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ |
| 892 | #define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ |
| 893 | #define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ |
| 894 | |
| 895 | /* USB Endpoint 4 Control Registers */ |
| 896 | |
| 897 | #define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ |
| 898 | #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ |
| 899 | #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ |
| 900 | #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ |
| 901 | #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ |
| 902 | #define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ |
| 903 | #define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ |
| 904 | #define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ |
| 905 | #define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ |
| 906 | #define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ |
| 907 | |
| 908 | /* USB Endpoint 5 Control Registers */ |
| 909 | |
| 910 | #define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ |
| 911 | #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ |
| 912 | #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ |
| 913 | #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ |
| 914 | #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ |
| 915 | #define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ |
| 916 | #define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ |
| 917 | #define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ |
| 918 | #define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ |
| 919 | #define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ |
| 920 | |
| 921 | /* USB Endpoint 6 Control Registers */ |
| 922 | |
| 923 | #define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ |
| 924 | #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ |
| 925 | #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ |
| 926 | #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ |
| 927 | #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ |
| 928 | #define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ |
| 929 | #define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ |
| 930 | #define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ |
| 931 | #define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ |
| 932 | #define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ |
| 933 | |
| 934 | /* USB Endpoint 7 Control Registers */ |
| 935 | |
| 936 | #define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ |
| 937 | #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ |
| 938 | #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ |
| 939 | #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ |
| 940 | #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ |
| 941 | #define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ |
| 942 | #define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ |
| 943 | #define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ |
| 944 | #define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ |
| 945 | #define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ |
| 946 | #define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ |
| 947 | #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ |
| 948 | |
| 949 | /* USB Channel 0 Config Registers */ |
| 950 | |
| 951 | #define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ |
| 952 | #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ |
| 953 | #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ |
| 954 | #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| 955 | #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| 956 | |
| 957 | /* USB Channel 1 Config Registers */ |
| 958 | |
| 959 | #define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ |
| 960 | #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ |
| 961 | #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ |
| 962 | #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| 963 | #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| 964 | |
| 965 | /* USB Channel 2 Config Registers */ |
| 966 | |
| 967 | #define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ |
| 968 | #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ |
| 969 | #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ |
| 970 | #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| 971 | #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| 972 | |
| 973 | /* USB Channel 3 Config Registers */ |
| 974 | |
| 975 | #define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ |
| 976 | #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ |
| 977 | #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ |
| 978 | #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| 979 | #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| 980 | |
| 981 | /* USB Channel 4 Config Registers */ |
| 982 | |
| 983 | #define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ |
| 984 | #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ |
| 985 | #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ |
| 986 | #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| 987 | #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| 988 | |
| 989 | /* USB Channel 5 Config Registers */ |
| 990 | |
| 991 | #define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ |
| 992 | #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ |
| 993 | #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ |
| 994 | #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| 995 | #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| 996 | |
| 997 | /* USB Channel 6 Config Registers */ |
| 998 | |
| 999 | #define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ |
| 1000 | #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ |
| 1001 | #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ |
| 1002 | #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| 1003 | #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| 1004 | |
| 1005 | /* USB Channel 7 Config Registers */ |
| 1006 | |
| 1007 | #define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ |
| 1008 | #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ |
| 1009 | #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ |
| 1010 | #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| 1011 | #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| 1012 | |
| 1013 | /* Keypad Registers */ |
| 1014 | |
| 1015 | #define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ |
| 1016 | #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ |
| 1017 | #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ |
| 1018 | #define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ |
| 1019 | #define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ |
| 1020 | #define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ |
| 1021 | |
| 1022 | /* Pixel Compositor (PIXC) Registers */ |
| 1023 | |
| 1024 | #define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ |
| 1025 | #define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ |
| 1026 | #define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ |
| 1027 | #define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ |
| 1028 | #define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ |
| 1029 | #define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ |
| 1030 | #define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ |
| 1031 | #define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ |
| 1032 | #define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ |
| 1033 | #define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ |
| 1034 | #define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ |
| 1035 | #define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ |
| 1036 | #define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ |
| 1037 | #define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ |
| 1038 | #define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ |
| 1039 | #define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ |
| 1040 | #define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ |
| 1041 | #define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ |
| 1042 | #define PIXC_TC 0xffc04450 /* Holds the transparent color value */ |
| 1043 | |
| 1044 | /* Handshake MDMA 0 Registers */ |
| 1045 | |
| 1046 | #define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ |
| 1047 | #define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ |
| 1048 | #define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ |
| 1049 | #define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ |
| 1050 | #define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ |
| 1051 | #define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ |
| 1052 | #define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ |
| 1053 | |
| 1054 | /* Handshake MDMA 1 Registers */ |
| 1055 | |
| 1056 | #define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ |
| 1057 | #define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ |
| 1058 | #define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ |
| 1059 | #define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ |
| 1060 | #define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ |
| 1061 | #define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ |
| 1062 | #define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ |
| 1063 | |
| 1064 | |
| 1065 | /* ********************************************************** */ |
| 1066 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ |
| 1067 | /* and MULTI BIT READ MACROS */ |
| 1068 | /* ********************************************************** */ |
| 1069 | |
| 1070 | /* Bit masks for PIXC_CTL */ |
| 1071 | |
| 1072 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1073 | #define OVR_A_EN 0x2 /* Overlay A Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1074 | #define OVR_B_EN 0x4 /* Overlay B Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1075 | #define IMG_FORM 0x8 /* Image Data Format */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1076 | #define OVR_FORM 0x10 /* Overlay Data Format */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1077 | #define OUT_FORM 0x20 /* Output Data Format */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1078 | #define UDS_MOD 0x40 /* Resampling Mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1079 | #define TC_EN 0x80 /* Transparent Color Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1080 | #define IMG_STAT 0x300 /* Image FIFO Status */ |
| 1081 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ |
| 1082 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ |
| 1083 | |
| 1084 | /* Bit masks for PIXC_AHSTART */ |
| 1085 | |
| 1086 | #define A_HSTART 0xfff /* Horizontal Start Coordinates */ |
| 1087 | |
| 1088 | /* Bit masks for PIXC_AHEND */ |
| 1089 | |
| 1090 | #define A_HEND 0xfff /* Horizontal End Coordinates */ |
| 1091 | |
| 1092 | /* Bit masks for PIXC_AVSTART */ |
| 1093 | |
| 1094 | #define A_VSTART 0x3ff /* Vertical Start Coordinates */ |
| 1095 | |
| 1096 | /* Bit masks for PIXC_AVEND */ |
| 1097 | |
| 1098 | #define A_VEND 0x3ff /* Vertical End Coordinates */ |
| 1099 | |
| 1100 | /* Bit masks for PIXC_ATRANSP */ |
| 1101 | |
| 1102 | #define A_TRANSP 0xf /* Transparency Value */ |
| 1103 | |
| 1104 | /* Bit masks for PIXC_BHSTART */ |
| 1105 | |
| 1106 | #define B_HSTART 0xfff /* Horizontal Start Coordinates */ |
| 1107 | |
| 1108 | /* Bit masks for PIXC_BHEND */ |
| 1109 | |
| 1110 | #define B_HEND 0xfff /* Horizontal End Coordinates */ |
| 1111 | |
| 1112 | /* Bit masks for PIXC_BVSTART */ |
| 1113 | |
| 1114 | #define B_VSTART 0x3ff /* Vertical Start Coordinates */ |
| 1115 | |
| 1116 | /* Bit masks for PIXC_BVEND */ |
| 1117 | |
| 1118 | #define B_VEND 0x3ff /* Vertical End Coordinates */ |
| 1119 | |
| 1120 | /* Bit masks for PIXC_BTRANSP */ |
| 1121 | |
| 1122 | #define B_TRANSP 0xf /* Transparency Value */ |
| 1123 | |
| 1124 | /* Bit masks for PIXC_INTRSTAT */ |
| 1125 | |
| 1126 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1127 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1128 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1129 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1130 | |
| 1131 | /* Bit masks for PIXC_RYCON */ |
| 1132 | |
| 1133 | #define A11 0x3ff /* A11 in the Coefficient Matrix */ |
| 1134 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ |
| 1135 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ |
| 1136 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1137 | |
| 1138 | /* Bit masks for PIXC_GUCON */ |
| 1139 | |
| 1140 | #define A21 0x3ff /* A21 in the Coefficient Matrix */ |
| 1141 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ |
| 1142 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ |
| 1143 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1144 | |
| 1145 | /* Bit masks for PIXC_BVCON */ |
| 1146 | |
| 1147 | #define A31 0x3ff /* A31 in the Coefficient Matrix */ |
| 1148 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ |
| 1149 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ |
| 1150 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1151 | |
| 1152 | /* Bit masks for PIXC_CCBIAS */ |
| 1153 | |
| 1154 | #define A14 0x3ff /* A14 in the Bias Vector */ |
| 1155 | #define A24 0xffc00 /* A24 in the Bias Vector */ |
| 1156 | #define A34 0x3ff00000 /* A34 in the Bias Vector */ |
| 1157 | |
| 1158 | /* Bit masks for PIXC_TC */ |
| 1159 | |
| 1160 | #define RY_TRANS 0xff /* Transparent Color - R/Y Component */ |
| 1161 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ |
| 1162 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ |
| 1163 | |
| 1164 | /* Bit masks for HOST_CONTROL */ |
| 1165 | |
| 1166 | #define HOST_EN 0x1 /* Host Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1167 | #define HOST_END 0x2 /* Host Endianess */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1168 | #define DATA_SIZE 0x4 /* Data Size */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1169 | #define HOST_RST 0x8 /* Host Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1170 | #define HRDY_OVR 0x20 /* Host Ready Override */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1171 | #define INT_MODE 0x40 /* Interrupt Mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1172 | #define BT_EN 0x80 /* Bus Timeout Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1173 | #define EHW 0x100 /* Enable Host Write */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1174 | #define EHR 0x200 /* Enable Host Read */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1175 | #define BDR 0x400 /* Burst DMA Requests */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1176 | |
| 1177 | /* Bit masks for HOST_STATUS */ |
| 1178 | |
| 1179 | #define READY 0x1 /* DMA Ready */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1180 | #define FIFOFULL 0x2 /* FIFO Full */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1181 | #define FIFOEMPTY 0x4 /* FIFO Empty */ |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1182 | #define DMA_COMPLETE 0x8 /* DMA Complete */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1183 | #define HSHK 0x10 /* Host Handshake */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1184 | #define TIMEOUT 0x20 /* Host Timeout */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1185 | #define HIRQ 0x40 /* Host Interrupt Request */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1186 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1187 | #define DMA_DIR 0x100 /* DMA Direction */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1188 | #define BTE 0x200 /* Bus Timeout Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1189 | |
| 1190 | /* Bit masks for HOST_TIMEOUT */ |
| 1191 | |
| 1192 | #define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ |
| 1193 | |
| 1194 | /* Bit masks for MXVR_CONFIG */ |
| 1195 | |
| 1196 | #define MXVREN 0x1 /* MXVR Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1197 | #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1198 | #define ACTIVE 0x4 /* Active Mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1199 | #define SDELAY 0x8 /* Synchronous Data Delay */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1200 | #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1201 | #define RWRRXEN 0x20 /* Remote Write Receive Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1202 | #define MTXEN 0x40 /* MXVR Transmit Data Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1203 | #define MTXONB 0x80 /* MXVR Phy Transmitter On */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1204 | #define EPARITY 0x100 /* Even Parity Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1205 | #define MSB 0x1e00 /* Master Synchronous Boundary */ |
| 1206 | #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1207 | #define WAKEUP 0x4000 /* Wake-Up */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1208 | #define LMECH 0x8000 /* Lock Mechanism Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1209 | |
| 1210 | /* Bit masks for MXVR_STATE_0 */ |
| 1211 | |
| 1212 | #define NACT 0x1 /* Network Activity */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1213 | #define SBLOCK 0x2 /* Super Block Lock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1214 | #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ |
| 1215 | #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ |
| 1216 | #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1217 | #define APARB 0x200 /* Asynchronous Packet Arbitrating */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1218 | #define APTX 0x400 /* Asynchronous Packet Transmitting */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1219 | #define APRX 0x800 /* Receiving Asynchronous Packet */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1220 | #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1221 | #define CMARB 0x2000 /* Control Message Arbitrating */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1222 | #define CMTX 0x4000 /* Control Message Transmitting */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1223 | #define CMRX 0x8000 /* Receiving Control Message */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1224 | #define MRXONB 0x10000 /* MRXONB Pin State */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1225 | #define RGSIP 0x20000 /* Remote Get Source In Progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1226 | #define DALIP 0x40000 /* Resource Deallocate In Progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1227 | #define ALIP 0x80000 /* Resource Allocate In Progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1228 | #define RRDIP 0x100000 /* Remote Read In Progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1229 | #define RWRIP 0x200000 /* Remote Write In Progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1230 | #define FLOCK 0x400000 /* Frame Lock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1231 | #define BLOCK 0x800000 /* Block Lock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1232 | #define RSB 0xf000000 /* Received Synchronous Boundary */ |
| 1233 | #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ |
| 1234 | |
| 1235 | /* Bit masks for MXVR_STATE_1 */ |
| 1236 | |
| 1237 | #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ |
| 1238 | #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ |
| 1239 | #define APCONT 0x100 /* Asynchronous Packet Continuation */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1240 | #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ |
| 1241 | #define DMAACTIVE0 0x10000 /* DMA0 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1242 | #define DMAACTIVE1 0x20000 /* DMA1 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1243 | #define DMAACTIVE2 0x40000 /* DMA2 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1244 | #define DMAACTIVE3 0x80000 /* DMA3 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1245 | #define DMAACTIVE4 0x100000 /* DMA4 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1246 | #define DMAACTIVE5 0x200000 /* DMA5 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1247 | #define DMAACTIVE6 0x400000 /* DMA6 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1248 | #define DMAACTIVE7 0x800000 /* DMA7 Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1249 | #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1250 | #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1251 | #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1252 | #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1253 | #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1254 | #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1255 | #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1256 | #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1257 | |
| 1258 | /* Bit masks for MXVR_INT_STAT_0 */ |
| 1259 | |
| 1260 | #define NI2A 0x1 /* Network Inactive to Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1261 | #define NA2I 0x2 /* Network Active to Inactive */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1262 | #define SBU2L 0x4 /* Super Block Unlock to Lock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1263 | #define SBL2U 0x8 /* Super Block Lock to Unlock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1264 | #define PRU 0x10 /* Position Register Updated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1265 | #define MPRU 0x20 /* Maximum Position Register Updated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1266 | #define DRU 0x40 /* Delay Register Updated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1267 | #define MDRU 0x80 /* Maximum Delay Register Updated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1268 | #define SBU 0x100 /* Synchronous Boundary Updated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1269 | #define ATU 0x200 /* Allocation Table Updated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1270 | #define FCZ0 0x400 /* Frame Counter 0 Zero */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1271 | #define FCZ1 0x800 /* Frame Counter 1 Zero */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1272 | #define PERR 0x1000 /* Parity Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1273 | #define MH2L 0x2000 /* MRXONB High to Low */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1274 | #define ML2H 0x4000 /* MRXONB Low to High */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1275 | #define WUP 0x8000 /* Wake-Up Preamble Received */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1276 | #define FU2L 0x10000 /* Frame Unlock to Lock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1277 | #define FL2U 0x20000 /* Frame Lock to Unlock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1278 | #define BU2L 0x40000 /* Block Unlock to Lock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1279 | #define BL2U 0x80000 /* Block Lock to Unlock */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1280 | #define OBERR 0x100000 /* DMA Out of Bounds Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1281 | #define PFL 0x200000 /* PLL Frequency Locked */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1282 | #define SCZ 0x400000 /* System Clock Counter Zero */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1283 | #define FERR 0x800000 /* FIFO Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1284 | #define CMR 0x1000000 /* Control Message Received */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1285 | #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1286 | #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1287 | #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1288 | #define RWRC 0x10000000 /* Remote Write Control Message Completed */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1289 | #define BCZ 0x20000000 /* Block Counter Zero */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1290 | #define BMERR 0x40000000 /* Biphase Mark Coding Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1291 | #define DERR 0x80000000 /* DMA Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1292 | |
| 1293 | /* Bit masks for MXVR_INT_STAT_1 */ |
| 1294 | |
| 1295 | #define HDONE0 0x1 /* DMA0 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1296 | #define DONE0 0x2 /* DMA0 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1297 | #define APR 0x4 /* Asynchronous Packet Received */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1298 | #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1299 | #define HDONE1 0x10 /* DMA1 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1300 | #define DONE1 0x20 /* DMA1 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1301 | #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1302 | #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1303 | #define HDONE2 0x100 /* DMA2 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1304 | #define DONE2 0x200 /* DMA2 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1305 | #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1306 | #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1307 | #define HDONE3 0x1000 /* DMA3 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1308 | #define DONE3 0x2000 /* DMA3 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1309 | #define HDONE4 0x10000 /* DMA4 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1310 | #define DONE4 0x20000 /* DMA4 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1311 | #define HDONE5 0x100000 /* DMA5 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1312 | #define DONE5 0x200000 /* DMA5 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1313 | #define HDONE6 0x1000000 /* DMA6 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1314 | #define DONE6 0x2000000 /* DMA6 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1315 | #define HDONE7 0x10000000 /* DMA7 Half Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1316 | #define DONE7 0x20000000 /* DMA7 Done */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1317 | |
| 1318 | /* Bit masks for MXVR_INT_EN_0 */ |
| 1319 | |
| 1320 | #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1321 | #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1322 | #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1323 | #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1324 | #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1325 | #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1326 | #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1327 | #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1328 | #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1329 | #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1330 | #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1331 | #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1332 | #define PERREN 0x1000 /* Parity Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1333 | #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1334 | #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1335 | #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1336 | #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1337 | #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1338 | #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1339 | #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1340 | #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1341 | #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1342 | #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1343 | #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1344 | #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1345 | #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1346 | #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1347 | #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1348 | #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1349 | #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1350 | #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1351 | #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1352 | |
| 1353 | /* Bit masks for MXVR_INT_EN_1 */ |
| 1354 | |
| 1355 | #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1356 | #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1357 | #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1358 | #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1359 | #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1360 | #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1361 | #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1362 | #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1363 | #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1364 | #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1365 | #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1366 | #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1367 | #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1368 | #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1369 | #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1370 | #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1371 | #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1372 | #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1373 | #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1374 | #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1375 | #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1376 | #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1377 | |
| 1378 | /* Bit masks for MXVR_POSITION */ |
| 1379 | |
| 1380 | #define POSITION 0x3f /* Node Position */ |
| 1381 | #define PVALID 0x8000 /* Node Position Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1382 | |
| 1383 | /* Bit masks for MXVR_MAX_POSITION */ |
| 1384 | |
| 1385 | #define MPOSITION 0x3f /* Maximum Node Position */ |
| 1386 | #define MPVALID 0x8000 /* Maximum Node Position Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1387 | |
| 1388 | /* Bit masks for MXVR_DELAY */ |
| 1389 | |
| 1390 | #define DELAY 0x3f /* Node Frame Delay */ |
| 1391 | #define DVALID 0x8000 /* Node Frame Delay Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1392 | |
| 1393 | /* Bit masks for MXVR_MAX_DELAY */ |
| 1394 | |
| 1395 | #define MDELAY 0x3f /* Maximum Node Frame Delay */ |
| 1396 | #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1397 | |
| 1398 | /* Bit masks for MXVR_LADDR */ |
| 1399 | |
| 1400 | #define LADDR 0xffff /* Logical Address */ |
| 1401 | #define LVALID 0x80000000 /* Logical Address Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1402 | |
| 1403 | /* Bit masks for MXVR_GADDR */ |
| 1404 | |
| 1405 | #define GADDRL 0xff /* Group Address Lower Byte */ |
| 1406 | #define GVALID 0x8000 /* Group Address Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1407 | |
| 1408 | /* Bit masks for MXVR_AADDR */ |
| 1409 | |
| 1410 | #define AADDR 0xffff /* Alternate Address */ |
| 1411 | #define AVALID 0x80000000 /* Alternate Address Valid */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1412 | |
| 1413 | /* Bit masks for MXVR_ALLOC_0 */ |
| 1414 | |
| 1415 | #define CL0 0x7f /* Channel 0 Connection Label */ |
| 1416 | #define CIU0 0x80 /* Channel 0 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1417 | #define CL1 0x7f00 /* Channel 0 Connection Label */ |
| 1418 | #define CIU1 0x8000 /* Channel 0 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1419 | #define CL2 0x7f0000 /* Channel 0 Connection Label */ |
| 1420 | #define CIU2 0x800000 /* Channel 0 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1421 | #define CL3 0x7f000000 /* Channel 0 Connection Label */ |
| 1422 | #define CIU3 0x80000000 /* Channel 0 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1423 | |
| 1424 | /* Bit masks for MXVR_ALLOC_1 */ |
| 1425 | |
| 1426 | #define CL4 0x7f /* Channel 4 Connection Label */ |
| 1427 | #define CIU4 0x80 /* Channel 4 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1428 | #define CL5 0x7f00 /* Channel 5 Connection Label */ |
| 1429 | #define CIU5 0x8000 /* Channel 5 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1430 | #define CL6 0x7f0000 /* Channel 6 Connection Label */ |
| 1431 | #define CIU6 0x800000 /* Channel 6 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1432 | #define CL7 0x7f000000 /* Channel 7 Connection Label */ |
| 1433 | #define CIU7 0x80000000 /* Channel 7 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1434 | |
| 1435 | /* Bit masks for MXVR_ALLOC_2 */ |
| 1436 | |
| 1437 | #define CL8 0x7f /* Channel 8 Connection Label */ |
| 1438 | #define CIU8 0x80 /* Channel 8 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1439 | #define CL9 0x7f00 /* Channel 9 Connection Label */ |
| 1440 | #define CIU9 0x8000 /* Channel 9 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1441 | #define CL10 0x7f0000 /* Channel 10 Connection Label */ |
| 1442 | #define CIU10 0x800000 /* Channel 10 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1443 | #define CL11 0x7f000000 /* Channel 11 Connection Label */ |
| 1444 | #define CIU11 0x80000000 /* Channel 11 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1445 | |
| 1446 | /* Bit masks for MXVR_ALLOC_3 */ |
| 1447 | |
| 1448 | #define CL12 0x7f /* Channel 12 Connection Label */ |
| 1449 | #define CIU12 0x80 /* Channel 12 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1450 | #define CL13 0x7f00 /* Channel 13 Connection Label */ |
| 1451 | #define CIU13 0x8000 /* Channel 13 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1452 | #define CL14 0x7f0000 /* Channel 14 Connection Label */ |
| 1453 | #define CIU14 0x800000 /* Channel 14 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1454 | #define CL15 0x7f000000 /* Channel 15 Connection Label */ |
| 1455 | #define CIU15 0x80000000 /* Channel 15 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1456 | |
| 1457 | /* Bit masks for MXVR_ALLOC_4 */ |
| 1458 | |
| 1459 | #define CL16 0x7f /* Channel 16 Connection Label */ |
| 1460 | #define CIU16 0x80 /* Channel 16 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1461 | #define CL17 0x7f00 /* Channel 17 Connection Label */ |
| 1462 | #define CIU17 0x8000 /* Channel 17 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1463 | #define CL18 0x7f0000 /* Channel 18 Connection Label */ |
| 1464 | #define CIU18 0x800000 /* Channel 18 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1465 | #define CL19 0x7f000000 /* Channel 19 Connection Label */ |
| 1466 | #define CIU19 0x80000000 /* Channel 19 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1467 | |
| 1468 | /* Bit masks for MXVR_ALLOC_5 */ |
| 1469 | |
| 1470 | #define CL20 0x7f /* Channel 20 Connection Label */ |
| 1471 | #define CIU20 0x80 /* Channel 20 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1472 | #define CL21 0x7f00 /* Channel 21 Connection Label */ |
| 1473 | #define CIU21 0x8000 /* Channel 21 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1474 | #define CL22 0x7f0000 /* Channel 22 Connection Label */ |
| 1475 | #define CIU22 0x800000 /* Channel 22 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1476 | #define CL23 0x7f000000 /* Channel 23 Connection Label */ |
| 1477 | #define CIU23 0x80000000 /* Channel 23 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1478 | |
| 1479 | /* Bit masks for MXVR_ALLOC_6 */ |
| 1480 | |
| 1481 | #define CL24 0x7f /* Channel 24 Connection Label */ |
| 1482 | #define CIU24 0x80 /* Channel 24 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1483 | #define CL25 0x7f00 /* Channel 25 Connection Label */ |
| 1484 | #define CIU25 0x8000 /* Channel 25 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1485 | #define CL26 0x7f0000 /* Channel 26 Connection Label */ |
| 1486 | #define CIU26 0x800000 /* Channel 26 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1487 | #define CL27 0x7f000000 /* Channel 27 Connection Label */ |
| 1488 | #define CIU27 0x80000000 /* Channel 27 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1489 | |
| 1490 | /* Bit masks for MXVR_ALLOC_7 */ |
| 1491 | |
| 1492 | #define CL28 0x7f /* Channel 28 Connection Label */ |
| 1493 | #define CIU28 0x80 /* Channel 28 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1494 | #define CL29 0x7f00 /* Channel 29 Connection Label */ |
| 1495 | #define CIU29 0x8000 /* Channel 29 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1496 | #define CL30 0x7f0000 /* Channel 30 Connection Label */ |
| 1497 | #define CIU30 0x800000 /* Channel 30 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1498 | #define CL31 0x7f000000 /* Channel 31 Connection Label */ |
| 1499 | #define CIU31 0x80000000 /* Channel 31 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1500 | |
| 1501 | /* Bit masks for MXVR_ALLOC_8 */ |
| 1502 | |
| 1503 | #define CL32 0x7f /* Channel 32 Connection Label */ |
| 1504 | #define CIU32 0x80 /* Channel 32 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1505 | #define CL33 0x7f00 /* Channel 33 Connection Label */ |
| 1506 | #define CIU33 0x8000 /* Channel 33 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1507 | #define CL34 0x7f0000 /* Channel 34 Connection Label */ |
| 1508 | #define CIU34 0x800000 /* Channel 34 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1509 | #define CL35 0x7f000000 /* Channel 35 Connection Label */ |
| 1510 | #define CIU35 0x80000000 /* Channel 35 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1511 | |
| 1512 | /* Bit masks for MXVR_ALLOC_9 */ |
| 1513 | |
| 1514 | #define CL36 0x7f /* Channel 36 Connection Label */ |
| 1515 | #define CIU36 0x80 /* Channel 36 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1516 | #define CL37 0x7f00 /* Channel 37 Connection Label */ |
| 1517 | #define CIU37 0x8000 /* Channel 37 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1518 | #define CL38 0x7f0000 /* Channel 38 Connection Label */ |
| 1519 | #define CIU38 0x800000 /* Channel 38 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1520 | #define CL39 0x7f000000 /* Channel 39 Connection Label */ |
| 1521 | #define CIU39 0x80000000 /* Channel 39 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1522 | |
| 1523 | /* Bit masks for MXVR_ALLOC_10 */ |
| 1524 | |
| 1525 | #define CL40 0x7f /* Channel 40 Connection Label */ |
| 1526 | #define CIU40 0x80 /* Channel 40 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1527 | #define CL41 0x7f00 /* Channel 41 Connection Label */ |
| 1528 | #define CIU41 0x8000 /* Channel 41 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1529 | #define CL42 0x7f0000 /* Channel 42 Connection Label */ |
| 1530 | #define CIU42 0x800000 /* Channel 42 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1531 | #define CL43 0x7f000000 /* Channel 43 Connection Label */ |
| 1532 | #define CIU43 0x80000000 /* Channel 43 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1533 | |
| 1534 | /* Bit masks for MXVR_ALLOC_11 */ |
| 1535 | |
| 1536 | #define CL44 0x7f /* Channel 44 Connection Label */ |
| 1537 | #define CIU44 0x80 /* Channel 44 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1538 | #define CL45 0x7f00 /* Channel 45 Connection Label */ |
| 1539 | #define CIU45 0x8000 /* Channel 45 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1540 | #define CL46 0x7f0000 /* Channel 46 Connection Label */ |
| 1541 | #define CIU46 0x800000 /* Channel 46 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1542 | #define CL47 0x7f000000 /* Channel 47 Connection Label */ |
| 1543 | #define CIU47 0x80000000 /* Channel 47 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1544 | |
| 1545 | /* Bit masks for MXVR_ALLOC_12 */ |
| 1546 | |
| 1547 | #define CL48 0x7f /* Channel 48 Connection Label */ |
| 1548 | #define CIU48 0x80 /* Channel 48 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1549 | #define CL49 0x7f00 /* Channel 49 Connection Label */ |
| 1550 | #define CIU49 0x8000 /* Channel 49 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1551 | #define CL50 0x7f0000 /* Channel 50 Connection Label */ |
| 1552 | #define CIU50 0x800000 /* Channel 50 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1553 | #define CL51 0x7f000000 /* Channel 51 Connection Label */ |
| 1554 | #define CIU51 0x80000000 /* Channel 51 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1555 | |
| 1556 | /* Bit masks for MXVR_ALLOC_13 */ |
| 1557 | |
| 1558 | #define CL52 0x7f /* Channel 52 Connection Label */ |
| 1559 | #define CIU52 0x80 /* Channel 52 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1560 | #define CL53 0x7f00 /* Channel 53 Connection Label */ |
| 1561 | #define CIU53 0x8000 /* Channel 53 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1562 | #define CL54 0x7f0000 /* Channel 54 Connection Label */ |
| 1563 | #define CIU54 0x800000 /* Channel 54 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1564 | #define CL55 0x7f000000 /* Channel 55 Connection Label */ |
| 1565 | #define CIU55 0x80000000 /* Channel 55 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1566 | |
| 1567 | /* Bit masks for MXVR_ALLOC_14 */ |
| 1568 | |
| 1569 | #define CL56 0x7f /* Channel 56 Connection Label */ |
| 1570 | #define CIU56 0x80 /* Channel 56 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1571 | #define CL57 0x7f00 /* Channel 57 Connection Label */ |
| 1572 | #define CIU57 0x8000 /* Channel 57 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1573 | #define CL58 0x7f0000 /* Channel 58 Connection Label */ |
| 1574 | #define CIU58 0x800000 /* Channel 58 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1575 | #define CL59 0x7f000000 /* Channel 59 Connection Label */ |
| 1576 | #define CIU59 0x80000000 /* Channel 59 In Use */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1577 | |
| 1578 | /* MXVR_SYNC_LCHAN_0 Masks */ |
| 1579 | |
| 1580 | #define LCHANPC0 0x0000000Flu |
| 1581 | #define LCHANPC1 0x000000F0lu |
| 1582 | #define LCHANPC2 0x00000F00lu |
| 1583 | #define LCHANPC3 0x0000F000lu |
| 1584 | #define LCHANPC4 0x000F0000lu |
| 1585 | #define LCHANPC5 0x00F00000lu |
| 1586 | #define LCHANPC6 0x0F000000lu |
| 1587 | #define LCHANPC7 0xF0000000lu |
| 1588 | |
| 1589 | |
| 1590 | /* MXVR_SYNC_LCHAN_1 Masks */ |
| 1591 | |
| 1592 | #define LCHANPC8 0x0000000Flu |
| 1593 | #define LCHANPC9 0x000000F0lu |
| 1594 | #define LCHANPC10 0x00000F00lu |
| 1595 | #define LCHANPC11 0x0000F000lu |
| 1596 | #define LCHANPC12 0x000F0000lu |
| 1597 | #define LCHANPC13 0x00F00000lu |
| 1598 | #define LCHANPC14 0x0F000000lu |
| 1599 | #define LCHANPC15 0xF0000000lu |
| 1600 | |
| 1601 | |
| 1602 | /* MXVR_SYNC_LCHAN_2 Masks */ |
| 1603 | |
| 1604 | #define LCHANPC16 0x0000000Flu |
| 1605 | #define LCHANPC17 0x000000F0lu |
| 1606 | #define LCHANPC18 0x00000F00lu |
| 1607 | #define LCHANPC19 0x0000F000lu |
| 1608 | #define LCHANPC20 0x000F0000lu |
| 1609 | #define LCHANPC21 0x00F00000lu |
| 1610 | #define LCHANPC22 0x0F000000lu |
| 1611 | #define LCHANPC23 0xF0000000lu |
| 1612 | |
| 1613 | |
| 1614 | /* MXVR_SYNC_LCHAN_3 Masks */ |
| 1615 | |
| 1616 | #define LCHANPC24 0x0000000Flu |
| 1617 | #define LCHANPC25 0x000000F0lu |
| 1618 | #define LCHANPC26 0x00000F00lu |
| 1619 | #define LCHANPC27 0x0000F000lu |
| 1620 | #define LCHANPC28 0x000F0000lu |
| 1621 | #define LCHANPC29 0x00F00000lu |
| 1622 | #define LCHANPC30 0x0F000000lu |
| 1623 | #define LCHANPC31 0xF0000000lu |
| 1624 | |
| 1625 | |
| 1626 | /* MXVR_SYNC_LCHAN_4 Masks */ |
| 1627 | |
| 1628 | #define LCHANPC32 0x0000000Flu |
| 1629 | #define LCHANPC33 0x000000F0lu |
| 1630 | #define LCHANPC34 0x00000F00lu |
| 1631 | #define LCHANPC35 0x0000F000lu |
| 1632 | #define LCHANPC36 0x000F0000lu |
| 1633 | #define LCHANPC37 0x00F00000lu |
| 1634 | #define LCHANPC38 0x0F000000lu |
| 1635 | #define LCHANPC39 0xF0000000lu |
| 1636 | |
| 1637 | |
| 1638 | /* MXVR_SYNC_LCHAN_5 Masks */ |
| 1639 | |
| 1640 | #define LCHANPC40 0x0000000Flu |
| 1641 | #define LCHANPC41 0x000000F0lu |
| 1642 | #define LCHANPC42 0x00000F00lu |
| 1643 | #define LCHANPC43 0x0000F000lu |
| 1644 | #define LCHANPC44 0x000F0000lu |
| 1645 | #define LCHANPC45 0x00F00000lu |
| 1646 | #define LCHANPC46 0x0F000000lu |
| 1647 | #define LCHANPC47 0xF0000000lu |
| 1648 | |
| 1649 | |
| 1650 | /* MXVR_SYNC_LCHAN_6 Masks */ |
| 1651 | |
| 1652 | #define LCHANPC48 0x0000000Flu |
| 1653 | #define LCHANPC49 0x000000F0lu |
| 1654 | #define LCHANPC50 0x00000F00lu |
| 1655 | #define LCHANPC51 0x0000F000lu |
| 1656 | #define LCHANPC52 0x000F0000lu |
| 1657 | #define LCHANPC53 0x00F00000lu |
| 1658 | #define LCHANPC54 0x0F000000lu |
| 1659 | #define LCHANPC55 0xF0000000lu |
| 1660 | |
| 1661 | |
| 1662 | /* MXVR_SYNC_LCHAN_7 Masks */ |
| 1663 | |
| 1664 | #define LCHANPC56 0x0000000Flu |
| 1665 | #define LCHANPC57 0x000000F0lu |
| 1666 | #define LCHANPC58 0x00000F00lu |
| 1667 | #define LCHANPC59 0x0000F000lu |
| 1668 | |
| 1669 | /* Bit masks for MXVR_DMAx_CONFIG */ |
| 1670 | |
| 1671 | #define MDMAEN 0x1 /* DMA Channel Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1672 | #define DD 0x2 /* DMA Channel Direction */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1673 | #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1674 | #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ |
| 1675 | #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1676 | #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1677 | #define MFLOW 0x7000 /* DMA Channel Operation Flow */ |
| 1678 | #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1679 | #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ |
| 1680 | #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ |
| 1681 | #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ |
| 1682 | |
| 1683 | /* Bit masks for MXVR_AP_CTL */ |
| 1684 | |
| 1685 | #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1686 | #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1687 | #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1688 | #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1689 | #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1690 | |
| 1691 | /* Bit masks for MXVR_APRB_START_ADDR */ |
| 1692 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1693 | #define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1694 | |
| 1695 | /* Bit masks for MXVR_APRB_CURR_ADDR */ |
| 1696 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1697 | #define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1698 | |
| 1699 | /* Bit masks for MXVR_APTB_START_ADDR */ |
| 1700 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1701 | #define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1702 | |
| 1703 | /* Bit masks for MXVR_APTB_CURR_ADDR */ |
| 1704 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1705 | #define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1706 | |
| 1707 | /* Bit masks for MXVR_CM_CTL */ |
| 1708 | |
| 1709 | #define STARTCM 0x1 /* Start Control Message Transmission */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1710 | #define CANCELCM 0x2 /* Cancel Control Message Transmission */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1711 | #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1712 | #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1713 | #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1714 | #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1715 | #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1716 | #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1717 | #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1718 | #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1719 | #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1720 | #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1721 | #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1722 | #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1723 | #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1724 | #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1725 | #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1726 | #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1727 | |
| 1728 | /* Bit masks for MXVR_CMRB_START_ADDR */ |
| 1729 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1730 | #define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1731 | |
| 1732 | /* Bit masks for MXVR_CMRB_CURR_ADDR */ |
| 1733 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1734 | #define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1735 | |
| 1736 | /* Bit masks for MXVR_CMTB_START_ADDR */ |
| 1737 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1738 | #define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1739 | |
| 1740 | /* Bit masks for MXVR_CMTB_CURR_ADDR */ |
| 1741 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1742 | #define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1743 | |
| 1744 | /* Bit masks for MXVR_RRDB_START_ADDR */ |
| 1745 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1746 | #define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1747 | |
| 1748 | /* Bit masks for MXVR_RRDB_CURR_ADDR */ |
| 1749 | |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 1750 | #define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1751 | |
| 1752 | /* Bit masks for MXVR_PAT_DATAx */ |
| 1753 | |
| 1754 | #define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */ |
| 1755 | #define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */ |
| 1756 | #define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */ |
| 1757 | #define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */ |
| 1758 | |
| 1759 | /* Bit masks for MXVR_PAT_EN_0 */ |
| 1760 | |
| 1761 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1762 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1763 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1764 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1765 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1766 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1767 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1768 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1769 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1770 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1771 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1772 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1773 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1774 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1775 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1776 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1777 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1778 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1779 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1780 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1781 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1782 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1783 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1784 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1785 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1786 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1787 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1788 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1789 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1790 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1791 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1792 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1793 | |
| 1794 | /* Bit masks for MXVR_PAT_EN_1 */ |
| 1795 | |
| 1796 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1797 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1798 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1799 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1800 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1801 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1802 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1803 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1804 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1805 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1806 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1807 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1808 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1809 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1810 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1811 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1812 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1813 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1814 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1815 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1816 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1817 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1818 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1819 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1820 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1821 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1822 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1823 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1824 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1825 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1826 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1827 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1828 | |
| 1829 | /* Bit masks for MXVR_FRAME_CNT_0 */ |
| 1830 | |
| 1831 | #define FCNT 0xffff /* Frame Count */ |
| 1832 | |
| 1833 | /* Bit masks for MXVR_FRAME_CNT_1 */ |
| 1834 | |
| 1835 | #define FCNT 0xffff /* Frame Count */ |
| 1836 | |
| 1837 | /* Bit masks for MXVR_ROUTING_0 */ |
| 1838 | |
| 1839 | #define TX_CH0 0x3f /* Transmit Channel 0 */ |
| 1840 | #define MUTE_CH0 0x80 /* Mute Channel 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1841 | #define TX_CH1 0x3f00 /* Transmit Channel 0 */ |
| 1842 | #define MUTE_CH1 0x8000 /* Mute Channel 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1843 | #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ |
| 1844 | #define MUTE_CH2 0x800000 /* Mute Channel 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1845 | #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ |
| 1846 | #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1847 | |
| 1848 | /* Bit masks for MXVR_ROUTING_1 */ |
| 1849 | |
| 1850 | #define TX_CH4 0x3f /* Transmit Channel 4 */ |
| 1851 | #define MUTE_CH4 0x80 /* Mute Channel 4 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1852 | #define TX_CH5 0x3f00 /* Transmit Channel 5 */ |
| 1853 | #define MUTE_CH5 0x8000 /* Mute Channel 5 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1854 | #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ |
| 1855 | #define MUTE_CH6 0x800000 /* Mute Channel 6 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1856 | #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ |
| 1857 | #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1858 | |
| 1859 | /* Bit masks for MXVR_ROUTING_2 */ |
| 1860 | |
| 1861 | #define TX_CH8 0x3f /* Transmit Channel 8 */ |
| 1862 | #define MUTE_CH8 0x80 /* Mute Channel 8 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1863 | #define TX_CH9 0x3f00 /* Transmit Channel 9 */ |
| 1864 | #define MUTE_CH9 0x8000 /* Mute Channel 9 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1865 | #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ |
| 1866 | #define MUTE_CH10 0x800000 /* Mute Channel 10 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1867 | #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ |
| 1868 | #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1869 | |
| 1870 | /* Bit masks for MXVR_ROUTING_3 */ |
| 1871 | |
| 1872 | #define TX_CH12 0x3f /* Transmit Channel 12 */ |
| 1873 | #define MUTE_CH12 0x80 /* Mute Channel 12 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1874 | #define TX_CH13 0x3f00 /* Transmit Channel 13 */ |
| 1875 | #define MUTE_CH13 0x8000 /* Mute Channel 13 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1876 | #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ |
| 1877 | #define MUTE_CH14 0x800000 /* Mute Channel 14 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1878 | #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ |
| 1879 | #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1880 | |
| 1881 | /* Bit masks for MXVR_ROUTING_4 */ |
| 1882 | |
| 1883 | #define TX_CH16 0x3f /* Transmit Channel 16 */ |
| 1884 | #define MUTE_CH16 0x80 /* Mute Channel 16 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1885 | #define TX_CH17 0x3f00 /* Transmit Channel 17 */ |
| 1886 | #define MUTE_CH17 0x8000 /* Mute Channel 17 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1887 | #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ |
| 1888 | #define MUTE_CH18 0x800000 /* Mute Channel 18 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1889 | #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ |
| 1890 | #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1891 | |
| 1892 | /* Bit masks for MXVR_ROUTING_5 */ |
| 1893 | |
| 1894 | #define TX_CH20 0x3f /* Transmit Channel 20 */ |
| 1895 | #define MUTE_CH20 0x80 /* Mute Channel 20 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1896 | #define TX_CH21 0x3f00 /* Transmit Channel 21 */ |
| 1897 | #define MUTE_CH21 0x8000 /* Mute Channel 21 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1898 | #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ |
| 1899 | #define MUTE_CH22 0x800000 /* Mute Channel 22 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1900 | #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ |
| 1901 | #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1902 | |
| 1903 | /* Bit masks for MXVR_ROUTING_6 */ |
| 1904 | |
| 1905 | #define TX_CH24 0x3f /* Transmit Channel 24 */ |
| 1906 | #define MUTE_CH24 0x80 /* Mute Channel 24 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1907 | #define TX_CH25 0x3f00 /* Transmit Channel 25 */ |
| 1908 | #define MUTE_CH25 0x8000 /* Mute Channel 25 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1909 | #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ |
| 1910 | #define MUTE_CH26 0x800000 /* Mute Channel 26 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1911 | #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ |
| 1912 | #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1913 | |
| 1914 | /* Bit masks for MXVR_ROUTING_7 */ |
| 1915 | |
| 1916 | #define TX_CH28 0x3f /* Transmit Channel 28 */ |
| 1917 | #define MUTE_CH28 0x80 /* Mute Channel 28 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1918 | #define TX_CH29 0x3f00 /* Transmit Channel 29 */ |
| 1919 | #define MUTE_CH29 0x8000 /* Mute Channel 29 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1920 | #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ |
| 1921 | #define MUTE_CH30 0x800000 /* Mute Channel 30 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1922 | #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ |
| 1923 | #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1924 | |
| 1925 | /* Bit masks for MXVR_ROUTING_8 */ |
| 1926 | |
| 1927 | #define TX_CH32 0x3f /* Transmit Channel 32 */ |
| 1928 | #define MUTE_CH32 0x80 /* Mute Channel 32 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1929 | #define TX_CH33 0x3f00 /* Transmit Channel 33 */ |
| 1930 | #define MUTE_CH33 0x8000 /* Mute Channel 33 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1931 | #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ |
| 1932 | #define MUTE_CH34 0x800000 /* Mute Channel 34 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1933 | #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ |
| 1934 | #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1935 | |
| 1936 | /* Bit masks for MXVR_ROUTING_9 */ |
| 1937 | |
| 1938 | #define TX_CH36 0x3f /* Transmit Channel 36 */ |
| 1939 | #define MUTE_CH36 0x80 /* Mute Channel 36 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1940 | #define TX_CH37 0x3f00 /* Transmit Channel 37 */ |
| 1941 | #define MUTE_CH37 0x8000 /* Mute Channel 37 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1942 | #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ |
| 1943 | #define MUTE_CH38 0x800000 /* Mute Channel 38 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1944 | #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ |
| 1945 | #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1946 | |
| 1947 | /* Bit masks for MXVR_ROUTING_10 */ |
| 1948 | |
| 1949 | #define TX_CH40 0x3f /* Transmit Channel 40 */ |
| 1950 | #define MUTE_CH40 0x80 /* Mute Channel 40 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1951 | #define TX_CH41 0x3f00 /* Transmit Channel 41 */ |
| 1952 | #define MUTE_CH41 0x8000 /* Mute Channel 41 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1953 | #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ |
| 1954 | #define MUTE_CH42 0x800000 /* Mute Channel 42 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1955 | #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ |
| 1956 | #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1957 | |
| 1958 | /* Bit masks for MXVR_ROUTING_11 */ |
| 1959 | |
| 1960 | #define TX_CH44 0x3f /* Transmit Channel 44 */ |
| 1961 | #define MUTE_CH44 0x80 /* Mute Channel 44 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1962 | #define TX_CH45 0x3f00 /* Transmit Channel 45 */ |
| 1963 | #define MUTE_CH45 0x8000 /* Mute Channel 45 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1964 | #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ |
| 1965 | #define MUTE_CH46 0x800000 /* Mute Channel 46 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1966 | #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ |
| 1967 | #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1968 | |
| 1969 | /* Bit masks for MXVR_ROUTING_12 */ |
| 1970 | |
| 1971 | #define TX_CH48 0x3f /* Transmit Channel 48 */ |
| 1972 | #define MUTE_CH48 0x80 /* Mute Channel 48 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1973 | #define TX_CH49 0x3f00 /* Transmit Channel 49 */ |
| 1974 | #define MUTE_CH49 0x8000 /* Mute Channel 49 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1975 | #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ |
| 1976 | #define MUTE_CH50 0x800000 /* Mute Channel 50 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1977 | #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ |
| 1978 | #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1979 | |
| 1980 | /* Bit masks for MXVR_ROUTING_13 */ |
| 1981 | |
| 1982 | #define TX_CH52 0x3f /* Transmit Channel 52 */ |
| 1983 | #define MUTE_CH52 0x80 /* Mute Channel 52 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1984 | #define TX_CH53 0x3f00 /* Transmit Channel 53 */ |
| 1985 | #define MUTE_CH53 0x8000 /* Mute Channel 53 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1986 | #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ |
| 1987 | #define MUTE_CH54 0x800000 /* Mute Channel 54 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1988 | #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ |
| 1989 | #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1990 | |
| 1991 | /* Bit masks for MXVR_ROUTING_14 */ |
| 1992 | |
| 1993 | #define TX_CH56 0x3f /* Transmit Channel 56 */ |
| 1994 | #define MUTE_CH56 0x80 /* Mute Channel 56 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1995 | #define TX_CH57 0x3f00 /* Transmit Channel 57 */ |
| 1996 | #define MUTE_CH57 0x8000 /* Mute Channel 57 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1997 | #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ |
| 1998 | #define MUTE_CH58 0x800000 /* Mute Channel 58 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1999 | #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ |
| 2000 | #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2001 | |
| 2002 | /* Bit masks for MXVR_BLOCK_CNT */ |
| 2003 | |
| 2004 | #define BCNT 0xffff /* Block Count */ |
| 2005 | |
| 2006 | /* Bit masks for MXVR_CLK_CTL */ |
| 2007 | |
| 2008 | #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2009 | #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2010 | #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ |
| 2011 | #define CLKX3SEL 0x80 /* Clock Generation Source Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2012 | #define MMCLKEN 0x100 /* Master Clock Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2013 | #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ |
| 2014 | #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ |
| 2015 | #define MBCLKEN 0x10000 /* Bit Clock Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2016 | #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ |
| 2017 | #define INVRX 0x800000 /* Invert Receive Data */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2018 | #define MFSEN 0x1000000 /* Frame Sync Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2019 | #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ |
| 2020 | #define MFSSEL 0x60000000 /* Frame Sync Select */ |
| 2021 | #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2022 | |
| 2023 | /* Bit masks for MXVR_CDRPLL_CTL */ |
| 2024 | |
| 2025 | #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2026 | #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2027 | #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2028 | #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2029 | #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ |
| 2030 | #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ |
| 2031 | #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ |
| 2032 | #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2033 | #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ |
| 2034 | |
| 2035 | /* Bit masks for MXVR_FMPLL_CTL */ |
| 2036 | |
| 2037 | #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2038 | #define FMRSTB 0x2 /* MXVR FMPLL Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2039 | #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2040 | #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ |
| 2041 | #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ |
| 2042 | #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ |
| 2043 | |
| 2044 | /* Bit masks for MXVR_PIN_CTL */ |
| 2045 | |
| 2046 | #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2047 | #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2048 | #define MFSOE 0x10 /* MFS Output Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2049 | #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2050 | #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2051 | |
| 2052 | /* Bit masks for MXVR_SCLK_CNT */ |
| 2053 | |
| 2054 | #define SCNT 0xffff /* System Clock Count */ |
| 2055 | |
| 2056 | /* Bit masks for KPAD_CTL */ |
| 2057 | |
| 2058 | #define KPAD_EN 0x1 /* Keypad Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2059 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ |
| 2060 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ |
| 2061 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ |
| 2062 | |
| 2063 | /* Bit masks for KPAD_PRESCALE */ |
| 2064 | |
| 2065 | #define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ |
| 2066 | |
| 2067 | /* Bit masks for KPAD_MSEL */ |
| 2068 | |
| 2069 | #define DBON_SCALE 0xff /* Debounce Scale Value */ |
| 2070 | #define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ |
| 2071 | |
| 2072 | /* Bit masks for KPAD_ROWCOL */ |
| 2073 | |
| 2074 | #define KPAD_ROW 0xff /* Rows Pressed */ |
| 2075 | #define KPAD_COL 0xff00 /* Columns Pressed */ |
| 2076 | |
| 2077 | /* Bit masks for KPAD_STAT */ |
| 2078 | |
| 2079 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2080 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ |
| 2081 | #define KPAD_PRESSED 0x8 /* Key press current status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2082 | |
| 2083 | /* Bit masks for KPAD_SOFTEVAL */ |
| 2084 | |
| 2085 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2086 | |
| 2087 | /* Bit masks for SDH_COMMAND */ |
| 2088 | |
| 2089 | #define CMD_IDX 0x3f /* Command Index */ |
| 2090 | #define CMD_RSP 0x40 /* Response */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2091 | #define CMD_L_RSP 0x80 /* Long Response */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2092 | #define CMD_INT_E 0x100 /* Command Interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2093 | #define CMD_PEND_E 0x200 /* Command Pending */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2094 | #define CMD_E 0x400 /* Command Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2095 | |
| 2096 | /* Bit masks for SDH_PWR_CTL */ |
| 2097 | |
| 2098 | #define PWR_ON 0x3 /* Power On */ |
| 2099 | #if 0 |
| 2100 | #define TBD 0x3c /* TBD */ |
| 2101 | #endif |
| 2102 | #define SD_CMD_OD 0x40 /* Open Drain Output */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2103 | #define ROD_CTL 0x80 /* Rod Control */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2104 | |
| 2105 | /* Bit masks for SDH_CLK_CTL */ |
| 2106 | |
| 2107 | #define CLKDIV 0xff /* MC_CLK Divisor */ |
| 2108 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2109 | #define PWR_SV_E 0x200 /* Power Save Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2110 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2111 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2112 | |
| 2113 | /* Bit masks for SDH_RESP_CMD */ |
| 2114 | |
| 2115 | #define RESP_CMD 0x3f /* Response Command */ |
| 2116 | |
| 2117 | /* Bit masks for SDH_DATA_CTL */ |
| 2118 | |
| 2119 | #define DTX_E 0x1 /* Data Transfer Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2120 | #define DTX_DIR 0x2 /* Data Transfer Direction */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2121 | #define DTX_MODE 0x4 /* Data Transfer Mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2122 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2123 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ |
| 2124 | |
| 2125 | /* Bit masks for SDH_STATUS */ |
| 2126 | |
| 2127 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2128 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ |
| Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame^] | 2129 | #define CMD_TIME_OUT 0x4 /* CMD Time Out */ |
| 2130 | #define DAT_TIME_OUT 0x8 /* Data Time Out */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2131 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2132 | #define RX_OVERRUN 0x20 /* Receive Overrun */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2133 | #define CMD_RESP_END 0x40 /* CMD Response End */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2134 | #define CMD_SENT 0x80 /* CMD Sent */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2135 | #define DAT_END 0x100 /* Data End */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2136 | #define START_BIT_ERR 0x200 /* Start Bit Error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2137 | #define DAT_BLK_END 0x400 /* Data Block End */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2138 | #define CMD_ACT 0x800 /* CMD Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2139 | #define TX_ACT 0x1000 /* Transmit Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2140 | #define RX_ACT 0x2000 /* Receive Active */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2141 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2142 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2143 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2144 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2145 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2146 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2147 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2148 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2149 | |
| 2150 | /* Bit masks for SDH_STATUS_CLR */ |
| 2151 | |
| 2152 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2153 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2154 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2155 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2156 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2157 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2158 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2159 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2160 | #define DAT_END_STAT 0x100 /* Data End Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2161 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2162 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2163 | |
| 2164 | /* Bit masks for SDH_MASK0 */ |
| 2165 | |
| 2166 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2167 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2168 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2169 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2170 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2171 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2172 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2173 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2174 | #define DAT_END_MASK 0x100 /* Data End Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2175 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2176 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2177 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2178 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2179 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2180 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2181 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2182 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2183 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2184 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2185 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2186 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2187 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2188 | |
| 2189 | /* Bit masks for SDH_FIFO_CNT */ |
| 2190 | |
| 2191 | #define FIFO_COUNT 0x7fff /* FIFO Count */ |
| 2192 | |
| 2193 | /* Bit masks for SDH_E_STATUS */ |
| 2194 | |
| 2195 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2196 | #define SD_CARD_DET 0x10 /* SD Card Detect */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2197 | |
| 2198 | /* Bit masks for SDH_E_MASK */ |
| 2199 | |
| 2200 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2201 | #define SCD_MSK 0x40 /* Mask Card Detect */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2202 | |
| 2203 | /* Bit masks for SDH_CFG */ |
| 2204 | |
| 2205 | #define CLKS_EN 0x1 /* Clocks Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2206 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2207 | #define MWE 0x8 /* Moving Window Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2208 | #define SD_RST 0x10 /* SDMMC Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2209 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2210 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2211 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2212 | |
| 2213 | /* Bit masks for SDH_RD_WAIT_EN */ |
| 2214 | |
| 2215 | #define RWR 0x1 /* Read Wait Request */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2216 | |
| 2217 | /* Bit masks for ATAPI_CONTROL */ |
| 2218 | |
| 2219 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2220 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2221 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2222 | #define XFER_DIR 0x8 /* Transfer Direction */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2223 | #define IORDY_EN 0x10 /* IORDY Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2224 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2225 | #define SOFT_RST 0x40 /* Soft Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2226 | #define DEV_RST 0x80 /* Device Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2227 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2228 | #define END_ON_TERM 0x200 /* End/Terminate Select */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2229 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2230 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ |
| 2231 | |
| 2232 | /* Bit masks for ATAPI_STATUS */ |
| 2233 | |
| 2234 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2235 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2236 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2237 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ |
| 2238 | |
| 2239 | /* Bit masks for ATAPI_DEV_ADDR */ |
| 2240 | |
| 2241 | #define DEV_ADDR 0x1f /* Device Address */ |
| 2242 | |
| 2243 | /* Bit masks for ATAPI_INT_MASK */ |
| 2244 | |
| 2245 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2246 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2247 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2248 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2249 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2250 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2251 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2252 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2253 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2254 | |
| 2255 | /* Bit masks for ATAPI_INT_STATUS */ |
| 2256 | |
| 2257 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2258 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2259 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2260 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2261 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2262 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2263 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2264 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2265 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2266 | |
| 2267 | /* Bit masks for ATAPI_LINE_STATUS */ |
| 2268 | |
| 2269 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2270 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2271 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2272 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2273 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ |
| 2274 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2275 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2276 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2277 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2278 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2279 | |
| 2280 | /* Bit masks for ATAPI_SM_STATE */ |
| 2281 | |
| 2282 | #define PIO_CSTATE 0xf /* PIO mode state machine current state */ |
| 2283 | #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ |
| 2284 | #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ |
| 2285 | #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ |
| 2286 | |
| 2287 | /* Bit masks for ATAPI_TERMINATE */ |
| 2288 | |
| 2289 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2290 | |
| 2291 | /* Bit masks for ATAPI_REG_TIM_0 */ |
| 2292 | |
| 2293 | #define T2_REG 0xff /* End of cycle time for register access transfers */ |
| 2294 | #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ |
| 2295 | |
| 2296 | /* Bit masks for ATAPI_PIO_TIM_0 */ |
| 2297 | |
| 2298 | #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ |
| 2299 | #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ |
| 2300 | #define T4_REG 0xf000 /* DIOW data hold */ |
| 2301 | |
| 2302 | /* Bit masks for ATAPI_PIO_TIM_1 */ |
| 2303 | |
| 2304 | #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ |
| 2305 | |
| 2306 | /* Bit masks for ATAPI_MULTI_TIM_0 */ |
| 2307 | |
| 2308 | #define TD 0xff /* DIOR/DIOW asserted pulsewidth */ |
| 2309 | #define TM 0xff00 /* Time from address valid to DIOR/DIOW */ |
| 2310 | |
| 2311 | /* Bit masks for ATAPI_MULTI_TIM_1 */ |
| 2312 | |
| 2313 | #define TKW 0xff /* Selects DIOW negated pulsewidth */ |
| 2314 | #define TKR 0xff00 /* Selects DIOR negated pulsewidth */ |
| 2315 | |
| 2316 | /* Bit masks for ATAPI_MULTI_TIM_2 */ |
| 2317 | |
| 2318 | #define TH 0xff /* Selects DIOW data hold */ |
| 2319 | #define TEOC 0xff00 /* Selects end of cycle for DMA */ |
| 2320 | |
| 2321 | /* Bit masks for ATAPI_ULTRA_TIM_0 */ |
| 2322 | |
| 2323 | #define TACK 0xff /* Selects setup and hold times for TACK */ |
| 2324 | #define TENV 0xff00 /* Selects envelope time */ |
| 2325 | |
| 2326 | /* Bit masks for ATAPI_ULTRA_TIM_1 */ |
| 2327 | |
| 2328 | #define TDVS 0xff /* Selects data valid setup time */ |
| 2329 | #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ |
| 2330 | |
| 2331 | /* Bit masks for ATAPI_ULTRA_TIM_2 */ |
| 2332 | |
| 2333 | #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ |
| 2334 | #define TMLI 0xff00 /* Selects interlock time */ |
| 2335 | |
| 2336 | /* Bit masks for ATAPI_ULTRA_TIM_3 */ |
| 2337 | |
| 2338 | #define TZAH 0xff /* Selects minimum delay required for output */ |
| 2339 | #define READY_PAUSE 0xff00 /* Selects ready to pause */ |
| 2340 | |
| 2341 | /* Bit masks for TIMER_ENABLE1 */ |
| 2342 | |
| 2343 | #define TIMEN8 0x1 /* Timer 8 Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2344 | #define TIMEN9 0x2 /* Timer 9 Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2345 | #define TIMEN10 0x4 /* Timer 10 Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2346 | |
| 2347 | /* Bit masks for TIMER_DISABLE1 */ |
| 2348 | |
| 2349 | #define TIMDIS8 0x1 /* Timer 8 Disable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2350 | #define TIMDIS9 0x2 /* Timer 9 Disable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2351 | #define TIMDIS10 0x4 /* Timer 10 Disable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2352 | |
| 2353 | /* Bit masks for TIMER_STATUS1 */ |
| 2354 | |
| 2355 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2356 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2357 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2358 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2359 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2360 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2361 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2362 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2363 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2364 | |
| 2365 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ |
| 2366 | |
| 2367 | /* Bit masks for USB_FADDR */ |
| 2368 | |
| 2369 | #define FUNCTION_ADDRESS 0x7f /* Function address */ |
| 2370 | |
| 2371 | /* Bit masks for USB_POWER */ |
| 2372 | |
| 2373 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2374 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2375 | #define RESUME_MODE 0x4 /* DMA Mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2376 | #define RESET 0x8 /* Reset indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2377 | #define HS_MODE 0x10 /* High Speed mode indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2378 | #define HS_ENABLE 0x20 /* high Speed Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2379 | #define SOFT_CONN 0x40 /* Soft connect */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2380 | #define ISO_UPDATE 0x80 /* Isochronous update */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2381 | |
| 2382 | /* Bit masks for USB_INTRTX */ |
| 2383 | |
| 2384 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2385 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2386 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2387 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2388 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2389 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2390 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2391 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2392 | |
| 2393 | /* Bit masks for USB_INTRRX */ |
| 2394 | |
| 2395 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2396 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2397 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2398 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2399 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2400 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2401 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2402 | |
| 2403 | /* Bit masks for USB_INTRTXE */ |
| 2404 | |
| 2405 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2406 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2407 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2408 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2409 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2410 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2411 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2412 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2413 | |
| 2414 | /* Bit masks for USB_INTRRXE */ |
| 2415 | |
| 2416 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2417 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2418 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2419 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2420 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2421 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2422 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2423 | |
| 2424 | /* Bit masks for USB_INTRUSB */ |
| 2425 | |
| 2426 | #define SUSPEND_B 0x1 /* Suspend indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2427 | #define RESUME_B 0x2 /* Resume indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2428 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2429 | #define SOF_B 0x8 /* Start of frame */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2430 | #define CONN_B 0x10 /* Connection indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2431 | #define DISCON_B 0x20 /* Disconnect indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2432 | #define SESSION_REQ_B 0x40 /* Session Request */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2433 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2434 | |
| 2435 | /* Bit masks for USB_INTRUSBE */ |
| 2436 | |
| 2437 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2438 | #define RESUME_BE 0x2 /* Resume indicator int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2439 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2440 | #define SOF_BE 0x8 /* Start of frame int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2441 | #define CONN_BE 0x10 /* Connection indicator int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2442 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2443 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2444 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2445 | |
| 2446 | /* Bit masks for USB_FRAME */ |
| 2447 | |
| 2448 | #define FRAME_NUMBER 0x7ff /* Frame number */ |
| 2449 | |
| 2450 | /* Bit masks for USB_INDEX */ |
| 2451 | |
| 2452 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ |
| 2453 | |
| 2454 | /* Bit masks for USB_GLOBAL_CTL */ |
| 2455 | |
| 2456 | #define GLOBAL_ENA 0x1 /* enables USB module */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2457 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2458 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2459 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2460 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2461 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2462 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2463 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2464 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2465 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2466 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2467 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2468 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2469 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2470 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2471 | |
| 2472 | /* Bit masks for USB_OTG_DEV_CTL */ |
| 2473 | |
| 2474 | #define SESSION 0x1 /* session indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2475 | #define HOST_REQ 0x2 /* Host negotiation request */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2476 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2477 | #define VBUS0 0x8 /* Vbus level indicator[0] */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2478 | #define VBUS1 0x10 /* Vbus level indicator[1] */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2479 | #define LSDEV 0x20 /* Low-speed indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2480 | #define FSDEV 0x40 /* Full or High-speed indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2481 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2482 | |
| 2483 | /* Bit masks for USB_OTG_VBUS_IRQ */ |
| 2484 | |
| 2485 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2486 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2487 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2488 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2489 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2490 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2491 | |
| 2492 | /* Bit masks for USB_OTG_VBUS_MASK */ |
| 2493 | |
| 2494 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2495 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2496 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2497 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2498 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2499 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2500 | |
| 2501 | /* Bit masks for USB_CSR0 */ |
| 2502 | |
| 2503 | #define RXPKTRDY 0x1 /* data packet receive indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2504 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2505 | #define STALL_SENT 0x4 /* STALL handshake sent */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2506 | #define DATAEND 0x8 /* Data end indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2507 | #define SETUPEND 0x10 /* Setup end */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2508 | #define SENDSTALL 0x20 /* Send STALL handshake */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2509 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2510 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2511 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2512 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2513 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2514 | #define ERROR_H 0x10 /* timeout error indicator host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2515 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2516 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2517 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2518 | |
| 2519 | /* Bit masks for USB_COUNT0 */ |
| 2520 | |
| 2521 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ |
| 2522 | |
| 2523 | /* Bit masks for USB_NAKLIMIT0 */ |
| 2524 | |
| 2525 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ |
| 2526 | |
| 2527 | /* Bit masks for USB_TX_MAX_PACKET */ |
| 2528 | |
| 2529 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ |
| 2530 | |
| 2531 | /* Bit masks for USB_RX_MAX_PACKET */ |
| 2532 | |
| 2533 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ |
| 2534 | |
| 2535 | /* Bit masks for USB_TXCSR */ |
| 2536 | |
| 2537 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2538 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2539 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2540 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2541 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2542 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2543 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2544 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2545 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2546 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2547 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2548 | #define ISO_T 0x4000 /* enable Isochronous transfers */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2549 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2550 | #define ERROR_TH 0x4 /* error condition host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2551 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2552 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2553 | |
| 2554 | /* Bit masks for USB_TXCOUNT */ |
| 2555 | |
| 2556 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
| 2557 | |
| 2558 | /* Bit masks for USB_RXCSR */ |
| 2559 | |
| 2560 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2561 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2562 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2563 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2564 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2565 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2566 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2567 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2568 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2569 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2570 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2571 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2572 | #define ISO_R 0x4000 /* enable Isochronous transfers */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2573 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2574 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2575 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2576 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2577 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2578 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2579 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2580 | |
| 2581 | /* Bit masks for USB_RXCOUNT */ |
| 2582 | |
| 2583 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ |
| 2584 | |
| 2585 | /* Bit masks for USB_TXTYPE */ |
| 2586 | |
| 2587 | #define TARGET_EP_NO_T 0xf /* EP number */ |
| 2588 | #define PROTOCOL_T 0xc /* transfer type */ |
| 2589 | |
| 2590 | /* Bit masks for USB_TXINTERVAL */ |
| 2591 | |
| 2592 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ |
| 2593 | |
| 2594 | /* Bit masks for USB_RXTYPE */ |
| 2595 | |
| 2596 | #define TARGET_EP_NO_R 0xf /* EP number */ |
| 2597 | #define PROTOCOL_R 0xc /* transfer type */ |
| 2598 | |
| 2599 | /* Bit masks for USB_RXINTERVAL */ |
| 2600 | |
| 2601 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ |
| 2602 | |
| 2603 | /* Bit masks for USB_DMA_INTERRUPT */ |
| 2604 | |
| 2605 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2606 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2607 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2608 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2609 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2610 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2611 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2612 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2613 | |
| 2614 | /* Bit masks for USB_DMAxCONTROL */ |
| 2615 | |
| 2616 | #define DMA_ENA 0x1 /* DMA enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2617 | #define DIRECTION 0x2 /* direction of DMA transfer */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2618 | #define MODE 0x4 /* DMA Bus error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2619 | #define INT_ENA 0x8 /* Interrupt enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2620 | #define EPNUM 0xf0 /* EP number */ |
| 2621 | #define BUSERROR 0x100 /* DMA Bus error */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2622 | |
| 2623 | /* Bit masks for USB_DMAxADDRHIGH */ |
| 2624 | |
| 2625 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ |
| 2626 | |
| 2627 | /* Bit masks for USB_DMAxADDRLOW */ |
| 2628 | |
| 2629 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ |
| 2630 | |
| 2631 | /* Bit masks for USB_DMAxCOUNTHIGH */ |
| 2632 | |
| 2633 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ |
| 2634 | |
| 2635 | /* Bit masks for USB_DMAxCOUNTLOW */ |
| 2636 | |
| 2637 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ |
| 2638 | |
| 2639 | /* Bit masks for HMDMAx_CONTROL */ |
| 2640 | |
| 2641 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2642 | #define REP 0x2 /* Handshake MDMA Request Polarity */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2643 | #define UTE 0x8 /* Urgency Threshold Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2644 | #define OIE 0x10 /* Overflow Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2645 | #define BDIE 0x20 /* Block Done Interrupt Enable */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2646 | #define MBDI 0x40 /* Mask Block Done Interrupt */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2647 | #define DRQ 0x300 /* Handshake MDMA Request Type */ |
| 2648 | #define RBC 0x1000 /* Force Reload of BCOUNT */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2649 | #define PS 0x2000 /* Pin Status */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2650 | #define OI 0x4000 /* Overflow Interrupt Generated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2651 | #define BDI 0x8000 /* Block Done Interrupt Generated */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 2652 | |
| 2653 | /* ******************************************* */ |
| 2654 | /* MULTI BIT MACRO ENUMERATIONS */ |
| 2655 | /* ******************************************* */ |
| 2656 | |
| 2657 | /* ************************ */ |
| 2658 | /* MXVR Address Offsets */ |
| 2659 | /* ************************ */ |
| 2660 | |
| 2661 | /* Control Message Receive Buffer (CMRB) Address Offsets */ |
| 2662 | |
| 2663 | #define CMRB_STRIDE 0x00000016lu |
| 2664 | |
| 2665 | #define CMRB_DST_OFFSET 0x00000000lu |
| 2666 | #define CMRB_SRC_OFFSET 0x00000002lu |
| 2667 | #define CMRB_DATA_OFFSET 0x00000005lu |
| 2668 | |
| 2669 | /* Control Message Transmit Buffer (CMTB) Address Offsets */ |
| 2670 | |
| 2671 | #define CMTB_PRIO_OFFSET 0x00000000lu |
| 2672 | #define CMTB_DST_OFFSET 0x00000002lu |
| 2673 | #define CMTB_SRC_OFFSET 0x00000004lu |
| 2674 | #define CMTB_TYPE_OFFSET 0x00000006lu |
| 2675 | #define CMTB_DATA_OFFSET 0x00000007lu |
| 2676 | |
| 2677 | #define CMTB_ANSWER_OFFSET 0x0000000Alu |
| 2678 | |
| 2679 | #define CMTB_STAT_N_OFFSET 0x00000018lu |
| 2680 | #define CMTB_STAT_A_OFFSET 0x00000016lu |
| 2681 | #define CMTB_STAT_D_OFFSET 0x0000000Elu |
| 2682 | #define CMTB_STAT_R_OFFSET 0x00000014lu |
| 2683 | #define CMTB_STAT_W_OFFSET 0x00000014lu |
| 2684 | #define CMTB_STAT_G_OFFSET 0x00000014lu |
| 2685 | |
| 2686 | /* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ |
| 2687 | |
| 2688 | #define APRB_STRIDE 0x00000400lu |
| 2689 | |
| 2690 | #define APRB_DST_OFFSET 0x00000000lu |
| 2691 | #define APRB_LEN_OFFSET 0x00000002lu |
| 2692 | #define APRB_SRC_OFFSET 0x00000004lu |
| 2693 | #define APRB_DATA_OFFSET 0x00000006lu |
| 2694 | |
| 2695 | /* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ |
| 2696 | |
| 2697 | #define APTB_PRIO_OFFSET 0x00000000lu |
| 2698 | #define APTB_DST_OFFSET 0x00000002lu |
| 2699 | #define APTB_LEN_OFFSET 0x00000004lu |
| 2700 | #define APTB_SRC_OFFSET 0x00000006lu |
| 2701 | #define APTB_DATA_OFFSET 0x00000008lu |
| 2702 | |
| 2703 | /* Remote Read Buffer (RRDB) Address Offsets */ |
| 2704 | |
| 2705 | #define RRDB_WADDR_OFFSET 0x00000100lu |
| 2706 | #define RRDB_WLEN_OFFSET 0x00000101lu |
| 2707 | |
| 2708 | /* **************** */ |
| 2709 | /* MXVR Macros */ |
| 2710 | /* **************** */ |
| 2711 | |
| 2712 | /* MXVR_CONFIG Macros */ |
| 2713 | |
| 2714 | #define SET_MSB(x) ( ( (x) & 0xF ) << 9) |
| 2715 | |
| 2716 | /* MXVR_INT_STAT_1 Macros */ |
| 2717 | |
| 2718 | #define DONEX(x) (0x00000002 << (4 * (x))) |
| 2719 | #define HDONEX(x) (0x00000001 << (4 * (x))) |
| 2720 | |
| 2721 | /* MXVR_INT_EN_1 Macros */ |
| 2722 | |
| 2723 | #define DONEENX(x) (0x00000002 << (4 * (x))) |
| 2724 | #define HDONEENX(x) (0x00000001 << (4 * (x))) |
| 2725 | |
| 2726 | /* MXVR_CDRPLL_CTL Macros */ |
| 2727 | |
| 2728 | #define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16) |
| 2729 | |
| 2730 | /* MXVR_FMPLL_CTL Macros */ |
| 2731 | |
| 2732 | #define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24) |
| 2733 | #define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24) |
| 2734 | |
| 2735 | #endif /* _DEF_BF549_H */ |