blob: b4ca20048446e498f327f280ea68500bb72d8759 [file] [log] [blame]
Paul Mundt253b0882009-05-13 17:38:11 +09001#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <asm/clock.h>
4
5static struct clk master_clk = {
6 .name = "master_clk",
7 .flags = CLK_ENABLE_ON_INIT,
8 .rate = CONFIG_SH_PCLK_FREQ,
9};
10
11static struct clk peripheral_clk = {
12 .name = "peripheral_clk",
13 .parent = &master_clk,
14 .flags = CLK_ENABLE_ON_INIT,
15};
16
17static struct clk bus_clk = {
18 .name = "bus_clk",
19 .parent = &master_clk,
20 .flags = CLK_ENABLE_ON_INIT,
21};
22
23static struct clk cpu_clk = {
24 .name = "cpu_clk",
25 .parent = &master_clk,
26 .flags = CLK_ENABLE_ON_INIT,
27};
28
29/*
30 * The ordering of these clocks matters, do not change it.
31 */
32static struct clk *onchip_clocks[] = {
33 &master_clk,
34 &peripheral_clk,
35 &bus_clk,
36 &cpu_clk,
37};
38
39int __init __deprecated cpg_clk_init(void)
40{
41 int i, ret = 0;
42
43 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
44 struct clk *clk = onchip_clocks[i];
45 arch_init_clk_ops(&clk->ops, i);
46 if (clk->ops)
47 ret |= clk_register(clk);
48 }
49
50 return ret;
51}
52
53/*
54 * Placeholder for compatability, until the lazy CPUs do this
55 * on their own.
56 */
57int __init __weak arch_clk_init(void)
58{
59 return cpg_clk_init();
60}