Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 25918f9811eae1d657db2bccdfcb077038d9454c / . / arch / arm / mach-imx / clk-imx51-imx53.c
blob: f6086693ebd2aa665e29fc7a5d5623caeb0d3d53 [file] [log] [blame]
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/of.h>
15#include <linux/err.h>
16
17#include <mach/hardware.h>
18#include <mach/common.h>
19
20#include "crm-regs-imx5.h"
21#include "clk.h"
22
23/* Low-power Audio Playback Mode clock */
24static const char *lp_apm_sel[] = { "osc", };
25
26/* This is used multiple times */
27static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
28static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
29static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
30static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
31static const char *per_root_sel[] = { "per_podf", "ipg", };
32static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
33static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]34static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
35static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
36static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
37static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
38static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]39static const char *emi_slow_sel[] = { "main_bus", "ahb", };
40static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
41static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
42static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
43static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
44static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
45static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
46static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
47static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
48static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
49static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
50static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
51static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
52
53enum imx5_clks {
54 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
55 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
56 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
57 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
58 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
59 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
60 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
Alexander Shiyan0f3557c2012-07-12 19:39:30 +0400[diff] [blame]61 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]62 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
63 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
64 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
65 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
66 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
67 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
68 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
69 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
70 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
71 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
72 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
73 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
74 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
75 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
76 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
77 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
78 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]79 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
80 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
81 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
82 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
Alexander Shiyand1e9e0e2012-07-12 19:39:28 +0400[diff] [blame]84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]85 clk_max
86};
87
88static struct clk *clk[clk_max];
89
90static void __init mx5_clocks_common_init(unsigned long rate_ckil,
91 unsigned long rate_osc, unsigned long rate_ckih1,
92 unsigned long rate_ckih2)
93{
94 int i;
95
96 clk[dummy] = imx_clk_fixed("dummy", 0);
97 clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
98 clk[osc] = imx_clk_fixed("osc", rate_osc);
99 clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
100 clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
101
102 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
103 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
104 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
105 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
106 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
107 main_bus_sel, ARRAY_SIZE(main_bus_sel));
Sascha Hauerc040be02012-05-16 12:01:40 +0200[diff] [blame]108 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]109 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
110 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
111 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
112 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
Sascha Hauerc040be02012-05-16 12:01:40 +0200[diff] [blame]113 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]114 per_root_sel, ARRAY_SIZE(per_root_sel));
115 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
116 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
117 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
118 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
119 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
120 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
121 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
122 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
123 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
124 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
125 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
126 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
127 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
128 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
129 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
130
131 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
132 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
133 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
134 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
135 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
136 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
137 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
138 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
139 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
140 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
141
142 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
143 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
144 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
145 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
146 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
147 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
148 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
149 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
150 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
151 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
152 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
153 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
154 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
155 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
156 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
157 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
158 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
159 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
160 clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
161 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
162 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
163 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
164 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
165 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
166 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
167 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
168 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
169 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
170 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]171 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
Alexander Shiyan796b72c2012-07-12 19:39:29 +0400[diff] [blame]172 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]173 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
Alexander Shiyan796b72c2012-07-12 19:39:29 +0400[diff] [blame]174 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
Alexander Shiyan0f3557c2012-07-12 19:39:30 +0400[diff] [blame]175 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
176 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]177 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
178 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
179 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
180 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
181 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
182 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
183 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
184 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
185 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
186 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
187 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
188 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
189 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
190 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
191 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
192 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
193 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
194 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
195 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
196 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
197 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
198 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
199 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
200 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
201 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
202 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
203 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
204 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
205 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
206 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
207 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
208
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]209 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
210 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
211 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
212 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
213 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
214 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
215 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
216 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
217 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
218 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
219 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
220 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
221 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
222 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
223 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
224 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
225 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
226 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
227 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
228 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
229 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
Alexander Shiyand1e9e0e2012-07-12 19:39:28 +0400[diff] [blame]230 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
231 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
232 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
233 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]234
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]235 for (i = 0; i < ARRAY_SIZE(clk); i++)
236 if (IS_ERR(clk[i]))
237 pr_err("i.MX5 clk %d: register failed with %ld\n",
238 i, PTR_ERR(clk[i]));
239
Alexander Shiyan0f3557c2012-07-12 19:39:30 +0400[diff] [blame]240 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]241 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
242 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
243 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
244 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
245 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
246 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
247 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
248 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
249 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
250 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
251 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
252 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
253 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
254 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
255 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
Alexander Shiyane0c29dc2012-07-12 19:39:31 +0400[diff] [blame]256 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]257 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
258 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
259 clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
260 clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
261 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
262 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
263 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
264 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
265 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
266 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
267 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
268 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
269 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
270 clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
271 clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
272 clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
273 clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
274 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
275 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
276 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]277 clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
278 clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]279 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
280 clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
281 clk_register_clkdev(clk[iim_gate], "iim", NULL);
282 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
283 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
284 clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
285 clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
286 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
Robert Leeaa96a182012-05-21 17:50:27 -0500[diff] [blame]287 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
Alexander Shiyand1e9e0e2012-07-12 19:39:28 +0400[diff] [blame]288 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
289 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
290 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
291 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]292
293 /* Set SDHC parents to be PLL2 */
294 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
295 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
296
297 /* move usb phy clk to 24MHz */
298 clk_set_parent(clk[usb_phy_sel], clk[osc]);
299
300 clk_prepare_enable(clk[gpc_dvfs]);
301 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
302 clk_prepare_enable(clk[aips_tz1]);
303 clk_prepare_enable(clk[aips_tz2]); /* fec */
304 clk_prepare_enable(clk[spba]);
305 clk_prepare_enable(clk[emi_fast_gate]); /* fec */
306 clk_prepare_enable(clk[tmax1]);
307 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
308 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
309}
310
311int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
312 unsigned long rate_ckih1, unsigned long rate_ckih2)
313{
314 int i;
315
316 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
317 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
318 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
319 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
320 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
321 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
322 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
323 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
324 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
325 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
326 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
327 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
328 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
329 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
330 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
331 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
332 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
333 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
334 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
335 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
336 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
337
338 for (i = 0; i < ARRAY_SIZE(clk); i++)
339 if (IS_ERR(clk[i]))
340 pr_err("i.MX51 clk %d: register failed with %ld\n",
341 i, PTR_ERR(clk[i]));
342
343 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
344
345 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx-i2c.2");
346 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
347 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
348 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]349 clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
350 clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
351 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
352 clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
353 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
354 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
355 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
356 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
357 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
358 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
359 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
360 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
361 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
362 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
363 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
364 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
365 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]366 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
367 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
368 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]369
370 /* set the usboh3 parent to pll2_sw */
371 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
372
373 /* set SDHC root clock to 166.25MHZ*/
374 clk_set_rate(clk[esdhc_a_podf], 166250000);
375 clk_set_rate(clk[esdhc_b_podf], 166250000);
376
377 /* System timer */
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200[diff] [blame]378 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]379
380 clk_prepare_enable(clk[iim_gate]);
381 imx_print_silicon_rev("i.MX51", mx51_revision());
382 clk_disable_unprepare(clk[iim_gate]);
383
384 return 0;
385}
386
387int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
388 unsigned long rate_ckih1, unsigned long rate_ckih2)
389{
390 int i;
391 unsigned long r;
392
393 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
394 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
395 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
396 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
397
398 clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
399 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
400 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
401 clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
402 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
403 clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
404 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
405 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
406 clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
407 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
408 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
409 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
410 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
411 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
412 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
413 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
414 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
415 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
416 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
417 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
418 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
419 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
420 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
421 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
422 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
423 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
424 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
425 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
426
427 for (i = 0; i < ARRAY_SIZE(clk); i++)
428 if (IS_ERR(clk[i]))
429 pr_err("i.MX53 clk %d: register failed with %ld\n",
430 i, PTR_ERR(clk[i]));
431
432 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
433
434 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
435 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
436 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
437 clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
438 clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
439 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
440 clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
441 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
442 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
443 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
444 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
445 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
446 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
447 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
448 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
449 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
450 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
451 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
452 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
453 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
Shawn Guo13b3a072012-05-03 20:15:57 +0800[diff] [blame]454 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
455 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
456 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]457
458 /* set SDHC root clock to 200MHZ*/
459 clk_set_rate(clk[esdhc_a_podf], 200000000);
460 clk_set_rate(clk[esdhc_b_podf], 200000000);
461
462 /* System timer */
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200[diff] [blame]463 mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
Sascha Hauerb8d41762012-03-19 12:36:57 +0100[diff] [blame]464
465 clk_prepare_enable(clk[iim_gate]);
466 imx_print_silicon_rev("i.MX53", mx53_revision());
467 clk_disable_unprepare(clk[iim_gate]);
468
469 r = clk_round_rate(clk[usboh3_per_gate], 54000000);
470 clk_set_rate(clk[usboh3_per_gate], r);
471
472 return 0;
473}
474
475#ifdef CONFIG_OF
476static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
477 unsigned long *ckih1, unsigned long *ckih2)
478{
479 struct device_node *np;
480
481 /* retrieve the freqency of fixed clocks from device tree */
482 for_each_compatible_node(np, NULL, "fixed-clock") {
483 u32 rate;
484 if (of_property_read_u32(np, "clock-frequency", &rate))
485 continue;
486
487 if (of_device_is_compatible(np, "fsl,imx-ckil"))
488 *ckil = rate;
489 else if (of_device_is_compatible(np, "fsl,imx-osc"))
490 *osc = rate;
491 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
492 *ckih1 = rate;
493 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
494 *ckih2 = rate;
495 }
496}
497
498int __init mx51_clocks_init_dt(void)
499{
500 unsigned long ckil, osc, ckih1, ckih2;
501
502 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
503 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
504}
505
506int __init mx53_clocks_init_dt(void)
507{
508 unsigned long ckil, osc, ckih1, ckih2;
509
510 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
511 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
512}
513#endif