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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
Kevin Hilman8bd22942009-05-28 10:56:16 -07002 * (C) Copyright 2007
3 * Texas Instruments
4 * Karthik Dasu <karthik-dp@ti.com>
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#include <linux/linkage.h>
26#include <asm/assembler.h>
Jean Pihetb4b36fd2010-12-18 16:44:42 +010027#include <plat/sram.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070028#include <mach/io.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070029
Paul Walmsley59fb6592010-12-21 15:30:55 -070030#include "cm2xxx_3xxx.h"
31#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070032#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060033#include "control.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070034
Jean Pihetfe360e12010-12-18 16:44:43 +010035/*
36 * Registers access definitions
37 */
38#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
39#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
40 (SDRC_SCRATCHPAD_SEM_OFFS)
41#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
42 OMAP3430_PM_PREPWSTST
Abhijit Pagare37903002010-01-26 20:12:51 -070043#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +020044#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -060045#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
Jean Pihetfe360e12010-12-18 16:44:43 +010046#define SRAM_BASE_P OMAP3_SRAM_PA
47#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
48#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
49 OMAP36XX_CONTROL_MEM_RTA_CTRL)
50
51/* Move this as correct place is available */
52#define SCRATCHPAD_MEM_OFFS 0x310
53#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
54 OMAP343X_CONTROL_MEM_WKUP +\
55 SCRATCHPAD_MEM_OFFS)
Kevin Hilman8bd22942009-05-28 10:56:16 -070056#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
Tero Kristo0795a752008-10-13 17:58:50 +030057#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
58#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
59#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
60#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
61#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
62#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
63#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +020064#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
65#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
Kevin Hilman8bd22942009-05-28 10:56:16 -070066
Dave Martindd313942011-03-04 15:33:57 +000067/*
68 * This file needs be built unconditionally as ARM to interoperate correctly
69 * with non-Thumb-2-capable firmware.
70 */
71 .arm
Rajendra Nayaka89b6f02009-05-28 18:13:06 +053072
Jean Pihetd3cdfd22010-12-18 16:44:41 +010073/*
74 * API functions
75 */
Rajendra Nayaka89b6f02009-05-28 18:13:06 +053076
Jean Pihetf7dfe3d2010-12-18 16:44:45 +010077/*
78 * The "get_*restore_pointer" functions are used to provide a
79 * physical restore address where the ROM code jumps while waking
80 * up from MPU OFF/OSWR state.
81 * The restore pointer is stored into the scratchpad.
82 */
83
Kevin Hilman8bd22942009-05-28 10:56:16 -070084 .text
85/* Function call to get the restore pointer for resume from OFF */
86ENTRY(get_restore_pointer)
Jean Pihetbb1c9032010-12-18 16:49:57 +010087 stmfd sp!, {lr} @ save registers on stack
Kevin Hilman8bd22942009-05-28 10:56:16 -070088 adr r0, restore
Jean Pihetbb1c9032010-12-18 16:49:57 +010089 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +000090ENDPROC(get_restore_pointer)
91 .align
Kevin Hilman8bd22942009-05-28 10:56:16 -070092ENTRY(get_restore_pointer_sz)
Jean Pihetbb1c9032010-12-18 16:49:57 +010093 .word . - get_restore_pointer
Jean Pihet1e81bc02010-12-18 16:44:44 +010094
Nishanth Menon458e9992010-12-20 14:05:06 -060095 .text
96/* Function call to get the restore pointer for 3630 resume from OFF */
97ENTRY(get_omap3630_restore_pointer)
Jean Pihetbb1c9032010-12-18 16:49:57 +010098 stmfd sp!, {lr} @ save registers on stack
Nishanth Menon458e9992010-12-20 14:05:06 -060099 adr r0, restore_3630
Jean Pihetbb1c9032010-12-18 16:49:57 +0100100 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +0000101ENDPROC(get_omap3630_restore_pointer)
102 .align
Nishanth Menon458e9992010-12-20 14:05:06 -0600103ENTRY(get_omap3630_restore_pointer_sz)
Jean Pihetbb1c9032010-12-18 16:49:57 +0100104 .word . - get_omap3630_restore_pointer
Tero Kristo0795a752008-10-13 17:58:50 +0300105
106 .text
Jean Pihet1e81bc02010-12-18 16:44:44 +0100107/* Function call to get the restore pointer for ES3 to resume from OFF */
108ENTRY(get_es3_restore_pointer)
109 stmfd sp!, {lr} @ save registers on stack
110 adr r0, restore_es3
111 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +0000112ENDPROC(get_es3_restore_pointer)
113 .align
Jean Pihet1e81bc02010-12-18 16:44:44 +0100114ENTRY(get_es3_restore_pointer_sz)
115 .word . - get_es3_restore_pointer
116
117 .text
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600118/*
119 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
Jean Pihet1e81bc02010-12-18 16:44:44 +0100120 * This function sets up a flag that will allow for this toggling to take
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100121 * place on 3630. Hopefully some version in the future may not need this.
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600122 */
123ENTRY(enable_omap3630_toggle_l2_on_restore)
Jean Pihetbb1c9032010-12-18 16:49:57 +0100124 stmfd sp!, {lr} @ save registers on stack
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600125 /* Setup so that we will disable and enable l2 */
126 mov r1, #0x1
Dave Martindd313942011-03-04 15:33:57 +0000127 adrl r2, l2dis_3630 @ may be too distant for plain adr
128 str r1, [r2]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100129 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +0000130ENDPROC(enable_omap3630_toggle_l2_on_restore)
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600131
Jean Pihetbb1c9032010-12-18 16:49:57 +0100132 .text
Tero Kristo27d59a42008-10-13 13:15:00 +0300133/* Function to call rom code to save secure ram context */
Jean Pihetb6338bd2011-02-02 16:38:06 +0100134 .align 3
Tero Kristo27d59a42008-10-13 13:15:00 +0300135ENTRY(save_secure_ram_context)
Russell King857c1b82011-06-22 12:44:32 +0100136 stmfd sp!, {r4 - r11, lr} @ save registers on stack
Tero Kristo27d59a42008-10-13 13:15:00 +0300137 adr r3, api_params @ r3 points to parameters
138 str r0, [r3,#0x4] @ r0 has sdram address
139 ldr r12, high_mask
140 and r3, r3, r12
141 ldr r12, sram_phy_addr_mask
142 orr r3, r3, r12
143 mov r0, #25 @ set service ID for PPA
144 mov r12, r0 @ copy secure service ID in r12
145 mov r1, #0 @ set task id for ROM code in r1
Kalle Jokiniemiba50ea72009-03-26 15:59:00 +0200146 mov r2, #4 @ set some flags in r2, r6
Tero Kristo27d59a42008-10-13 13:15:00 +0300147 mov r6, #0xff
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530148 dsb @ data write barrier
149 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000150 smc #1 @ call SMI monitor (smi #1)
Tero Kristo27d59a42008-10-13 13:15:00 +0300151 nop
152 nop
153 nop
154 nop
Russell King857c1b82011-06-22 12:44:32 +0100155 ldmfd sp!, {r4 - r11, pc}
Dave Martindd313942011-03-04 15:33:57 +0000156 .align
Tero Kristo27d59a42008-10-13 13:15:00 +0300157sram_phy_addr_mask:
158 .word SRAM_BASE_P
159high_mask:
160 .word 0xffff
161api_params:
162 .word 0x4, 0x0, 0x0, 0x1, 0x1
Dave Martindd313942011-03-04 15:33:57 +0000163ENDPROC(save_secure_ram_context)
Tero Kristo27d59a42008-10-13 13:15:00 +0300164ENTRY(save_secure_ram_context_sz)
165 .word . - save_secure_ram_context
166
Kevin Hilman8bd22942009-05-28 10:56:16 -0700167/*
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100168 * ======================
169 * == Idle entry point ==
170 * ======================
171 */
172
173/*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700174 * Forces OMAP into idle state
175 *
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100176 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
177 * and executes the WFI instruction. Calling WFI effectively changes the
178 * power domains states to the desired target power states.
Kevin Hilman8bd22942009-05-28 10:56:16 -0700179 *
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100180 *
181 * Notes:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100182 * - this code gets copied to internal SRAM at boot and after wake-up
183 * from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100184 * - when the OMAP wakes up it continues at different execution points
185 * depending on the low power mode (non-OFF vs OFF modes),
186 * cf. 'Resume path for xxx mode' comments.
Kevin Hilman8bd22942009-05-28 10:56:16 -0700187 */
Jean Pihetb6338bd2011-02-02 16:38:06 +0100188 .align 3
Kevin Hilman8bd22942009-05-28 10:56:16 -0700189ENTRY(omap34xx_cpu_suspend)
Russell King857c1b82011-06-22 12:44:32 +0100190 stmfd sp!, {r4 - r11, lr} @ save registers on stack
Jean Pihetd3cdfd22010-12-18 16:44:41 +0100191
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100192 /*
Santosh Shilimkarc9749a32011-01-23 19:33:53 +0530193 * r0 contains CPU context save/restore pointer in sdram
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100194 * r1 contains information about saving context:
195 * 0 - No context lost
196 * 1 - Only L1 and logic lost
Santosh Shilimkarc9749a32011-01-23 19:33:53 +0530197 * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
198 * 3 - Both L1 and L2 lost and logic lost
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100199 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700200
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100201 /* Directly jump to WFI is the context save is not required */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700202 cmp r1, #0x0
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100203 beq omap3_do_wfi
204
205 /* Otherwise fall through to the save context code */
206save_context_wfi:
207 mov r8, r0 @ Store SDRAM address in r8
208 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
209 mov r4, #0x1 @ Number of parameters for restore call
210 stmia r8!, {r4-r5} @ Push parameters for restore call
211 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
212 stmia r8!, {r4-r5} @ Push parameters for restore call
213
214 /* Check what that target sleep state is from r1 */
215 cmp r1, #0x2 @ Only L2 lost, no need to save context
216 beq clean_caches
217
218l1_logic_lost:
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530219 mov r4, sp @ Store sp
220 mrs r5, spsr @ Store spsr
221 mov r6, lr @ Store lr
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100222 stmia r8!, {r4-r6}
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100223
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530224 mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
225 mrc p15, 0, r5, c2, c0, 0 @ TTBR0
226 mrc p15, 0, r6, c2, c0, 1 @ TTBR1
227 mrc p15, 0, r7, c2, c0, 2 @ TTBCR
228 stmia r8!, {r4-r7}
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100229
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530230 mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
231 mrc p15, 0, r5, c10, c2, 0 @ PRRR
232 mrc p15, 0, r6, c10, c2, 1 @ NMRR
233 stmia r8!,{r4-r6}
234
235 mrc p15, 0, r4, c13, c0, 1 @ Context ID
236 mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
237 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
238 mrs r7, cpsr @ Store current cpsr
239 stmia r8!, {r4-r7}
240
241 mrc p15, 0, r4, c1, c0, 0 @ save control register
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100242 stmia r8!, {r4}
243
244clean_caches:
245 /*
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100246 * jump out to kernel flush routine
247 * - reuse that code is better
248 * - it executes in a cached space so is faster than refetch per-block
249 * - should be faster and will change with kernel
250 * - 'might' have to copy address, load and jump to it
Santosh Shilimkar90625112011-01-23 22:51:09 +0530251 * Flush all data from the L1 data cache before disabling
252 * SCTLR.C bit.
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100253 */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100254 ldr r1, kernel_flush
255 mov lr, pc
256 bx r1
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100257
Santosh Shilimkar90625112011-01-23 22:51:09 +0530258 /*
259 * Clear the SCTLR.C bit to prevent further data cache
260 * allocation. Clearing SCTLR.C would make all the data accesses
261 * strongly ordered and would not hit the cache.
262 */
263 mrc p15, 0, r0, c1, c0, 0
264 bic r0, r0, #(1 << 2) @ Disable the C bit
265 mcr p15, 0, r0, c1, c0, 0
266 isb
267
268 /*
269 * Invalidate L1 data cache. Even though only invalidate is
270 * necessary exported flush API is used here. Doing clean
271 * on already clean cache would be almost NOP.
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100272 */
273 ldr r1, kernel_flush
Dave Martindd313942011-03-04 15:33:57 +0000274 blx r1
275 /*
276 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
277 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
278 * This sequence switches back to ARM. Note that .align may insert a
279 * nop: bx pc needs to be word-aligned in order to work.
280 */
281 THUMB( .thumb )
282 THUMB( .align )
283 THUMB( bx pc )
284 THUMB( nop )
285 .arm
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100286
287omap3_do_wfi:
288 ldr r4, sdrc_power @ read the SDRC_POWER register
289 ldr r5, [r4] @ read the contents of SDRC_POWER
290 orr r5, r5, #0x40 @ enable self refresh on idle req
291 str r5, [r4] @ write back to SDRC_POWER register
292
Kevin Hilman8bd22942009-05-28 10:56:16 -0700293 /* Data memory barrier and Data sync barrier */
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530294 dsb
295 dmb
Kevin Hilman8bd22942009-05-28 10:56:16 -0700296
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100297/*
298 * ===================================
299 * == WFI instruction => Enter idle ==
300 * ===================================
301 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700302 wfi @ wait for interrupt
303
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100304/*
305 * ===================================
306 * == Resume path for non-OFF modes ==
307 * ===================================
308 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700309 nop
310 nop
311 nop
312 nop
313 nop
314 nop
315 nop
316 nop
317 nop
318 nop
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200319 bl wait_sdrc_ok
Kevin Hilman8bd22942009-05-28 10:56:16 -0700320
Santosh Shilimkar90625112011-01-23 22:51:09 +0530321 mrc p15, 0, r0, c1, c0, 0
322 tst r0, #(1 << 2) @ Check C bit enabled?
323 orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
324 mcreq p15, 0, r0, c1, c0, 0
325 isb
326
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100327/*
328 * ===================================
329 * == Exit point from non-OFF modes ==
330 * ===================================
331 */
Russell King857c1b82011-06-22 12:44:32 +0100332 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100333
334
335/*
336 * ==============================
337 * == Resume path for OFF mode ==
338 * ==============================
339 */
340
341/*
342 * The restore_* functions are called by the ROM code
343 * when back from WFI in OFF mode.
344 * Cf. the get_*restore_pointer functions.
345 *
346 * restore_es3: applies to 34xx >= ES3.0
347 * restore_3630: applies to 36xx
348 * restore: common code for 3xxx
349 */
Tero Kristo0795a752008-10-13 17:58:50 +0300350restore_es3:
Tero Kristo0795a752008-10-13 17:58:50 +0300351 ldr r5, pm_prepwstst_core_p
352 ldr r4, [r5]
353 and r4, r4, #0x3
354 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
355 bne restore
356 adr r0, es3_sdrc_fix
357 ldr r1, sram_base
358 ldr r2, es3_sdrc_fix_sz
359 mov r2, r2, ror #2
360copy_to_sram:
361 ldmia r0!, {r3} @ val = *src
362 stmia r1!, {r3} @ *dst = val
363 subs r2, r2, #0x1 @ num_words--
364 bne copy_to_sram
365 ldr r1, sram_base
366 blx r1
Nishanth Menon458e9992010-12-20 14:05:06 -0600367 b restore
368
369restore_3630:
Nishanth Menon458e9992010-12-20 14:05:06 -0600370 ldr r1, pm_prepwstst_core_p
371 ldr r2, [r1]
372 and r2, r2, #0x3
373 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
374 bne restore
375 /* Disable RTA before giving control */
376 ldr r1, control_mem_rta
377 mov r2, #OMAP36XX_RTA_DISABLE
378 str r2, [r1]
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100379
380 /* Fall through to common code for the remaining logic */
381
Kevin Hilman8bd22942009-05-28 10:56:16 -0700382restore:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100383 /*
Russell King2637ce32011-06-22 12:54:41 +0100384 * Read the pwstctrl register to check the reason for mpu reset.
385 * This tells us what was lost.
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100386 */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100387 ldr r1, pm_pwstctrl_mpu
Kevin Hilman8bd22942009-05-28 10:56:16 -0700388 ldr r2, [r1]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100389 and r2, r2, #0x3
390 cmp r2, #0x0 @ Check if target power state was OFF or RET
Kevin Hilman8bd22942009-05-28 10:56:16 -0700391 bne logic_l1_restore
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600392
393 ldr r0, l2dis_3630
394 cmp r0, #0x1 @ should we disable L2 on 3630?
395 bne skipl2dis
396 mrc p15, 0, r0, c1, c0, 1
397 bic r0, r0, #2 @ disable L2 cache
398 mcr p15, 0, r0, c1, c0, 1
399skipl2dis:
Tero Kristo27d59a42008-10-13 13:15:00 +0300400 ldr r0, control_stat
401 ldr r1, [r0]
402 and r1, #0x700
403 cmp r1, #0x300
404 beq l2_inv_gp
Jean Pihetbb1c9032010-12-18 16:49:57 +0100405 mov r0, #40 @ set service ID for PPA
406 mov r12, r0 @ copy secure Service ID in r12
407 mov r1, #0 @ set task id for ROM code in r1
408 mov r2, #4 @ set some flags in r2, r6
Tero Kristo27d59a42008-10-13 13:15:00 +0300409 mov r6, #0xff
410 adr r3, l2_inv_api_params @ r3 points to dummy parameters
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530411 dsb @ data write barrier
412 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000413 smc #1 @ call SMI monitor (smi #1)
Tero Kristo27d59a42008-10-13 13:15:00 +0300414 /* Write to Aux control register to set some bits */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100415 mov r0, #42 @ set service ID for PPA
416 mov r12, r0 @ copy secure Service ID in r12
417 mov r1, #0 @ set task id for ROM code in r1
418 mov r2, #4 @ set some flags in r2, r6
Tero Kristo27d59a42008-10-13 13:15:00 +0300419 mov r6, #0xff
Tero Kristoa087cad2009-11-12 12:07:20 +0200420 ldr r4, scratchpad_base
Jean Pihetbb1c9032010-12-18 16:49:57 +0100421 ldr r3, [r4, #0xBC] @ r3 points to parameters
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530422 dsb @ data write barrier
423 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000424 smc #1 @ call SMI monitor (smi #1)
Tero Kristo27d59a42008-10-13 13:15:00 +0300425
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200426#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
427 /* Restore L2 aux control register */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100428 @ set service ID for PPA
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200429 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
Jean Pihetbb1c9032010-12-18 16:49:57 +0100430 mov r12, r0 @ copy service ID in r12
431 mov r1, #0 @ set task ID for ROM code in r1
432 mov r2, #4 @ set some flags in r2, r6
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200433 mov r6, #0xff
434 ldr r4, scratchpad_base
435 ldr r3, [r4, #0xBC]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100436 adds r3, r3, #8 @ r3 points to parameters
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530437 dsb @ data write barrier
438 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000439 smc #1 @ call SMI monitor (smi #1)
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200440#endif
Tero Kristo27d59a42008-10-13 13:15:00 +0300441 b logic_l1_restore
Jean Pihetbb1c9032010-12-18 16:49:57 +0100442
Dave Martindd313942011-03-04 15:33:57 +0000443 .align
Tero Kristo27d59a42008-10-13 13:15:00 +0300444l2_inv_api_params:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100445 .word 0x1, 0x00
Tero Kristo27d59a42008-10-13 13:15:00 +0300446l2_inv_gp:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700447 /* Execute smi to invalidate L2 cache */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100448 mov r12, #0x1 @ set up to invalidate L2
Dave Martin76d50012011-03-04 15:33:55 +0000449 smc #0 @ Call SMI monitor (smieq)
Tero Kristo27d59a42008-10-13 13:15:00 +0300450 /* Write to Aux control register to set some bits */
Tero Kristoa087cad2009-11-12 12:07:20 +0200451 ldr r4, scratchpad_base
452 ldr r3, [r4,#0xBC]
453 ldr r0, [r3,#4]
Tero Kristo27d59a42008-10-13 13:15:00 +0300454 mov r12, #0x3
Dave Martin76d50012011-03-04 15:33:55 +0000455 smc #0 @ Call SMI monitor (smieq)
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200456 ldr r4, scratchpad_base
457 ldr r3, [r4,#0xBC]
458 ldr r0, [r3,#12]
459 mov r12, #0x2
Dave Martin76d50012011-03-04 15:33:55 +0000460 smc #0 @ Call SMI monitor (smieq)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700461logic_l1_restore:
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600462 ldr r1, l2dis_3630
Jean Pihetbb1c9032010-12-18 16:49:57 +0100463 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600464 bne skipl2reen
465 mrc p15, 0, r1, c1, c0, 1
Jean Pihetbb1c9032010-12-18 16:49:57 +0100466 orr r1, r1, #2 @ re-enable L2 cache
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600467 mcr p15, 0, r1, c1, c0, 1
468skipl2reen:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700469 mov r1, #0
Jean Pihetbb1c9032010-12-18 16:49:57 +0100470 /*
471 * Invalidate all instruction caches to PoU
472 * and flush branch target cache
473 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700474 mcr p15, 0, r1, c7, c5, 0
475
476 ldr r4, scratchpad_base
477 ldr r3, [r4,#0xBC]
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200478 adds r3, r3, #16
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530479
Kevin Hilman8bd22942009-05-28 10:56:16 -0700480 ldmia r3!, {r4-r6}
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530481 mov sp, r4 @ Restore sp
482 msr spsr_cxsf, r5 @ Restore spsr
483 mov lr, r6 @ Restore lr
Kevin Hilman8bd22942009-05-28 10:56:16 -0700484
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530485 ldmia r3!, {r4-r7}
486 mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
487 mcr p15, 0, r5, c2, c0, 0 @ TTBR0
488 mcr p15, 0, r6, c2, c0, 1 @ TTBR1
489 mcr p15, 0, r7, c2, c0, 2 @ TTBCR
Kevin Hilman8bd22942009-05-28 10:56:16 -0700490
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530491 ldmia r3!,{r4-r6}
492 mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
493 mcr p15, 0, r5, c10, c2, 0 @ PRRR
494 mcr p15, 0, r6, c10, c2, 1 @ NMRR
Kevin Hilman8bd22942009-05-28 10:56:16 -0700495
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530496
Jean Pihetbb1c9032010-12-18 16:49:57 +0100497 ldmia r3!,{r4-r7}
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530498 mcr p15, 0, r4, c13, c0, 1 @ Context ID
499 mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
500 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
501 msr cpsr, r7 @ store cpsr
Kevin Hilman8bd22942009-05-28 10:56:16 -0700502
503 /* Enabling MMU here */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100504 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
505 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700506 and r7, #0x7
507 cmp r7, #0x0
508 beq usettbr0
509ttbr_error:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100510 /*
511 * More work needs to be done to support N[0:2] value other than 0
512 * So looping here so that the error can be detected
513 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700514 b ttbr_error
515usettbr0:
516 mrc p15, 0, r2, c2, c0, 0
517 ldr r5, ttbrbit_mask
518 and r2, r5
519 mov r4, pc
520 ldr r5, table_index_mask
Jean Pihetbb1c9032010-12-18 16:49:57 +0100521 and r4, r5 @ r4 = 31 to 20 bits of pc
Kevin Hilman8bd22942009-05-28 10:56:16 -0700522 /* Extract the value to be written to table entry */
523 ldr r1, table_entry
Jean Pihetbb1c9032010-12-18 16:49:57 +0100524 /* r1 has the value to be written to table entry*/
525 add r1, r1, r4
Kevin Hilman8bd22942009-05-28 10:56:16 -0700526 /* Getting the address of table entry to modify */
527 lsr r4, #18
Jean Pihetbb1c9032010-12-18 16:49:57 +0100528 /* r2 has the location which needs to be modified */
529 add r2, r4
Kevin Hilman8bd22942009-05-28 10:56:16 -0700530 /* Storing previous entry of location being modified */
531 ldr r5, scratchpad_base
532 ldr r4, [r2]
533 str r4, [r5, #0xC0]
534 /* Modify the table entry */
535 str r1, [r2]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100536 /*
537 * Storing address of entry being modified
538 * - will be restored after enabling MMU
539 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700540 ldr r5, scratchpad_base
541 str r2, [r5, #0xC4]
542
543 mov r0, #0
544 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
545 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
546 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
547 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
Jean Pihetbb1c9032010-12-18 16:49:57 +0100548 /*
549 * Restore control register. This enables the MMU.
550 * The caches and prediction are not enabled here, they
551 * will be enabled after restoring the MMU table entry.
552 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700553 ldmia r3!, {r4}
554 /* Store previous value of control register in scratchpad */
555 str r4, [r5, #0xC8]
556 ldr r2, cache_pred_disable_mask
557 and r4, r2
558 mcr p15, 0, r4, c1, c0, 0
Santosh Shilimkar8409d572011-01-23 16:04:39 +0530559 dsb
560 isb
561 ldr r0, =restoremmu_on
562 bx r0
Kevin Hilman8bd22942009-05-28 10:56:16 -0700563
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100564/*
565 * ==============================
566 * == Exit point from OFF mode ==
567 * ==============================
568 */
Santosh Shilimkar8409d572011-01-23 16:04:39 +0530569restoremmu_on:
Russell King857c1b82011-06-22 12:44:32 +0100570 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
Kevin Hilman8bd22942009-05-28 10:56:16 -0700571
Jean Pihet1e81bc02010-12-18 16:44:44 +0100572
573/*
574 * Internal functions
575 */
576
Jean Pihet83521292010-12-18 16:44:46 +0100577/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
Jean Pihet1e81bc02010-12-18 16:44:44 +0100578 .text
Dave Martindd313942011-03-04 15:33:57 +0000579 .align 3
Jean Pihet1e81bc02010-12-18 16:44:44 +0100580ENTRY(es3_sdrc_fix)
581 ldr r4, sdrc_syscfg @ get config addr
582 ldr r5, [r4] @ get value
583 tst r5, #0x100 @ is part access blocked
584 it eq
585 biceq r5, r5, #0x100 @ clear bit if set
586 str r5, [r4] @ write back change
587 ldr r4, sdrc_mr_0 @ get config addr
588 ldr r5, [r4] @ get value
589 str r5, [r4] @ write back change
590 ldr r4, sdrc_emr2_0 @ get config addr
591 ldr r5, [r4] @ get value
592 str r5, [r4] @ write back change
593 ldr r4, sdrc_manual_0 @ get config addr
594 mov r5, #0x2 @ autorefresh command
595 str r5, [r4] @ kick off refreshes
596 ldr r4, sdrc_mr_1 @ get config addr
597 ldr r5, [r4] @ get value
598 str r5, [r4] @ write back change
599 ldr r4, sdrc_emr2_1 @ get config addr
600 ldr r5, [r4] @ get value
601 str r5, [r4] @ write back change
602 ldr r4, sdrc_manual_1 @ get config addr
603 mov r5, #0x2 @ autorefresh command
604 str r5, [r4] @ kick off refreshes
605 bx lr
606
Dave Martindd313942011-03-04 15:33:57 +0000607 .align
Jean Pihet1e81bc02010-12-18 16:44:44 +0100608sdrc_syscfg:
609 .word SDRC_SYSCONFIG_P
610sdrc_mr_0:
611 .word SDRC_MR_0_P
612sdrc_emr2_0:
613 .word SDRC_EMR2_0_P
614sdrc_manual_0:
615 .word SDRC_MANUAL_0_P
616sdrc_mr_1:
617 .word SDRC_MR_1_P
618sdrc_emr2_1:
619 .word SDRC_EMR2_1_P
620sdrc_manual_1:
621 .word SDRC_MANUAL_1_P
Dave Martindd313942011-03-04 15:33:57 +0000622ENDPROC(es3_sdrc_fix)
Jean Pihet1e81bc02010-12-18 16:44:44 +0100623ENTRY(es3_sdrc_fix_sz)
624 .word . - es3_sdrc_fix
625
Jean Pihet83521292010-12-18 16:44:46 +0100626/*
627 * This function implements the erratum ID i581 WA:
628 * SDRC state restore before accessing the SDRAM
629 *
630 * Only used at return from non-OFF mode. For OFF
631 * mode the ROM code configures the SDRC and
632 * the DPLL before calling the restore code directly
633 * from DDR.
634 */
635
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200636/* Make sure SDRC accesses are ok */
637wait_sdrc_ok:
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600638
Jean Pihetbb1c9032010-12-18 16:49:57 +0100639/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600640 ldr r4, cm_idlest_ckgen
641wait_dpll3_lock:
642 ldr r5, [r4]
643 tst r5, #1
644 beq wait_dpll3_lock
645
Jean Pihetbb1c9032010-12-18 16:49:57 +0100646 ldr r4, cm_idlest1_core
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600647wait_sdrc_ready:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100648 ldr r5, [r4]
649 tst r5, #0x2
650 bne wait_sdrc_ready
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600651 /* allow DLL powerdown upon hw idle req */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100652 ldr r4, sdrc_power
653 ldr r5, [r4]
654 bic r5, r5, #0x40
655 str r5, [r4]
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600656
Dave Martindd313942011-03-04 15:33:57 +0000657/*
658 * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
659 * base instead.
660 * Be careful not to clobber r7 when maintaing this code.
661 */
662
Jean Pihetbb1c9032010-12-18 16:49:57 +0100663is_dll_in_lock_mode:
664 /* Is dll in lock mode? */
665 ldr r4, sdrc_dlla_ctrl
666 ldr r5, [r4]
667 tst r5, #0x4
668 bxne lr @ Return if locked
669 /* wait till dll locks */
Dave Martindd313942011-03-04 15:33:57 +0000670 adr r7, kick_counter
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600671wait_dll_lock_timed:
672 ldr r4, wait_dll_lock_counter
673 add r4, r4, #1
Dave Martindd313942011-03-04 15:33:57 +0000674 str r4, [r7, #wait_dll_lock_counter - kick_counter]
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600675 ldr r4, sdrc_dlla_status
Jean Pihetbb1c9032010-12-18 16:49:57 +0100676 /* Wait 20uS for lock */
677 mov r6, #8
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600678wait_dll_lock:
679 subs r6, r6, #0x1
680 beq kick_dll
Jean Pihetbb1c9032010-12-18 16:49:57 +0100681 ldr r5, [r4]
682 and r5, r5, #0x4
683 cmp r5, #0x4
684 bne wait_dll_lock
685 bx lr @ Return when locked
Kevin Hilman8bd22942009-05-28 10:56:16 -0700686
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600687 /* disable/reenable DLL if not locked */
688kick_dll:
689 ldr r4, sdrc_dlla_ctrl
690 ldr r5, [r4]
691 mov r6, r5
Jean Pihetbb1c9032010-12-18 16:49:57 +0100692 bic r6, #(1<<3) @ disable dll
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600693 str r6, [r4]
694 dsb
Jean Pihetbb1c9032010-12-18 16:49:57 +0100695 orr r6, r6, #(1<<3) @ enable dll
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600696 str r6, [r4]
697 dsb
698 ldr r4, kick_counter
699 add r4, r4, #1
Dave Martindd313942011-03-04 15:33:57 +0000700 str r4, [r7] @ kick_counter
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600701 b wait_dll_lock_timed
702
Dave Martindd313942011-03-04 15:33:57 +0000703 .align
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200704cm_idlest1_core:
705 .word CM_IDLEST1_CORE_V
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600706cm_idlest_ckgen:
707 .word CM_IDLEST_CKGEN_V
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200708sdrc_dlla_status:
709 .word SDRC_DLLA_STATUS_V
710sdrc_dlla_ctrl:
711 .word SDRC_DLLA_CTRL_V
Tero Kristo0795a752008-10-13 17:58:50 +0300712pm_prepwstst_core_p:
713 .word PM_PREPWSTST_CORE_P
Kevin Hilman8bd22942009-05-28 10:56:16 -0700714pm_pwstctrl_mpu:
715 .word PM_PWSTCTRL_MPU_P
716scratchpad_base:
717 .word SCRATCHPAD_BASE_P
Tero Kristo0795a752008-10-13 17:58:50 +0300718sram_base:
719 .word SRAM_BASE_P + 0x8000
Kevin Hilman8bd22942009-05-28 10:56:16 -0700720sdrc_power:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100721 .word SDRC_POWER_V
Kevin Hilman8bd22942009-05-28 10:56:16 -0700722ttbrbit_mask:
723 .word 0xFFFFC000
724table_index_mask:
725 .word 0xFFF00000
726table_entry:
727 .word 0x00000C02
728cache_pred_disable_mask:
729 .word 0xFFFFE7FB
Tero Kristo27d59a42008-10-13 13:15:00 +0300730control_stat:
731 .word CONTROL_STAT
Nishanth Menon458e9992010-12-20 14:05:06 -0600732control_mem_rta:
733 .word CONTROL_MEM_RTA_CTRL
Richard Woodruff0bd40532010-12-20 14:05:03 -0600734kernel_flush:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100735 .word v7_flush_dcache_all
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600736l2dis_3630:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100737 .word 0
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600738 /*
739 * When exporting to userspace while the counters are in SRAM,
740 * these 2 words need to be at the end to facilitate retrival!
741 */
742kick_counter:
743 .word 0
744wait_dll_lock_counter:
745 .word 0
Dave Martindd313942011-03-04 15:33:57 +0000746ENDPROC(omap34xx_cpu_suspend)
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100747
Kevin Hilman8bd22942009-05-28 10:56:16 -0700748ENTRY(omap34xx_cpu_suspend_sz)
749 .word . - omap34xx_cpu_suspend