blob: 16627069c53610a2930013c6c2886003068dc0a5 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/mm/tlb-sh3.c
3 *
4 * SH-3 specific TLB operations
5 *
6 * Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2002 Paul Mundt
8 *
9 * Released under the terms of the GNU GPL v2.0.
10 */
Paul Mundt26b7a782006-12-28 10:31:48 +090011#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15void __flush_tlb_page(unsigned long asid, unsigned long page)
16{
17 unsigned long addr, data;
18 int i, ways = MMU_NTLB_WAYS;
19
20 /*
21 * NOTE: PTEH.ASID should be set to this MM
22 * _AND_ we need to write ASID to the array.
23 *
24 * It would be simple if we didn't need to set PTEH.ASID...
25 */
26 addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
27 data = (page & 0xfffe0000) | asid; /* VALID bit is off */
Paul Mundt0d6d82b2005-11-07 00:58:28 -080028
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 if ((cpu_data->flags & CPU_HAS_MMU_PAGE_ASSOC)) {
30 addr |= MMU_PAGE_ASSOC_BIT;
31 ways = 1; /* we already know the way .. */
32 }
33
34 for (i = 0; i < ways; i++)
35 ctrl_outl(data, addr + (i << 8));
36}