blob: c81e6b67ad300e9e8b23c5adfc1658184d1ea59e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/mm/consistent.c
3 *
4 * Copyright (C) 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/mm.h>
11#include <linux/dma-mapping.h>
Paul Mundt26ff6c12006-09-27 15:13:36 +090012#include <asm/cacheflush.h>
13#include <asm/addrspace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <asm/io.h>
15
Al Viro6dae2c22005-10-21 03:21:38 -040016void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *handle)
Linus Torvalds1da177e2005-04-16 15:20:36 -070017{
18 struct page *page, *end, *free;
19 void *ret;
20 int order;
21
22 size = PAGE_ALIGN(size);
23 order = get_order(size);
24
25 page = alloc_pages(gfp, order);
26 if (!page)
27 return NULL;
Nick Piggin8dfcc9b2006-03-22 00:08:05 -080028 split_page(page, order);
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30 ret = page_address(page);
31 *handle = virt_to_phys(ret);
32
33 /*
34 * We must flush the cache before we pass it on to the device
35 */
36 dma_cache_wback_inv(ret, size);
37
38 page = virt_to_page(ret);
39 free = page + (size >> PAGE_SHIFT);
40 end = page + (1 << order);
41
42 while (++page < end) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070043 /* Free any unused pages */
44 if (page >= free) {
45 __free_page(page);
46 }
47 }
48
49 return P2SEGADDR(ret);
50}
51
52void consistent_free(void *vaddr, size_t size)
53{
54 unsigned long addr = P1SEGADDR((unsigned long)vaddr);
55 struct page *page=virt_to_page(addr);
56 int num_pages=(size+PAGE_SIZE-1) >> PAGE_SHIFT;
57 int i;
58
59 for(i=0;i<num_pages;i++) {
60 __free_page((page+i));
61 }
62}
63
64void consistent_sync(void *vaddr, size_t size, int direction)
65{
66 void * p1addr = (void*) P1SEGADDR((unsigned long)vaddr);
67
68 switch (direction) {
69 case DMA_FROM_DEVICE: /* invalidate only */
70 dma_cache_inv(p1addr, size);
71 break;
72 case DMA_TO_DEVICE: /* writeback only */
73 dma_cache_wback(p1addr, size);
74 break;
75 case DMA_BIDIRECTIONAL: /* writeback and invalidate */
76 dma_cache_wback_inv(p1addr, size);
77 break;
78 default:
79 BUG();
80 }
81}
82
83EXPORT_SYMBOL(consistent_alloc);
84EXPORT_SYMBOL(consistent_free);
85EXPORT_SYMBOL(consistent_sync);
86