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review.evervolv.com / android_kernel_oneplus_msm8996 / 270f8ce3122b12f4224f7c72806ebf05e23835a6 / . / arch / arm / boot / dts / tegra20.dtsi
blob: 5b104f1d5003fffb1376b18c11a8d21dbafb684e [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0x304>;
98 };
99
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <5 5 2>;
104 arm,tag-latency = <4 4 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]109 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]110 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]111 reg = <0x50041000 0x1000
112 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]113 interrupt-controller;
114 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]115 };
116
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]117 timer@60005000 {
118 compatible = "nvidia,tegra20-timer";
119 reg = <0x60005000 0x60>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04>;
124 };
125
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame^]126 tegra_car: clock {
127 compatible = "nvidia,tegra20-car";
128 reg = <0x60006000 0x1000>;
129 #clock-cells = <1>;
130 };
131
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]132 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]133 compatible = "nvidia,tegra20-apbdma";
134 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]135 interrupts = <0 104 0x04
136 0 105 0x04
137 0 106 0x04
138 0 107 0x04
139 0 108 0x04
140 0 109 0x04
141 0 110 0x04
142 0 111 0x04
143 0 112 0x04
144 0 113 0x04
145 0 114 0x04
146 0 115 0x04
147 0 116 0x04
148 0 117 0x04
149 0 118 0x04
150 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]151 };
152
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]153 ahb {
154 compatible = "nvidia,tegra20-ahb";
155 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]156 };
157
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]158 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]159 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]160 reg = <0x6000d000 0x1000>;
161 interrupts = <0 32 0x04
162 0 33 0x04
163 0 34 0x04
164 0 35 0x04
165 0 55 0x04
166 0 87 0x04
167 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]168 #gpio-cells = <2>;
169 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]170 #interrupt-cells = <2>;
171 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]172 };
173
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]174 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]175 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]176 reg = <0x70000014 0x10 /* Tri-state registers */
177 0x70000080 0x20 /* Mux registers */
178 0x700000a0 0x14 /* Pull-up/down registers */
179 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]180 };
181
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]182 das {
183 compatible = "nvidia,tegra20-das";
184 reg = <0x70000c00 0x80>;
185 };
186
187 tegra_i2s1: i2s@70002800 {
188 compatible = "nvidia,tegra20-i2s";
189 reg = <0x70002800 0x200>;
190 interrupts = <0 13 0x04>;
191 nvidia,dma-request-selector = <&apbdma 2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]192 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]193 };
194
195 tegra_i2s2: i2s@70002a00 {
196 compatible = "nvidia,tegra20-i2s";
197 reg = <0x70002a00 0x200>;
198 interrupts = <0 3 0x04>;
199 nvidia,dma-request-selector = <&apbdma 1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]200 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]201 };
202
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]203 serial@70006000 {
204 compatible = "nvidia,tegra20-uart";
205 reg = <0x70006000 0x40>;
206 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]207 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]208 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]209 };
210
211 serial@70006040 {
212 compatible = "nvidia,tegra20-uart";
213 reg = <0x70006040 0x40>;
214 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]215 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]216 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]217 };
218
219 serial@70006200 {
220 compatible = "nvidia,tegra20-uart";
221 reg = <0x70006200 0x100>;
222 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]223 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]224 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]225 };
226
227 serial@70006300 {
228 compatible = "nvidia,tegra20-uart";
229 reg = <0x70006300 0x100>;
230 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]231 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]232 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]233 };
234
235 serial@70006400 {
236 compatible = "nvidia,tegra20-uart";
237 reg = <0x70006400 0x100>;
238 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]239 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]240 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]241 };
242
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]243 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]244 compatible = "nvidia,tegra20-pwm";
245 reg = <0x7000a000 0x100>;
246 #pwm-cells = <2>;
247 };
248
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]249 rtc {
250 compatible = "nvidia,tegra20-rtc";
251 reg = <0x7000e000 0x100>;
252 interrupts = <0 2 0x04>;
253 };
254
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]255 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]256 compatible = "nvidia,tegra20-i2c";
257 reg = <0x7000c000 0x100>;
258 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]259 #address-cells = <1>;
260 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]261 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]262 };
263
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]264 spi@7000c380 {
265 compatible = "nvidia,tegra20-sflash";
266 reg = <0x7000c380 0x80>;
267 interrupts = <0 39 0x04>;
268 nvidia,dma-request-selector = <&apbdma 11>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
273
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]274 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]275 compatible = "nvidia,tegra20-i2c";
276 reg = <0x7000c400 0x100>;
277 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]278 #address-cells = <1>;
279 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]280 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]281 };
282
283 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]284 compatible = "nvidia,tegra20-i2c";
285 reg = <0x7000c500 0x100>;
286 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]287 #address-cells = <1>;
288 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]289 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]290 };
291
292 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]293 compatible = "nvidia,tegra20-i2c-dvc";
294 reg = <0x7000d000 0x200>;
295 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]296 #address-cells = <1>;
297 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]298 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]299 };
300
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]301 spi@7000d400 {
302 compatible = "nvidia,tegra20-slink";
303 reg = <0x7000d400 0x200>;
304 interrupts = <0 59 0x04>;
305 nvidia,dma-request-selector = <&apbdma 15>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 status = "disabled";
309 };
310
311 spi@7000d600 {
312 compatible = "nvidia,tegra20-slink";
313 reg = <0x7000d600 0x200>;
314 interrupts = <0 82 0x04>;
315 nvidia,dma-request-selector = <&apbdma 16>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 status = "disabled";
319 };
320
321 spi@7000d800 {
322 compatible = "nvidia,tegra20-slink";
323 reg = <0x7000d480 0x200>;
324 interrupts = <0 83 0x04>;
325 nvidia,dma-request-selector = <&apbdma 17>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328 status = "disabled";
329 };
330
331 spi@7000da00 {
332 compatible = "nvidia,tegra20-slink";
333 reg = <0x7000da00 0x200>;
334 interrupts = <0 93 0x04>;
335 nvidia,dma-request-selector = <&apbdma 18>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 status = "disabled";
339 };
340
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]341 pmc {
342 compatible = "nvidia,tegra20-pmc";
343 reg = <0x7000e400 0x400>;
344 };
345
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]346 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]347 compatible = "nvidia,tegra20-mc";
348 reg = <0x7000f000 0x024
349 0x7000f03c 0x3c4>;
350 interrupts = <0 77 0x04>;
351 };
352
353 gart {
354 compatible = "nvidia,tegra20-gart";
355 reg = <0x7000f024 0x00000018 /* controller registers */
356 0x58000000 0x02000000>; /* GART aperture */
357 };
358
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]359 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]360 compatible = "nvidia,tegra20-emc";
361 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]362 #address-cells = <1>;
363 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]364 };
365
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]366 usb@c5000000 {
367 compatible = "nvidia,tegra20-ehci", "usb-ehci";
368 reg = <0xc5000000 0x4000>;
369 interrupts = <0 20 0x04>;
370 phy_type = "utmi";
371 nvidia,has-legacy-mode;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]372 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]373 };
374
375 usb@c5004000 {
376 compatible = "nvidia,tegra20-ehci", "usb-ehci";
377 reg = <0xc5004000 0x4000>;
378 interrupts = <0 21 0x04>;
379 phy_type = "ulpi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]380 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]381 };
382
383 usb@c5008000 {
384 compatible = "nvidia,tegra20-ehci", "usb-ehci";
385 reg = <0xc5008000 0x4000>;
386 interrupts = <0 97 0x04>;
387 phy_type = "utmi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]388 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]389 };
390
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]391 sdhci@c8000000 {
392 compatible = "nvidia,tegra20-sdhci";
393 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]394 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]395 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]396 };
397
398 sdhci@c8000200 {
399 compatible = "nvidia,tegra20-sdhci";
400 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]401 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]402 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]403 };
404
405 sdhci@c8000400 {
406 compatible = "nvidia,tegra20-sdhci";
407 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]408 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]409 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]410 };
411
412 sdhci@c8000600 {
413 compatible = "nvidia,tegra20-sdhci";
414 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]415 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]416 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]417 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]418
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]419 pmu {
420 compatible = "arm,cortex-a9-pmu";
421 interrupts = <0 56 0x04
422 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]423 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]424};