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review.evervolv.com / android_kernel_oneplus_msm8996 / 28a1f533ae8606020238b840b82ae70a3f87609e / . / arch / sparc / kernel / rtrap_64.S
blob: 090b9e9ad5e36a416258e003be80556b49330a62 [file] [log] [blame]
Adrian Bunkb00dc832008-05-19 16:52:27 -0700[diff] [blame]1/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2 * rtrap.S: Preparing for return from trap on Sparc V9.
3 *
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 */
7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8
9#include <asm/asi.h>
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12#include <asm/spitfire.h>
13#include <asm/head.h>
14#include <asm/visasm.h>
15#include <asm/processor.h>
16
David S. Miller64f2dde2008-10-29 21:25:00 -0700[diff] [blame]17#define RTRAP_PSTATE (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18#define RTRAP_PSTATE_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
19#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]20
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]21 .text
22 .align 32
23__handle_softirq:
24 call do_softirq
25 nop
26 ba,a,pt %xcc, __handle_softirq_continue
27 nop
28__handle_preemption:
29 call schedule
30 wrpr %g0, RTRAP_PSTATE, %pstate
31 ba,pt %xcc, __handle_preemption_continue
32 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
33
34__handle_user_windows:
35 call fault_in_user_windows
36 wrpr %g0, RTRAP_PSTATE, %pstate
37 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
38 /* Redo sched+sig checks */
39 ldx [%g6 + TI_FLAGS], %l0
40 andcc %l0, _TIF_NEED_RESCHED, %g0
41
42 be,pt %xcc, 1f
43 nop
44 call schedule
45 wrpr %g0, RTRAP_PSTATE, %pstate
46 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
47 ldx [%g6 + TI_FLAGS], %l0
48
Roland McGrathe35a8922008-04-20 15:06:49 -0700[diff] [blame]491: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]50 be,pt %xcc, __handle_user_windows_continue
51 nop
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]52 mov %l5, %o1
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]53 add %sp, PTREGS_OFF, %o0
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame]54 mov %l0, %o2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]55
56 call do_notify_resume
57 wrpr %g0, RTRAP_PSTATE, %pstate
58 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]59 /* Signal delivery can modify pt_regs tstate, so we must
60 * reload it.
61 */
62 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
63 sethi %hi(0xf << 20), %l4
64 and %l1, %l4, %l4
65 ba,pt %xcc, __handle_user_windows_continue
66
67 andn %l1, %l4, %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]68__handle_userfpu:
69 rd %fprs, %l5
70 andcc %l5, FPRS_FEF, %g0
71 sethi %hi(TSTATE_PEF), %o0
72 be,a,pn %icc, __handle_userfpu_continue
73 andn %l1, %o0, %l1
74 ba,a,pt %xcc, __handle_userfpu_continue
75
76__handle_signal:
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]77 mov %l5, %o1
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]78 add %sp, PTREGS_OFF, %o0
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame]79 mov %l0, %o2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]80 call do_notify_resume
81 wrpr %g0, RTRAP_PSTATE, %pstate
82 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]83
84 /* Signal delivery can modify pt_regs tstate, so we must
85 * reload it.
86 */
87 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
88 sethi %hi(0xf << 20), %l4
89 and %l1, %l4, %l4
90 ba,pt %xcc, __handle_signal_continue
91 andn %l1, %l4, %l1
92
David S. Miller55657362008-11-25 22:24:59 -0800[diff] [blame]93 /* When returning from a NMI (%pil==15) interrupt we want to
94 * avoid running softirqs, doing IRQ tracing, preempting, etc.
95 */
96 .globl rtrap_nmi
97rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 sethi %hi(0xf << 20), %l4
99 and %l1, %l4, %l4
100 andn %l1, %l4, %l1
101 srl %l4, 20, %l4
102 ba,pt %xcc, rtrap_no_irq_enable
103 wrpr %l4, %pil
104
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]105 .align 64
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame]106 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]107rtrap_irq:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]108rtrap:
David S. Millerd7ce78f2005-08-29 22:46:43 -0700[diff] [blame]109#ifndef CONFIG_SMP
Rusty Russelldd17c8f2009-10-29 22:34:15 +0900[diff] [blame]110 sethi %hi(__cpu_data), %l0
111 lduw [%l0 + %lo(__cpu_data)], %l1
David S. Millerd7ce78f2005-08-29 22:46:43 -0700[diff] [blame]112#else
Rusty Russelldd17c8f2009-10-29 22:34:15 +0900[diff] [blame]113 sethi %hi(__cpu_data), %l0
114 or %l0, %lo(__cpu_data), %l0
David S. Millerd7ce78f2005-08-29 22:46:43 -0700[diff] [blame]115 lduw [%l0 + %g5], %l1
116#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]117 cmp %l1, 0
118
119 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
120 bne,pn %icc, __handle_softirq
121 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
122__handle_softirq_continue:
123rtrap_xcall:
124 sethi %hi(0xf << 20), %l4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]125 and %l1, %l4, %l4
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]126 andn %l1, %l4, %l1
127 srl %l4, 20, %l4
128#ifdef CONFIG_TRACE_IRQFLAGS
129 brnz,pn %l4, rtrap_no_irq_enable
130 nop
131 call trace_hardirqs_on
132 nop
David S. Miller28a1f532010-04-20 00:48:37 -0700[diff] [blame^]133 /* Do not actually set the %pil here. We will do that
134 * below after we clear PSTATE_IE in the %pstate register.
135 * If we re-enable interrupts here, we can recurse down
136 * the hardirq stack potentially endlessly, causing a
137 * stack overflow.
138 *
139 * It is tempting to put this test and trace_hardirqs_on
140 * call at the 'rt_continue' label, but that will not work
141 * as that path hits unconditionally and we do not want to
142 * execute this in NMI return paths, for example.
143 */
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]144#endif
David S. Miller55657362008-11-25 22:24:59 -0800[diff] [blame]145rtrap_no_irq_enable:
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]146 andcc %l1, TSTATE_PRIV, %l3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]147 bne,pn %icc, to_kernel
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]148 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]149
150 /* We must hold IRQs off and atomically test schedule+signal
151 * state, then hold them off all the way back to userspace.
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]152 * If we are returning to kernel, none of this matters. Note
153 * that we are disabling interrupts via PSTATE_IE, not using
154 * %pil.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]155 *
156 * If we do not do this, there is a window where we would do
157 * the tests, later the signal/resched event arrives but we do
158 * not process it since we are still in kernel mode. It would
159 * take until the next local IRQ before the signal/resched
160 * event would be handled.
161 *
David S. Millerc7d5a002010-03-03 08:08:49 -0800[diff] [blame]162 * This also means that if we have to deal with user
163 * windows, we have to redo all of these sched+signal checks
164 * with IRQs disabled.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]165 */
166to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
167 wrpr 0, %pil
168__handle_preemption_continue:
169 ldx [%g6 + TI_FLAGS], %l0
170 sethi %hi(_TIF_USER_WORK_MASK), %o0
171 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
172 andcc %l0, %o0, %g0
173 sethi %hi(TSTATE_PEF), %o0
174 be,pt %xcc, user_nowork
175 andcc %l1, %o0, %g0
176 andcc %l0, _TIF_NEED_RESCHED, %g0
177 bne,pn %xcc, __handle_preemption
Roland McGrathe35a8922008-04-20 15:06:49 -0700[diff] [blame]178 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]179 bne,pn %xcc, __handle_signal
180__handle_signal_continue:
181 ldub [%g6 + TI_WSAVED], %o2
182 brnz,pn %o2, __handle_user_windows
183 nop
184__handle_user_windows_continue:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]185 sethi %hi(TSTATE_PEF), %o0
David S. Millerc7d5a002010-03-03 08:08:49 -0800[diff] [blame]186 andcc %l1, %o0, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]187
188 /* This fpdepth clear is necessary for non-syscall rtraps only */
189user_nowork:
190 bne,pn %xcc, __handle_userfpu
191 stb %g0, [%g6 + TI_FPDEPTH]
192__handle_userfpu_continue:
193
194rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
195 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
196
197 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
198 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
199 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]200 brz,pt %l3, 1f
David S. Miller314981a2006-02-05 21:59:03 -0800[diff] [blame]201 mov %g6, %l2
202
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]203 /* Must do this before thread reg is clobbered below. */
David S. Millerffe483d2006-02-02 21:55:10 -0800[diff] [blame]204 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]2051:
206 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]207 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]208
209 /* Normal globals are restored, go to trap globals. */
210661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
David S. Milleraf02bec2006-02-16 16:23:45 -0800[diff] [blame]211 nop
212 .section .sun4v_2insn_patch, "ax"
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]213 .word 661b
David S. Milleraf02bec2006-02-16 16:23:45 -0800[diff] [blame]214 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]215 SET_GL(1)
216 .previous
217
David S. Miller314981a2006-02-05 21:59:03 -0800[diff] [blame]218 mov %l2, %g6
219
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]220 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
221 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
222
223 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
224 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
225 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
226 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
227 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
228 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
229 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
230 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
231
232 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
233 wr %o3, %g0, %y
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]234 wrpr %l4, 0x0, %pil
235 wrpr %g0, 0x1, %tl
David S. Miller28e61032008-05-11 02:07:19 -0700[diff] [blame]236 andn %l1, TSTATE_SYSCALL, %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]237 wrpr %l1, %g0, %tstate
238 wrpr %l2, %g0, %tpc
239 wrpr %o2, %g0, %tnpc
240
241 brnz,pn %l3, kern_rtt
242 mov PRIMARY_CONTEXT, %l7
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]243
244661: ldxa [%l7 + %l7] ASI_DMMU, %l0
245 .section .sun4v_1insn_patch, "ax"
246 .word 661b
247 ldxa [%l7 + %l7] ASI_MMU, %l0
248 .previous
249
David S. Miller0835ae02005-10-04 15:23:20 -0700[diff] [blame]250 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
251 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]252 or %l0, %l1, %l0
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]253
254661: stxa %l0, [%l7] ASI_DMMU
255 .section .sun4v_1insn_patch, "ax"
256 .word 661b
257 stxa %l0, [%l7] ASI_MMU
258 .previous
259
David S. Miller4da808c2006-01-31 18:33:00 -0800[diff] [blame]260 sethi %hi(KERNBASE), %l7
261 flush %l7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]262 rdpr %wstate, %l1
263 rdpr %otherwin, %l2
264 srl %l1, 3, %l1
265
266 wrpr %l2, %g0, %canrestore
267 wrpr %l1, %g0, %wstate
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]268 brnz,pt %l2, user_rtt_restore
269 wrpr %g0, %g0, %otherwin
270
271 ldx [%g6 + TI_FLAGS], %g3
272 wr %g0, ASI_AIUP, %asi
273 rdpr %cwp, %g1
274 andcc %g3, _TIF_32BIT, %g0
275 sub %g1, 1, %g1
276 bne,pt %xcc, user_rtt_fill_32bit
277 wrpr %g1, %cwp
278 ba,a,pt %xcc, user_rtt_fill_64bit
279
280user_rtt_fill_fixup:
281 rdpr %cwp, %g1
282 add %g1, 1, %g1
283 wrpr %g1, 0x0, %cwp
284
285 rdpr %wstate, %g2
286 sll %g2, 3, %g2
287 wrpr %g2, 0x0, %wstate
288
289 /* We know %canrestore and %otherwin are both zero. */
290
291 sethi %hi(sparc64_kern_pri_context), %g2
292 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
293 mov PRIMARY_CONTEXT, %g1
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]294
295661: stxa %g2, [%g1] ASI_DMMU
296 .section .sun4v_1insn_patch, "ax"
297 .word 661b
298 stxa %g2, [%g1] ASI_MMU
299 .previous
300
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]301 sethi %hi(KERNBASE), %g1
302 flush %g1
303
304 or %g4, FAULT_CODE_WINFIXUP, %g4
305 stb %g4, [%g6 + TI_FAULT_CODE]
306 stx %g5, [%g6 + TI_FAULT_ADDR]
307
308 mov %g6, %l1
309 wrpr %g0, 0x0, %tl
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]310
311661: nop
David S. Millerdf7d6ae2006-02-07 00:00:16 -0800[diff] [blame]312 .section .sun4v_1insn_patch, "ax"
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]313 .word 661b
314 SET_GL(0)
315 .previous
316
David S. Millerfc504922006-02-22 16:15:45 -0800[diff] [blame]317 wrpr %g0, RTRAP_PSTATE, %pstate
318
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]319 mov %l1, %g6
320 ldx [%g6 + TI_TASK], %g4
321 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
322 call do_sparc64_fault
323 add %sp, PTREGS_OFF, %o0
324 ba,pt %xcc, rtrap
325 nop
326
327user_rtt_pre_restore:
328 add %g1, 1, %g1
329 wrpr %g1, 0x0, %cwp
330
331user_rtt_restore:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]332 restore
333 rdpr %canrestore, %g1
334 wrpr %g1, 0x0, %cleanwin
335 retry
336 nop
337
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]338kern_rtt: rdpr %canrestore, %g1
339 brz,pn %g1, kern_rtt_fill
340 nop
341kern_rtt_restore:
David S. Millerada44a02008-05-21 21:50:01 -0700[diff] [blame]342 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]343 restore
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]344 retry
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]345
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]346to_kernel:
347#ifdef CONFIG_PREEMPT
348 ldsw [%g6 + TI_PRE_COUNT], %l5
349 brnz %l5, kern_fpucheck
350 ldx [%g6 + TI_FLAGS], %l5
351 andcc %l5, _TIF_NEED_RESCHED, %g0
352 be,pt %xcc, kern_fpucheck
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]353 nop
354 cmp %l4, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]355 bne,pn %xcc, kern_fpucheck
356 sethi %hi(PREEMPT_ACTIVE), %l6
357 stw %l6, [%g6 + TI_PRE_COUNT]
358 call schedule
359 nop
360 ba,pt %xcc, rtrap
361 stw %g0, [%g6 + TI_PRE_COUNT]
362#endif
363kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
364 brz,pt %l5, rt_continue
365 srl %l5, 1, %o0
366 add %g6, TI_FPSAVED, %l6
367 ldub [%l6 + %o0], %l2
368 sub %l5, 2, %l5
369
370 add %g6, TI_GSR, %o1
371 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
372 be,pt %icc, 2f
373 and %l2, FPRS_DL, %l6
374 andcc %l2, FPRS_FEF, %g0
375 be,pn %icc, 5f
376 sll %o0, 3, %o5
377 rd %fprs, %g1
378
379 wr %g1, FPRS_FEF, %fprs
380 ldx [%o1 + %o5], %g1
381 add %g6, TI_XFSR, %o1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]382 sll %o0, 8, %o2
383 add %g6, TI_FPREGS, %o3
384 brz,pn %l6, 1f
385 add %g6, TI_FPREGS+0x40, %o4
386
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]387 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]388 ldda [%o3 + %o2] ASI_BLK_P, %f0
389 ldda [%o4 + %o2] ASI_BLK_P, %f16
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]390 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3911: andcc %l2, FPRS_DU, %g0
392 be,pn %icc, 1f
393 wr %g1, 0, %gsr
394 add %o2, 0x80, %o2
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]395 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]396 ldda [%o3 + %o2] ASI_BLK_P, %f32
397 ldda [%o4 + %o2] ASI_BLK_P, %f48
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3981: membar #Sync
399 ldx [%o1 + %o5], %fsr
4002: stb %l5, [%g6 + TI_FPDEPTH]
401 ba,pt %xcc, rt_continue
402 nop
4035: wr %g0, FPRS_FEF, %fprs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]404 sll %o0, 8, %o2
405
406 add %g6, TI_FPREGS+0x80, %o3
407 add %g6, TI_FPREGS+0xc0, %o4
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]408 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]409 ldda [%o3 + %o2] ASI_BLK_P, %f32
410 ldda [%o4 + %o2] ASI_BLK_P, %f48
411 membar #Sync
412 wr %g0, FPRS_DU, %fprs
413 ba,pt %xcc, rt_continue
414 stb %l5, [%g6 + TI_FPDEPTH]