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Mark Brown73b34ea2010-03-15 17:46:02 +00001/*
2 * linux/sound/wm8903.h -- Platform data for WM8903
3 *
4 * Copyright 2010 Wolfson Microelectronics. PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_WM8903_H
12#define __LINUX_SND_WM8903_H
13
14/* Used to enable configuration of a GPIO to all zeros */
15#define WM8903_GPIO_NO_CONFIG 0x8000
16
17/*
Mark Brown37f88e82010-03-15 18:14:34 +000018 * R6 (0x06) - Mic Bias Control 0
19 */
Stephen Warren28d639f72011-02-10 15:37:13 -070020#define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
21#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */
22#define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */
Mark Brown37f88e82010-03-15 18:14:34 +000023#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
24#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
25#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
26#define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27#define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
28#define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
29#define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
30#define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31#define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32#define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
33#define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
34
35/*
Mark Brown73b34ea2010-03-15 17:46:02 +000036 * R116 (0x74) - GPIO Control 1
37 */
38#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */
39#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */
40#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */
41#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */
42#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */
43#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */
44#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */
45#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */
46#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */
47#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */
48#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
49#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */
50#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */
51#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */
52#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */
53#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */
54#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */
55#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */
56#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */
57#define WM8903_GP1_PD 0x0008 /* GP1_PD */
58#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */
59#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */
60#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */
61#define WM8903_GP1_PU 0x0004 /* GP1_PU */
62#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */
63#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */
64#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */
65#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */
66#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */
67#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */
68#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */
69#define WM8903_GP1_DB 0x0001 /* GP1_DB */
70#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */
71#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */
72#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */
73
74/*
75 * R117 (0x75) - GPIO Control 2
76 */
77#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */
78#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */
79#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */
80#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */
81#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */
82#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */
83#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */
84#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */
85#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */
86#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */
87#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
88#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */
89#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */
90#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */
91#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */
92#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */
93#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */
94#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */
95#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */
96#define WM8903_GP2_PD 0x0008 /* GP2_PD */
97#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */
98#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */
99#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */
100#define WM8903_GP2_PU 0x0004 /* GP2_PU */
101#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */
102#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */
103#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */
104#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */
105#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */
106#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */
107#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */
108#define WM8903_GP2_DB 0x0001 /* GP2_DB */
109#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */
110#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */
111#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */
112
113/*
114 * R118 (0x76) - GPIO Control 3
115 */
116#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */
117#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */
118#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */
119#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */
120#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */
121#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */
122#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */
123#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */
124#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */
125#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */
126#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
127#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */
128#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */
129#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */
130#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */
131#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */
132#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */
133#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */
134#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */
135#define WM8903_GP3_PD 0x0008 /* GP3_PD */
136#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */
137#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */
138#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */
139#define WM8903_GP3_PU 0x0004 /* GP3_PU */
140#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */
141#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */
142#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */
143#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */
144#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */
145#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */
146#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */
147#define WM8903_GP3_DB 0x0001 /* GP3_DB */
148#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */
149#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */
150#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */
151
152/*
153 * R119 (0x77) - GPIO Control 4
154 */
155#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */
156#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */
157#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */
158#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */
159#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */
160#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */
161#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */
162#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */
163#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */
164#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */
165#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
166#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */
167#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */
168#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */
169#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */
170#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */
171#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */
172#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */
173#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */
174#define WM8903_GP4_PD 0x0008 /* GP4_PD */
175#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */
176#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */
177#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */
178#define WM8903_GP4_PU 0x0004 /* GP4_PU */
179#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */
180#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */
181#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */
182#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */
183#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */
184#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */
185#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */
186#define WM8903_GP4_DB 0x0001 /* GP4_DB */
187#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */
188#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */
189#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */
190
191/*
192 * R120 (0x78) - GPIO Control 5
193 */
194#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */
195#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */
196#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */
197#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */
198#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */
199#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */
200#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */
201#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */
202#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */
203#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */
204#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
205#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */
206#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */
207#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */
208#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */
209#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */
210#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */
211#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */
212#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */
213#define WM8903_GP5_PD 0x0008 /* GP5_PD */
214#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */
215#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */
216#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */
217#define WM8903_GP5_PU 0x0004 /* GP5_PU */
218#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */
219#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */
220#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */
221#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */
222#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */
223#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */
224#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */
225#define WM8903_GP5_DB 0x0001 /* GP5_DB */
226#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */
227#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */
228#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */
229
230struct wm8903_platform_data {
Mark Brown8abd16a2010-03-15 18:25:26 +0000231 bool irq_active_low; /* Set if IRQ active low, default high */
232
Mark Brown37f88e82010-03-15 18:14:34 +0000233 /* Default register value for R6 (Mic bias), used to configure
234 * microphone detection. In conjunction with gpio_cfg this
235 * can be used to route the microphone status signals out onto
236 * the GPIOs for use with snd_soc_jack_add_gpios().
237 */
238 u16 micdet_cfg;
239
Mark Brown72453872010-03-15 21:22:58 +0000240 int micdet_delay; /* Delay after microphone detection (ms) */
241
Mark Brown73b34ea2010-03-15 17:46:02 +0000242 u32 gpio_cfg[5]; /* Default register values for GPIO pin mux */
243};
244
245#endif