| Jonas Bonn | 6162576 | 2011-06-04 22:45:16 +0300 | [diff] [blame] | 1 | OpenRISC Linux |
| 2 | ============== |
| 3 | |
| 4 | This is a port of Linux to the OpenRISC class of microprocessors; the initial |
| 5 | target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). |
| 6 | |
| 7 | For information about OpenRISC processors and ongoing development: |
| 8 | |
| 9 | website http://openrisc.net |
| 10 | |
| 11 | For more information about Linux on OpenRISC, please contact South Pole AB. |
| 12 | |
| 13 | email: info@southpole.se |
| 14 | |
| 15 | website: http://southpole.se |
| 16 | http://southpoleconsulting.com |
| 17 | |
| 18 | --------------------------------------------------------------------- |
| 19 | |
| 20 | Build instructions for OpenRISC toolchain and Linux |
| 21 | =================================================== |
| 22 | |
| 23 | In order to build and run Linux for OpenRISC, you'll need at least a basic |
| 24 | toolchain and, perhaps, the architectural simulator. Steps to get these bits |
| 25 | in place are outlined here. |
| 26 | |
| 27 | 1) The toolchain can be obtained from openrisc.net. Instructions for building |
| 28 | a toolchain can be found at: |
| 29 | |
| 30 | http://openrisc.net/toolchain-build.html |
| 31 | |
| 32 | 2) or1ksim (optional) |
| 33 | |
| 34 | or1ksim is the architectural simulator which will allow you to actually run |
| 35 | your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand. |
| 36 | |
| 37 | git clone git://openrisc.net/jonas/or1ksim-svn |
| 38 | |
| 39 | cd or1ksim |
| 40 | ./configure --prefix=$OPENRISC_PREFIX |
| 41 | make |
| 42 | make install |
| 43 | |
| 44 | 3) Linux kernel |
| 45 | |
| 46 | Build the kernel as usual |
| 47 | |
| 48 | make ARCH=openrisc defconfig |
| 49 | make ARCH=openrisc |
| 50 | |
| 51 | 4) Run in architectural simulator |
| 52 | |
| 53 | Grab the or1ksim platform configuration file (from the or1ksim source) and |
| 54 | together with your freshly built vmlinux, run your kernel with the following |
| 55 | incantation: |
| 56 | |
| 57 | sim -f arch/openrisc/or1ksim.cfg vmlinux |
| 58 | |
| 59 | --------------------------------------------------------------------- |
| 60 | |
| 61 | Terminology |
| 62 | =========== |
| 63 | |
| 64 | In the code, the following particles are used on symbols to limit the scope |
| 65 | to more or less specific processor implementations: |
| 66 | |
| 67 | openrisc: the OpenRISC class of processors |
| 68 | or1k: the OpenRISC 1000 family of processors |
| 69 | or1200: the OpenRISC 1200 processor |
| 70 | |
| 71 | --------------------------------------------------------------------- |
| 72 | |
| 73 | History |
| 74 | ======== |
| 75 | |
| 76 | 18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com) |
| 77 | initial port of linux to OpenRISC/or32 architecture. |
| 78 | all the core stuff is implemented and seams usable. |
| 79 | |
| 80 | 08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com) |
| 81 | complete change of TLB miss handling. |
| 82 | rewrite of exceptions handling. |
| 83 | fully functional sash-3.6 in default initrd. |
| 84 | a much improved version with changes all around. |
| 85 | |
| 86 | 10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com) |
| 87 | alot of bugfixes all over. |
| 88 | ethernet support, functional http and telnet servers. |
| 89 | running many standard linux apps. |
| 90 | |
| 91 | 26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com) |
| 92 | port to 2.6.x |
| 93 | |
| 94 | 30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com) |
| 95 | lots of bugfixes and enhancments. |
| 96 | added opencores framebuffer driver. |
| 97 | |
| 98 | 09. 10. 2010 Jonas Bonn (jonas@southpole.se) |
| 99 | major rewrite to bring up to par with upstream Linux 2.6.36 |