| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: estate.h,v 1.1 2001/03/28 10:56:34 davem Exp $ */ |
| 2 | #ifndef _SPARC64_ESTATE_H |
| 3 | #define _SPARC64_ESTATE_H |
| 4 | |
| 5 | /* UltraSPARC-III E-cache Error Enable */ |
| 6 | #define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */ |
| 7 | #define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */ |
| 8 | #define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */ |
| 9 | #define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */ |
| 10 | #define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */ |
| 11 | #define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */ |
| 12 | #define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */ |
| 13 | |
| 14 | /* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache |
| 15 | * errors 2) uncorrectable E-cache errors. Such events only occur on reads |
| 16 | * of the E-cache by the local processor for: 1) data loads 2) instruction |
| 17 | * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge |
| 18 | * 2) writeback 2) copyout. The AFSR bits associated with these traps are |
| 19 | * UCC and UCU. |
| 20 | */ |
| 21 | |
| 22 | /* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps |
| 23 | * for uncorrectable ECC errors and system errors. |
| 24 | * |
| 25 | * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT, |
| 26 | * or system bus BusERR: |
| 27 | * 1) As the result of an instruction fetch, will generate instruction_access_error |
| 28 | * 2) As the result of a load etc. will generate data_access_error. |
| 29 | * 3) As the result of store merge completion, writeback, or copyout will |
| 30 | * generate a disrupting ECC_error trap. |
| 31 | * 4) As the result of such errors on instruction vector fetch can generate any |
| 32 | * of the 3 trap types. |
| 33 | * |
| 34 | * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE, |
| 35 | * BERR, and TO. |
| 36 | */ |
| 37 | |
| 38 | /* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus |
| 39 | * reads resulting in a hardware corrected data or MTAG ECC error will generate an |
| 40 | * ECC_error disrupting trap with this bit enabled. |
| 41 | * |
| 42 | * This same trap will also be generated when a hardware corrected ECC error results |
| 43 | * during store merge, writeback, and copyout operations. |
| 44 | */ |
| 45 | |
| 46 | /* In general, if the trap enable bits above are disabled the AFSR bits will still |
| 47 | * log the events even though the trap will not be generated by the processor. |
| 48 | */ |
| 49 | |
| 50 | #endif /* _SPARC64_ESTATE_H */ |