| David S. Miller | 2a7e299 | 2005-09-21 18:50:51 -0700 | [diff] [blame^] | 1 | /* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling. |
| 2 | * |
| 3 | * Copyright (C) 1995, 1997, 2005 David S. Miller <davem@davemloft.net> |
| 4 | * Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de) |
| 5 | * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) |
| 6 | * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
| 7 | */ |
| 8 | |
| 9 | #include <linux/config.h> |
| 10 | #include <asm/head.h> |
| 11 | #include <asm/asi.h> |
| 12 | #include <asm/page.h> |
| 13 | #include <asm/pgtable.h> |
| 14 | |
| 15 | .text |
| 16 | .align 32 |
| 17 | |
| 18 | .globl sparc64_vpte_patchme1 |
| 19 | .globl sparc64_vpte_patchme2 |
| 20 | /* |
| 21 | * On a second level vpte miss, check whether the original fault is to the OBP |
| 22 | * range (note that this is only possible for instruction miss, data misses to |
| 23 | * obp range do not use vpte). If so, go back directly to the faulting address. |
| 24 | * This is because we want to read the tpc, otherwise we have no way of knowing |
| 25 | * the 8k aligned faulting address if we are using >8k kernel pagesize. This |
| 26 | * also ensures no vpte range addresses are dropped into tlb while obp is |
| 27 | * executing (see inherit_locked_prom_mappings() rant). |
| 28 | */ |
| 29 | sparc64_vpte_nucleus: |
| 30 | /* Note that kvmap below has verified that the address is |
| 31 | * in the range MODULES_VADDR --> VMALLOC_END already. So |
| 32 | * here we need only check if it is an OBP address or not. |
| 33 | */ |
| 34 | sethi %hi(LOW_OBP_ADDRESS), %g5 |
| 35 | cmp %g4, %g5 |
| 36 | blu,pn %xcc, sparc64_vpte_patchme1 |
| 37 | mov 0x1, %g5 |
| 38 | sllx %g5, 32, %g5 |
| 39 | cmp %g4, %g5 |
| 40 | blu,pn %xcc, obp_iaddr_patch |
| 41 | nop |
| 42 | |
| 43 | /* These two instructions are patched by paginig_init(). */ |
| 44 | sparc64_vpte_patchme1: |
| 45 | sethi %hi(0), %g5 |
| 46 | sparc64_vpte_patchme2: |
| 47 | or %g5, %lo(0), %g5 |
| 48 | |
| 49 | /* With kernel PGD in %g5, branch back into dtlb_backend. */ |
| 50 | ba,pt %xcc, sparc64_kpte_continue |
| 51 | andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */ |
| 52 | |
| 53 | vpte_noent: |
| 54 | /* Restore previous TAG_ACCESS, %g5 is zero, and we will |
| 55 | * skip over the trap instruction so that the top level |
| 56 | * TLB miss handler will thing this %g5 value is just an |
| 57 | * invalid PTE, thus branching to full fault processing. |
| 58 | */ |
| 59 | mov TLB_SFSR, %g1 |
| 60 | stxa %g4, [%g1 + %g1] ASI_DMMU |
| 61 | done |
| 62 | |
| 63 | .globl obp_iaddr_patch |
| 64 | obp_iaddr_patch: |
| 65 | /* These two instructions patched by inherit_prom_mappings(). */ |
| 66 | sethi %hi(0), %g5 |
| 67 | or %g5, %lo(0), %g5 |
| 68 | |
| 69 | /* Behave as if we are at TL0. */ |
| 70 | wrpr %g0, 1, %tl |
| 71 | rdpr %tpc, %g4 /* Find original faulting iaddr */ |
| 72 | srlx %g4, 13, %g4 /* Throw out context bits */ |
| 73 | sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */ |
| 74 | |
| 75 | /* Restore previous TAG_ACCESS. */ |
| 76 | mov TLB_SFSR, %g1 |
| 77 | stxa %g4, [%g1 + %g1] ASI_IMMU |
| 78 | |
| 79 | /* Get PMD offset. */ |
| 80 | srlx %g4, 23, %g6 |
| 81 | and %g6, 0x7ff, %g6 |
| 82 | sllx %g6, 2, %g6 |
| 83 | |
| 84 | /* Load PMD, is it valid? */ |
| 85 | lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 |
| 86 | brz,pn %g5, longpath |
| 87 | sllx %g5, 11, %g5 |
| 88 | |
| 89 | /* Get PTE offset. */ |
| 90 | srlx %g4, 13, %g6 |
| 91 | and %g6, 0x3ff, %g6 |
| 92 | sllx %g6, 3, %g6 |
| 93 | |
| 94 | /* Load PTE. */ |
| 95 | ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 |
| 96 | brgez,pn %g5, longpath |
| 97 | nop |
| 98 | |
| 99 | /* TLB load and return from trap. */ |
| 100 | stxa %g5, [%g0] ASI_ITLB_DATA_IN |
| 101 | retry |
| 102 | |
| 103 | .globl obp_daddr_patch |
| 104 | obp_daddr_patch: |
| 105 | /* These two instructions patched by inherit_prom_mappings(). */ |
| 106 | sethi %hi(0), %g5 |
| 107 | or %g5, %lo(0), %g5 |
| 108 | |
| 109 | /* Get PMD offset. */ |
| 110 | srlx %g4, 23, %g6 |
| 111 | and %g6, 0x7ff, %g6 |
| 112 | sllx %g6, 2, %g6 |
| 113 | |
| 114 | /* Load PMD, is it valid? */ |
| 115 | lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 |
| 116 | brz,pn %g5, longpath |
| 117 | sllx %g5, 11, %g5 |
| 118 | |
| 119 | /* Get PTE offset. */ |
| 120 | srlx %g4, 13, %g6 |
| 121 | and %g6, 0x3ff, %g6 |
| 122 | sllx %g6, 3, %g6 |
| 123 | |
| 124 | /* Load PTE. */ |
| 125 | ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 |
| 126 | brgez,pn %g5, longpath |
| 127 | nop |
| 128 | |
| 129 | /* TLB load and return from trap. */ |
| 130 | stxa %g5, [%g0] ASI_DTLB_DATA_IN |
| 131 | retry |
| 132 | |
| 133 | /* |
| 134 | * On a first level data miss, check whether this is to the OBP range (note |
| 135 | * that such accesses can be made by prom, as well as by kernel using |
| 136 | * prom_getproperty on "address"), and if so, do not use vpte access ... |
| 137 | * rather, use information saved during inherit_prom_mappings() using 8k |
| 138 | * pagesize. |
| 139 | */ |
| 140 | .align 32 |
| 141 | kvmap: |
| 142 | brlz,pt %g4, kvmap_load |
| 143 | xor %g2, %g4, %g5 |
| 144 | |
| 145 | kvmap_nonlinear: |
| 146 | sethi %hi(MODULES_VADDR), %g5 |
| 147 | cmp %g4, %g5 |
| 148 | blu,pn %xcc, longpath |
| 149 | mov (VMALLOC_END >> 24), %g5 |
| 150 | sllx %g5, 24, %g5 |
| 151 | cmp %g4, %g5 |
| 152 | bgeu,pn %xcc, longpath |
| 153 | nop |
| 154 | |
| 155 | kvmap_check_obp: |
| 156 | sethi %hi(LOW_OBP_ADDRESS), %g5 |
| 157 | cmp %g4, %g5 |
| 158 | blu,pn %xcc, kvmap_vmalloc_addr |
| 159 | mov 0x1, %g5 |
| 160 | sllx %g5, 32, %g5 |
| 161 | cmp %g4, %g5 |
| 162 | blu,pn %xcc, obp_daddr_patch |
| 163 | nop |
| 164 | |
| 165 | kvmap_vmalloc_addr: |
| 166 | /* If we get here, a vmalloc addr was accessed, load kernel VPTE. */ |
| 167 | ldxa [%g3 + %g6] ASI_N, %g5 |
| 168 | brgez,pn %g5, longpath |
| 169 | nop |
| 170 | |
| 171 | kvmap_load: |
| 172 | /* PTE is valid, load into TLB and return from trap. */ |
| 173 | stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB |
| 174 | retry |