Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 2b72b5bd65f00bce786ca080aca27e91e90af6df / . / drivers / net / ixgbe / ixgbe_phy.h
blob: 9cf5f3b4cc5dc38227f2ca4733547cab575e1758 [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Shannon Nelson8c47eaa2010-01-13 01:49:34 +0000[diff] [blame]4 Copyright(c) 1999 - 2010 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_PHY_H_
29#define _IXGBE_PHY_H_
30
31#include "ixgbe_type.h"
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]32#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]33
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]34/* EEPROM byte offsets */
35#define IXGBE_SFF_IDENTIFIER 0x0
36#define IXGBE_SFF_IDENTIFIER_SFP 0x3
37#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
38#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
39#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
40#define IXGBE_SFF_1GBE_COMP_CODES 0x6
41#define IXGBE_SFF_10GBE_COMP_CODES 0x3
Peter P Waskiewicz Jr537d58a2009-05-19 09:18:51 +0000[diff] [blame]42#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]43
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]44/* Bitmasks */
Peter P Waskiewicz Jr537d58a2009-05-19 09:18:51 +0000[diff] [blame]45#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]46#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000[diff] [blame]47#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]48#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
49#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
50#define IXGBE_I2C_EEPROM_READ_MASK 0x100
51#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
52#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
53#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
54#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
55#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
56
57/* Bit-shift macros */
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]58#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
59#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
60#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]61
62/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
63#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
64#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
65#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]66#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]67
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]68/* I2C SDA and SCL timing parameters for standard mode */
69#define IXGBE_I2C_T_HD_STA 4
70#define IXGBE_I2C_T_LOW 5
71#define IXGBE_I2C_T_HIGH 4
72#define IXGBE_I2C_T_SU_STA 5
73#define IXGBE_I2C_T_HD_DATA 5
74#define IXGBE_I2C_T_SU_DATA 1
75#define IXGBE_I2C_T_RISE 1
76#define IXGBE_I2C_T_FALL 1
77#define IXGBE_I2C_T_SU_STO 4
78#define IXGBE_I2C_T_BUF 5
79
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]80
81s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
82s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
83s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
84s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
85 u32 device_type, u16 *phy_data);
86s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
87 u32 device_type, u16 phy_data);
88s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
89s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
90 ixgbe_link_speed speed,
91 bool autoneg,
92 bool autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]93
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]94/* PHY specific */
95s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
96 ixgbe_link_speed *speed,
97 bool *link_up);
98s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
99 u16 *firmware_version);
100
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]101s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
102s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
103s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
104 u16 *list_offset,
105 u16 *data_offset);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]106s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
107 u8 dev_addr, u8 *data);
108s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
109 u8 dev_addr, u8 data);
110s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
111 u8 *eeprom_data);
112s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
113 u8 eeprom_data);
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]114#endif /* _IXGBE_PHY_H_ */