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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Francois Romieu07d3f512007-02-21 22:40:46 +01002 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
Rafael J. Wysockie1759442010-03-14 14:33:51 +000026#include <linux/pm_runtime.h>
françois romieubca03d52011-01-03 15:07:31 +000027#include <linux/firmware.h>
Stanislaw Gruszkaba04c7c2011-02-22 02:00:11 +000028#include <linux/pci-aspm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Francois Romieu99f252b2007-04-02 22:59:59 +020030#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include <asm/io.h>
32#include <asm/irq.h>
33
Francois Romieu865c6522008-05-11 14:51:00 +020034#define RTL8169_VERSION "2.3LK-NAPI"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#define MODULENAME "r8169"
36#define PFX MODULENAME ": "
37
françois romieubca03d52011-01-03 15:07:31 +000038#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
hayeswang01dc7fe2011-03-21 01:50:28 +000040#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
Hayes Wang5a5e4442011-02-22 17:26:21 +080042#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
françois romieubca03d52011-01-03 15:07:31 +000043
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#ifdef RTL8169_DEBUG
45#define assert(expr) \
Francois Romieu5b0384f2006-08-16 16:00:01 +020046 if (!(expr)) { \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
Harvey Harrisonb39d66a2008-08-20 16:52:04 -070048 #expr,__FILE__,__func__,__LINE__); \
Francois Romieu5b0384f2006-08-16 16:00:01 +020049 }
Joe Perches06fa7352007-10-18 21:15:00 +020050#define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070052#else
53#define assert(expr) do {} while (0)
54#define dprintk(fmt, args...) do {} while (0)
55#endif /* RTL8169_DEBUG */
56
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +020057#define R8169_MSG_DEFAULT \
Francois Romieuf0e837d2005-09-30 16:54:02 -070058 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +020059
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
Linus Torvalds1da177e2005-04-16 15:20:36 -070063/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
Arjan van de Venf71e1302006-03-03 21:33:57 -050065static const int multicast_filter_limit = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
67/* MAC address length */
68#define MAC_ADDR_LEN 6
69
Francois Romieu9c14cea2008-07-05 00:21:15 +020070#define MAX_READ_REQUEST_SHIFT 12
Linus Torvalds1da177e2005-04-16 15:20:36 -070071#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070074#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
françois romieuea8dbdd2009-03-15 01:10:50 +000088#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
Francois Romieue1564ec2008-10-16 22:46:13 +020090#define RTL_EEPROM_SIG_ADDR 0x0000
91
Linus Torvalds1da177e2005-04-16 15:20:36 -070092/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
Junchang Wang06f555f2010-05-30 02:26:07 +000098#define RTL_R32(reg) readl (ioaddr + (reg))
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100enum mac_version {
Jean Delvaref21b75e2009-05-26 20:54:48 -0700101 RTL_GIGA_MAC_NONE = 0x00,
Francois Romieuba6eb6e2007-06-11 23:35:18 +0200102 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
Francois Romieu6dccd162007-02-13 23:38:05 +0100107 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
Francois Romieu2857ffb2008-08-02 21:08:49 +0200108 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
Francois Romieu2dd99532007-06-11 23:22:52 +0200112 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
Francois Romieue3cf0cc2007-08-17 14:55:46 +0200113 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
Francois Romieu197ff762008-06-28 13:16:02 +0200121 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
Francois Romieu6fb07052008-06-29 11:54:28 +0200122 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
Francois Romieuef3386f2008-06-29 12:24:30 +0200123 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
Francois Romieu7f3e3d32008-07-20 18:53:20 +0200124 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
Francois Romieu5b538df2008-07-20 16:22:45 +0200125 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
françois romieudaf9df62009-10-07 12:44:20 +0000126 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
françois romieue6de30d2011-01-03 15:08:37 +0000128 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
Hayes Wang5a5e4442011-02-22 17:26:21 +0800130 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
hayeswang4804b3b2011-03-21 01:50:29 +0000132 RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
hayeswang01dc7fe2011-03-21 01:50:28 +0000133 RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134 RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135};
136
Francois Romieu2b7b4312011-04-18 22:53:24 -0700137enum rtl_tx_desc_version {
138 RTL_TD_0 = 0,
139 RTL_TD_1 = 1,
140};
141
142#define _R(NAME,MAC,TD) \
143 { .name = NAME, .mac_version = MAC, .txd_version = TD }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144
Jesper Juhl3c6bee12006-01-09 20:54:01 -0800145static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146 const char *name;
147 u8 mac_version;
Francois Romieu2b7b4312011-04-18 22:53:24 -0700148 enum rtl_tx_desc_version txd_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149} rtl_chip_info[] = {
Francois Romieu2b7b4312011-04-18 22:53:24 -0700150 _R("RTL8169", RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151 _R("RTL8169s", RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152 _R("RTL8110s", RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156 _R("RTL8102e", RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157 _R("RTL8102e", RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158 _R("RTL8102e", RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159 _R("RTL8101e", RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162 _R("RTL8101e", RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163 _R("RTL8100e", RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164 _R("RTL8100e", RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166 _R("RTL8101e", RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178 _R("RTL8105e", RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179 _R("RTL8105e", RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, RTL_TD_1) // PCI-E
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183};
184#undef _R
185
François Romieu953a12c2011-04-24 17:38:48 +0200186static const struct rtl_firmware_info {
187 int mac_version;
188 const char *fw_name;
189} rtl_firmware_infos[] = {
190 { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
191 { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
192 { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
David S. Miller2bd93d72011-04-26 12:16:46 -0700193 { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
194 { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
195 { .mac_version = RTL_GIGA_MAC_VER_31, .fw_name = FIRMWARE_8168E_1 },
196 { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_2 }
François Romieu953a12c2011-04-24 17:38:48 +0200197};
198
Francois Romieubcf0bf92006-07-26 23:14:13 +0200199enum cfg_version {
200 RTL_CFG_0 = 0x00,
201 RTL_CFG_1,
202 RTL_CFG_2
203};
204
Francois Romieu07ce4062007-02-23 23:36:39 +0100205static void rtl_hw_start_8169(struct net_device *);
206static void rtl_hw_start_8168(struct net_device *);
207static void rtl_hw_start_8101(struct net_device *);
208
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000209static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
Francois Romieubcf0bf92006-07-26 23:14:13 +0200210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
Francois Romieud2eed8c2006-08-31 22:01:07 +0200211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
Francois Romieud81bf552006-09-20 21:31:20 +0200212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
Francois Romieu07ce4062007-02-23 23:36:39 +0100213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
Francois Romieubcf0bf92006-07-26 23:14:13 +0200214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
215 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
Francois Romieubc1660b2007-10-12 23:58:09 +0200216 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
Francois Romieubcf0bf92006-07-26 23:14:13 +0200217 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
218 { PCI_VENDOR_ID_LINKSYS, 0x1032,
219 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
Ciaran McCreesh11d2e282007-11-01 22:48:15 +0100220 { 0x0001, 0x8168,
221 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 {0,},
223};
224
225MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
226
Eric Dumazet6f0333b2010-10-11 11:17:47 +0000227static int rx_buf_sz = 16383;
David S. Miller4300e8c2010-03-26 10:23:30 -0700228static int use_dac;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200229static struct {
230 u32 msg_enable;
231} debug = { -1 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232
Francois Romieu07d3f512007-02-21 22:40:46 +0100233enum rtl_registers {
234 MAC0 = 0, /* Ethernet hardware address. */
Francois Romieu773d2022007-01-31 23:47:43 +0100235 MAC4 = 4,
Francois Romieu07d3f512007-02-21 22:40:46 +0100236 MAR0 = 8, /* Multicast filter. */
237 CounterAddrLow = 0x10,
238 CounterAddrHigh = 0x14,
239 TxDescStartAddrLow = 0x20,
240 TxDescStartAddrHigh = 0x24,
241 TxHDescStartAddrLow = 0x28,
242 TxHDescStartAddrHigh = 0x2c,
243 FLASH = 0x30,
244 ERSR = 0x36,
245 ChipCmd = 0x37,
246 TxPoll = 0x38,
247 IntrMask = 0x3c,
248 IntrStatus = 0x3e,
249 TxConfig = 0x40,
250 RxConfig = 0x44,
Francois Romieu2b7b4312011-04-18 22:53:24 -0700251
252#define RTL_RX_CONFIG_MASK 0xff7e1880u
253
Francois Romieu07d3f512007-02-21 22:40:46 +0100254 RxMissed = 0x4c,
255 Cfg9346 = 0x50,
256 Config0 = 0x51,
257 Config1 = 0x52,
258 Config2 = 0x53,
259 Config3 = 0x54,
260 Config4 = 0x55,
261 Config5 = 0x56,
262 MultiIntr = 0x5c,
263 PHYAR = 0x60,
Francois Romieu07d3f512007-02-21 22:40:46 +0100264 PHYstatus = 0x6c,
265 RxMaxSize = 0xda,
266 CPlusCmd = 0xe0,
267 IntrMitigate = 0xe2,
268 RxDescAddrLow = 0xe4,
269 RxDescAddrHigh = 0xe8,
françois romieuf0298f82011-01-03 15:07:42 +0000270 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
271
272#define NoEarlyTx 0x3f /* Max value : no early transmit. */
273
274 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
275
276#define TxPacketMax (8064 >> 7)
277
Francois Romieu07d3f512007-02-21 22:40:46 +0100278 FuncEvent = 0xf0,
279 FuncEventMask = 0xf4,
280 FuncPresetState = 0xf8,
281 FuncForceEvent = 0xfc,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282};
283
Francois Romieuf162a5d2008-06-01 22:37:49 +0200284enum rtl8110_registers {
285 TBICSR = 0x64,
286 TBI_ANAR = 0x68,
287 TBI_LPAR = 0x6a,
288};
289
290enum rtl8168_8101_registers {
291 CSIDR = 0x64,
292 CSIAR = 0x68,
293#define CSIAR_FLAG 0x80000000
294#define CSIAR_WRITE_CMD 0x80000000
295#define CSIAR_BYTE_ENABLE 0x0f
296#define CSIAR_BYTE_ENABLE_SHIFT 12
297#define CSIAR_ADDR_MASK 0x0fff
françois romieu065c27c2011-01-03 15:08:12 +0000298 PMCH = 0x6f,
Francois Romieuf162a5d2008-06-01 22:37:49 +0200299 EPHYAR = 0x80,
300#define EPHYAR_FLAG 0x80000000
301#define EPHYAR_WRITE_CMD 0x80000000
302#define EPHYAR_REG_MASK 0x1f
303#define EPHYAR_REG_SHIFT 16
304#define EPHYAR_DATA_MASK 0xffff
Hayes Wang5a5e4442011-02-22 17:26:21 +0800305 DLLPR = 0xd0,
306#define PM_SWITCH (1 << 6)
Francois Romieuf162a5d2008-06-01 22:37:49 +0200307 DBG_REG = 0xd1,
308#define FIX_NAK_1 (1 << 4)
309#define FIX_NAK_2 (1 << 3)
Hayes Wang5a5e4442011-02-22 17:26:21 +0800310 TWSI = 0xd2,
311 MCU = 0xd3,
312#define EN_NDP (1 << 3)
313#define EN_OOB_RESET (1 << 2)
françois romieudaf9df62009-10-07 12:44:20 +0000314 EFUSEAR = 0xdc,
315#define EFUSEAR_FLAG 0x80000000
316#define EFUSEAR_WRITE_CMD 0x80000000
317#define EFUSEAR_READ_CMD 0x00000000
318#define EFUSEAR_REG_MASK 0x03ff
319#define EFUSEAR_REG_SHIFT 8
320#define EFUSEAR_DATA_MASK 0xff
Francois Romieuf162a5d2008-06-01 22:37:49 +0200321};
322
françois romieuc0e45c12011-01-03 15:08:04 +0000323enum rtl8168_registers {
françois romieub646d902011-01-03 15:08:21 +0000324 ERIDR = 0x70,
325 ERIAR = 0x74,
326#define ERIAR_FLAG 0x80000000
327#define ERIAR_WRITE_CMD 0x80000000
328#define ERIAR_READ_CMD 0x00000000
329#define ERIAR_ADDR_BYTE_ALIGN 4
330#define ERIAR_EXGMAC 0
331#define ERIAR_MSIX 1
332#define ERIAR_ASF 2
333#define ERIAR_TYPE_SHIFT 16
334#define ERIAR_BYTEEN 0x0f
335#define ERIAR_BYTEEN_SHIFT 12
françois romieuc0e45c12011-01-03 15:08:04 +0000336 EPHY_RXER_NUM = 0x7c,
337 OCPDR = 0xb0, /* OCP GPHY access */
338#define OCPDR_WRITE_CMD 0x80000000
339#define OCPDR_READ_CMD 0x00000000
340#define OCPDR_REG_MASK 0x7f
341#define OCPDR_GPHY_REG_SHIFT 16
342#define OCPDR_DATA_MASK 0xffff
343 OCPAR = 0xb4,
344#define OCPAR_FLAG 0x80000000
345#define OCPAR_GPHY_WRITE_CMD 0x8000f060
346#define OCPAR_GPHY_READ_CMD 0x0000f060
hayeswang01dc7fe2011-03-21 01:50:28 +0000347 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
348 MISC = 0xf0, /* 8168e only. */
349 txpla_rst = (1 << 29)
françois romieuc0e45c12011-01-03 15:08:04 +0000350};
351
Francois Romieu07d3f512007-02-21 22:40:46 +0100352enum rtl_register_content {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 /* InterruptStatusBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100354 SYSErr = 0x8000,
355 PCSTimeout = 0x4000,
356 SWInt = 0x0100,
357 TxDescUnavail = 0x0080,
358 RxFIFOOver = 0x0040,
359 LinkChg = 0x0020,
360 RxOverflow = 0x0010,
361 TxErr = 0x0008,
362 TxOK = 0x0004,
363 RxErr = 0x0002,
364 RxOK = 0x0001,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
366 /* RxStatusDesc */
Francois Romieu9dccf612006-05-14 12:31:17 +0200367 RxFOVF = (1 << 23),
368 RxRWT = (1 << 22),
369 RxRES = (1 << 21),
370 RxRUNT = (1 << 20),
371 RxCRC = (1 << 19),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
373 /* ChipCmdBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100374 CmdReset = 0x10,
375 CmdRxEnb = 0x08,
376 CmdTxEnb = 0x04,
377 RxBufEmpty = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
Francois Romieu275391a2007-02-23 23:50:28 +0100379 /* TXPoll register p.5 */
380 HPQ = 0x80, /* Poll cmd on the high prio queue */
381 NPQ = 0x40, /* Poll cmd on the low prio queue */
382 FSWInt = 0x01, /* Forced software interrupt */
383
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 /* Cfg9346Bits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100385 Cfg9346_Lock = 0x00,
386 Cfg9346_Unlock = 0xc0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387
388 /* rx_mode_bits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100389 AcceptErr = 0x20,
390 AcceptRunt = 0x10,
391 AcceptBroadcast = 0x08,
392 AcceptMulticast = 0x04,
393 AcceptMyPhys = 0x02,
394 AcceptAllPhys = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395
396 /* RxConfigBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100397 RxCfgFIFOShift = 13,
398 RxCfgDMAShift = 8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399
400 /* TxConfigBits */
401 TxInterFrameGapShift = 24,
402 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
403
Francois Romieu5d06a992006-02-23 00:47:58 +0100404 /* Config1 register p.24 */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200405 LEDS1 = (1 << 7),
406 LEDS0 = (1 << 6),
Francois Romieufbac58f2007-10-04 22:51:38 +0200407 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200408 Speed_down = (1 << 4),
409 MEMMAP = (1 << 3),
410 IOMAP = (1 << 2),
411 VPD = (1 << 1),
Francois Romieu5d06a992006-02-23 00:47:58 +0100412 PMEnable = (1 << 0), /* Power Management Enable */
413
Francois Romieu6dccd162007-02-13 23:38:05 +0100414 /* Config2 register p. 25 */
415 PCI_Clock_66MHz = 0x01,
416 PCI_Clock_33MHz = 0x00,
417
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100418 /* Config3 register p.25 */
419 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
420 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200421 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100422
Francois Romieu5d06a992006-02-23 00:47:58 +0100423 /* Config5 register p.27 */
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100424 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
425 MWF = (1 << 5), /* Accept Multicast wakeup frame */
426 UWF = (1 << 4), /* Accept Unicast wakeup frame */
hayeswang01dc7fe2011-03-21 01:50:28 +0000427 spi_en = (1 << 3),
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100428 LanWake = (1 << 1), /* LanWake enable/disable */
Francois Romieu5d06a992006-02-23 00:47:58 +0100429 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
430
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 /* TBICSR p.28 */
432 TBIReset = 0x80000000,
433 TBILoopback = 0x40000000,
434 TBINwEnable = 0x20000000,
435 TBINwRestart = 0x10000000,
436 TBILinkOk = 0x02000000,
437 TBINwComplete = 0x01000000,
438
439 /* CPlusCmd p.31 */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200440 EnableBist = (1 << 15), // 8168 8101
441 Mac_dbgo_oe = (1 << 14), // 8168 8101
442 Normal_mode = (1 << 13), // unused
443 Force_half_dup = (1 << 12), // 8168 8101
444 Force_rxflow_en = (1 << 11), // 8168 8101
445 Force_txflow_en = (1 << 10), // 8168 8101
446 Cxpl_dbg_sel = (1 << 9), // 8168 8101
447 ASF = (1 << 8), // 8168 8101
448 PktCntrDisable = (1 << 7), // 8168 8101
449 Mac_dbgo_sel = 0x001c, // 8168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 RxVlan = (1 << 6),
451 RxChkSum = (1 << 5),
452 PCIDAC = (1 << 4),
453 PCIMulRW = (1 << 3),
Francois Romieu0e485152007-02-20 00:00:26 +0100454 INTT_0 = 0x0000, // 8168
455 INTT_1 = 0x0001, // 8168
456 INTT_2 = 0x0002, // 8168
457 INTT_3 = 0x0003, // 8168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458
459 /* rtl8169_PHYstatus */
Francois Romieu07d3f512007-02-21 22:40:46 +0100460 TBI_Enable = 0x80,
461 TxFlowCtrl = 0x40,
462 RxFlowCtrl = 0x20,
463 _1000bpsF = 0x10,
464 _100bps = 0x08,
465 _10bps = 0x04,
466 LinkStatus = 0x02,
467 FullDup = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469 /* _TBICSRBit */
Francois Romieu07d3f512007-02-21 22:40:46 +0100470 TBILinkOK = 0x02000000,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +0200471
472 /* DumpCounterCommand */
Francois Romieu07d3f512007-02-21 22:40:46 +0100473 CounterDump = 0x8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474};
475
Francois Romieu2b7b4312011-04-18 22:53:24 -0700476enum rtl_desc_bit {
477 /* First doubleword. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
479 RingEnd = (1 << 30), /* End of descriptor ring */
480 FirstFrag = (1 << 29), /* First segment of a packet */
481 LastFrag = (1 << 28), /* Final segment of a packet */
Francois Romieu2b7b4312011-04-18 22:53:24 -0700482};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
Francois Romieu2b7b4312011-04-18 22:53:24 -0700484/* Generic case. */
485enum rtl_tx_desc_bit {
486 /* First doubleword. */
487 TD_LSO = (1 << 27), /* Large Send Offload */
488#define TD_MSS_MAX 0x07ffu /* MSS value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489
Francois Romieu2b7b4312011-04-18 22:53:24 -0700490 /* Second doubleword. */
491 TxVlanTag = (1 << 17), /* Add VLAN tag */
492};
493
494/* 8169, 8168b and 810x except 8102e. */
495enum rtl_tx_desc_bit_0 {
496 /* First doubleword. */
497#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
498 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
499 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
500 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
501};
502
503/* 8102e, 8168c and beyond. */
504enum rtl_tx_desc_bit_1 {
505 /* Second doubleword. */
506#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
507 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
508 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
509 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
510};
511
512static const struct rtl_tx_desc_info {
513 struct {
514 u32 udp;
515 u32 tcp;
516 } checksum;
517 u16 mss_shift;
518 u16 opts_offset;
519} tx_desc_info [] = {
520 [RTL_TD_0] = {
521 .checksum = {
522 .udp = TD0_IP_CS | TD0_UDP_CS,
523 .tcp = TD0_IP_CS | TD0_TCP_CS
524 },
525 .mss_shift = TD0_MSS_SHIFT,
526 .opts_offset = 0
527 },
528 [RTL_TD_1] = {
529 .checksum = {
530 .udp = TD1_IP_CS | TD1_UDP_CS,
531 .tcp = TD1_IP_CS | TD1_TCP_CS
532 },
533 .mss_shift = TD1_MSS_SHIFT,
534 .opts_offset = 1
535 }
536};
537
538enum rtl_rx_desc_bit {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 /* Rx private */
540 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
541 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
542
543#define RxProtoUDP (PID1)
544#define RxProtoTCP (PID0)
545#define RxProtoIP (PID1 | PID0)
546#define RxProtoMask RxProtoIP
547
548 IPFail = (1 << 16), /* IP checksum failed */
549 UDPFail = (1 << 15), /* UDP/IP checksum failed */
550 TCPFail = (1 << 14), /* TCP/IP checksum failed */
551 RxVlanTag = (1 << 16), /* VLAN tag available */
552};
553
554#define RsvdMask 0x3fffc000
555
556struct TxDesc {
Rolf Eike Beer6cccd6e2007-05-21 22:11:04 +0200557 __le32 opts1;
558 __le32 opts2;
559 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560};
561
562struct RxDesc {
Rolf Eike Beer6cccd6e2007-05-21 22:11:04 +0200563 __le32 opts1;
564 __le32 opts2;
565 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566};
567
568struct ring_info {
569 struct sk_buff *skb;
570 u32 len;
571 u8 __pad[sizeof(void *) - sizeof(u32)];
572};
573
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200574enum features {
Francois Romieuccdffb92008-07-26 14:26:06 +0200575 RTL_FEATURE_WOL = (1 << 0),
576 RTL_FEATURE_MSI = (1 << 1),
577 RTL_FEATURE_GMII = (1 << 2),
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200578};
579
Ivan Vecera355423d2009-02-06 21:49:57 -0800580struct rtl8169_counters {
581 __le64 tx_packets;
582 __le64 rx_packets;
583 __le64 tx_errors;
584 __le32 rx_errors;
585 __le16 rx_missed;
586 __le16 align_errors;
587 __le32 tx_one_collision;
588 __le32 tx_multi_collision;
589 __le64 rx_unicast;
590 __le64 rx_broadcast;
591 __le32 rx_multicast;
592 __le16 tx_aborted;
593 __le16 tx_underun;
594};
595
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596struct rtl8169_private {
597 void __iomem *mmio_addr; /* memory map physical address */
598 struct pci_dev *pci_dev; /* Index of PCI device */
David Howellsc4028952006-11-22 14:57:56 +0000599 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700600 struct napi_struct napi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 spinlock_t lock; /* spin lock flag */
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200602 u32 msg_enable;
Francois Romieu2b7b4312011-04-18 22:53:24 -0700603 u16 txd_version;
604 u16 mac_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
606 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
607 u32 dirty_rx;
608 u32 dirty_tx;
609 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
610 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
611 dma_addr_t TxPhyAddr;
612 dma_addr_t RxPhyAddr;
Eric Dumazet6f0333b2010-10-11 11:17:47 +0000613 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 struct timer_list timer;
616 u16 cp_cmd;
Francois Romieu0e485152007-02-20 00:00:26 +0100617 u16 intr_event;
618 u16 napi_event;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 u16 intr_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 int phy_1000_ctrl_reg;
françois romieuc0e45c12011-01-03 15:08:04 +0000621
622 struct mdio_ops {
623 void (*write)(void __iomem *, int, int);
624 int (*read)(void __iomem *, int);
625 } mdio_ops;
626
françois romieu065c27c2011-01-03 15:08:12 +0000627 struct pll_power_ops {
628 void (*down)(struct rtl8169_private *);
629 void (*up)(struct rtl8169_private *);
630 } pll_power_ops;
631
Oliver Neukum54405cd2011-01-06 21:55:13 +0100632 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
Francois Romieuccdffb92008-07-26 14:26:06 +0200633 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
françois romieu4da19632011-01-03 15:07:55 +0000634 void (*phy_reset_enable)(struct rtl8169_private *tp);
Francois Romieu07ce4062007-02-23 23:36:39 +0100635 void (*hw_start)(struct net_device *);
françois romieu4da19632011-01-03 15:07:55 +0000636 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 unsigned int (*link_ok)(void __iomem *);
Francois Romieu8b4ab282008-11-19 22:05:25 -0800638 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
Francois Romieu9c14cea2008-07-05 00:21:15 +0200639 int pcie_cap;
David Howellsc4028952006-11-22 14:57:56 +0000640 struct delayed_work task;
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200641 unsigned features;
Francois Romieuccdffb92008-07-26 14:26:06 +0200642
643 struct mii_if_info mii;
Ivan Vecera355423d2009-02-06 21:49:57 -0800644 struct rtl8169_counters counters;
Rafael J. Wysockie1759442010-03-14 14:33:51 +0000645 u32 saved_wolopts;
françois romieuf1e02ed2011-01-13 13:07:53 +0000646
647 const struct firmware *fw;
François Romieu953a12c2011-04-24 17:38:48 +0200648#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649};
650
Ralf Baechle979b6c12005-06-13 14:30:40 -0700651MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653module_param(use_dac, int, 0);
David S. Miller4300e8c2010-03-26 10:23:30 -0700654MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200655module_param_named(debug, debug.msg_enable, int, 0);
656MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657MODULE_LICENSE("GPL");
658MODULE_VERSION(RTL8169_VERSION);
françois romieubca03d52011-01-03 15:07:31 +0000659MODULE_FIRMWARE(FIRMWARE_8168D_1);
660MODULE_FIRMWARE(FIRMWARE_8168D_2);
hayeswang01dc7fe2011-03-21 01:50:28 +0000661MODULE_FIRMWARE(FIRMWARE_8168E_1);
662MODULE_FIRMWARE(FIRMWARE_8168E_2);
Hayes Wang5a5e4442011-02-22 17:26:21 +0800663MODULE_FIRMWARE(FIRMWARE_8105E_1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
665static int rtl8169_open(struct net_device *dev);
Stephen Hemminger613573252009-08-31 19:50:58 +0000666static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
667 struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100668static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669static int rtl8169_init_ring(struct net_device *dev);
Francois Romieu07ce4062007-02-23 23:36:39 +0100670static void rtl_hw_start(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671static int rtl8169_close(struct net_device *dev);
Francois Romieu07ce4062007-02-23 23:36:39 +0100672static void rtl_set_rx_mode(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673static void rtl8169_tx_timeout(struct net_device *dev);
Richard Dawe4dcb7d32005-05-27 21:12:00 +0200674static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700676 void __iomem *, u32 budget);
Richard Dawe4dcb7d32005-05-27 21:12:00 +0200677static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678static void rtl8169_down(struct net_device *dev);
Francois Romieu99f252b2007-04-02 22:59:59 +0200679static void rtl8169_rx_clear(struct rtl8169_private *tp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700680static int rtl8169_poll(struct napi_struct *napi, int budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682static const unsigned int rtl8169_rx_config =
Francois Romieu5b0384f2006-08-16 16:00:01 +0200683 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684
françois romieub646d902011-01-03 15:08:21 +0000685static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
686{
687 void __iomem *ioaddr = tp->mmio_addr;
688 int i;
689
690 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
691 for (i = 0; i < 20; i++) {
692 udelay(100);
693 if (RTL_R32(OCPAR) & OCPAR_FLAG)
694 break;
695 }
696 return RTL_R32(OCPDR);
697}
698
699static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
700{
701 void __iomem *ioaddr = tp->mmio_addr;
702 int i;
703
704 RTL_W32(OCPDR, data);
705 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
706 for (i = 0; i < 20; i++) {
707 udelay(100);
708 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
709 break;
710 }
711}
712
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800713static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
françois romieub646d902011-01-03 15:08:21 +0000714{
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800715 void __iomem *ioaddr = tp->mmio_addr;
françois romieub646d902011-01-03 15:08:21 +0000716 int i;
717
718 RTL_W8(ERIDR, cmd);
719 RTL_W32(ERIAR, 0x800010e8);
720 msleep(2);
721 for (i = 0; i < 5; i++) {
722 udelay(100);
723 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
724 break;
725 }
726
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800727 ocp_write(tp, 0x1, 0x30, 0x00000001);
françois romieub646d902011-01-03 15:08:21 +0000728}
729
730#define OOB_CMD_RESET 0x00
731#define OOB_CMD_DRIVER_START 0x05
732#define OOB_CMD_DRIVER_STOP 0x06
733
734static void rtl8168_driver_start(struct rtl8169_private *tp)
735{
736 int i;
hayeswang4804b3b2011-03-21 01:50:29 +0000737 u32 reg;
françois romieub646d902011-01-03 15:08:21 +0000738
739 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
740
hayeswang4804b3b2011-03-21 01:50:29 +0000741 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
742 reg = 0xb8;
743 else
744 reg = 0x10;
745
françois romieub646d902011-01-03 15:08:21 +0000746 for (i = 0; i < 10; i++) {
747 msleep(10);
hayeswang4804b3b2011-03-21 01:50:29 +0000748 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
françois romieub646d902011-01-03 15:08:21 +0000749 break;
750 }
751}
752
753static void rtl8168_driver_stop(struct rtl8169_private *tp)
754{
755 int i;
hayeswang4804b3b2011-03-21 01:50:29 +0000756 u32 reg;
françois romieub646d902011-01-03 15:08:21 +0000757
758 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
759
hayeswang4804b3b2011-03-21 01:50:29 +0000760 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
761 reg = 0xb8;
762 else
763 reg = 0x10;
764
françois romieub646d902011-01-03 15:08:21 +0000765 for (i = 0; i < 10; i++) {
766 msleep(10);
hayeswang4804b3b2011-03-21 01:50:29 +0000767 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
françois romieub646d902011-01-03 15:08:21 +0000768 break;
769 }
770}
771
hayeswang4804b3b2011-03-21 01:50:29 +0000772static int r8168dp_check_dash(struct rtl8169_private *tp)
773{
774 u32 reg;
775
776 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
777 reg = 0xb8;
778 else
779 reg = 0x10;
780
781 if (ocp_read(tp, 0xF, reg) & 0x00008000)
782 return 1;
783 else
784 return 0;
785}
françois romieub646d902011-01-03 15:08:21 +0000786
françois romieu4da19632011-01-03 15:07:55 +0000787static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788{
789 int i;
790
Francois Romieua6baf3a2007-11-08 23:23:21 +0100791 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792
Francois Romieu23714082006-01-29 00:49:09 +0100793 for (i = 20; i > 0; i--) {
Francois Romieu07d3f512007-02-21 22:40:46 +0100794 /*
795 * Check if the RTL8169 has completed writing to the specified
796 * MII register.
797 */
Francois Romieu5b0384f2006-08-16 16:00:01 +0200798 if (!(RTL_R32(PHYAR) & 0x80000000))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 break;
Francois Romieu23714082006-01-29 00:49:09 +0100800 udelay(25);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 }
Timo Teräs024a07b2010-06-06 15:38:47 -0700802 /*
Timo Teräs81a95f02010-06-09 17:31:48 -0700803 * According to hardware specs a 20us delay is required after write
804 * complete indication, but before sending next command.
Timo Teräs024a07b2010-06-06 15:38:47 -0700805 */
Timo Teräs81a95f02010-06-09 17:31:48 -0700806 udelay(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807}
808
françois romieu4da19632011-01-03 15:07:55 +0000809static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810{
811 int i, value = -1;
812
Francois Romieua6baf3a2007-11-08 23:23:21 +0100813 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
Francois Romieu23714082006-01-29 00:49:09 +0100815 for (i = 20; i > 0; i--) {
Francois Romieu07d3f512007-02-21 22:40:46 +0100816 /*
817 * Check if the RTL8169 has completed retrieving data from
818 * the specified MII register.
819 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 if (RTL_R32(PHYAR) & 0x80000000) {
Francois Romieua6baf3a2007-11-08 23:23:21 +0100821 value = RTL_R32(PHYAR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822 break;
823 }
Francois Romieu23714082006-01-29 00:49:09 +0100824 udelay(25);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 }
Timo Teräs81a95f02010-06-09 17:31:48 -0700826 /*
827 * According to hardware specs a 20us delay is required after read
828 * complete indication, but before sending next command.
829 */
830 udelay(20);
831
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 return value;
833}
834
françois romieuc0e45c12011-01-03 15:08:04 +0000835static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
836{
837 int i;
838
839 RTL_W32(OCPDR, data |
840 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
841 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
842 RTL_W32(EPHY_RXER_NUM, 0);
843
844 for (i = 0; i < 100; i++) {
845 mdelay(1);
846 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
847 break;
848 }
849}
850
851static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
852{
853 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
854 (value & OCPDR_DATA_MASK));
855}
856
857static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
858{
859 int i;
860
861 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
862
863 mdelay(1);
864 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
865 RTL_W32(EPHY_RXER_NUM, 0);
866
867 for (i = 0; i < 100; i++) {
868 mdelay(1);
869 if (RTL_R32(OCPAR) & OCPAR_FLAG)
870 break;
871 }
872
873 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
874}
875
françois romieue6de30d2011-01-03 15:08:37 +0000876#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
877
878static void r8168dp_2_mdio_start(void __iomem *ioaddr)
879{
880 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
881}
882
883static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
884{
885 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
886}
887
888static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
889{
890 r8168dp_2_mdio_start(ioaddr);
891
892 r8169_mdio_write(ioaddr, reg_addr, value);
893
894 r8168dp_2_mdio_stop(ioaddr);
895}
896
897static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
898{
899 int value;
900
901 r8168dp_2_mdio_start(ioaddr);
902
903 value = r8169_mdio_read(ioaddr, reg_addr);
904
905 r8168dp_2_mdio_stop(ioaddr);
906
907 return value;
908}
909
françois romieu4da19632011-01-03 15:07:55 +0000910static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
Francois Romieudacf8152008-08-02 20:44:13 +0200911{
françois romieuc0e45c12011-01-03 15:08:04 +0000912 tp->mdio_ops.write(tp->mmio_addr, location, val);
Francois Romieudacf8152008-08-02 20:44:13 +0200913}
914
françois romieu4da19632011-01-03 15:07:55 +0000915static int rtl_readphy(struct rtl8169_private *tp, int location)
916{
françois romieuc0e45c12011-01-03 15:08:04 +0000917 return tp->mdio_ops.read(tp->mmio_addr, location);
françois romieu4da19632011-01-03 15:07:55 +0000918}
919
920static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
921{
922 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
923}
924
925static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
françois romieudaf9df62009-10-07 12:44:20 +0000926{
927 int val;
928
françois romieu4da19632011-01-03 15:07:55 +0000929 val = rtl_readphy(tp, reg_addr);
930 rtl_writephy(tp, reg_addr, (val | p) & ~m);
françois romieudaf9df62009-10-07 12:44:20 +0000931}
932
Francois Romieuccdffb92008-07-26 14:26:06 +0200933static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
934 int val)
935{
936 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +0200937
françois romieu4da19632011-01-03 15:07:55 +0000938 rtl_writephy(tp, location, val);
Francois Romieuccdffb92008-07-26 14:26:06 +0200939}
940
941static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
942{
943 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +0200944
françois romieu4da19632011-01-03 15:07:55 +0000945 return rtl_readphy(tp, location);
Francois Romieuccdffb92008-07-26 14:26:06 +0200946}
947
Francois Romieudacf8152008-08-02 20:44:13 +0200948static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
949{
950 unsigned int i;
951
952 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
953 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
954
955 for (i = 0; i < 100; i++) {
956 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
957 break;
958 udelay(10);
959 }
960}
961
962static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
963{
964 u16 value = 0xffff;
965 unsigned int i;
966
967 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
968
969 for (i = 0; i < 100; i++) {
970 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
971 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
972 break;
973 }
974 udelay(10);
975 }
976
977 return value;
978}
979
980static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
981{
982 unsigned int i;
983
984 RTL_W32(CSIDR, value);
985 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
986 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
987
988 for (i = 0; i < 100; i++) {
989 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
990 break;
991 udelay(10);
992 }
993}
994
995static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
996{
997 u32 value = ~0x00;
998 unsigned int i;
999
1000 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1001 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1002
1003 for (i = 0; i < 100; i++) {
1004 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1005 value = RTL_R32(CSIDR);
1006 break;
1007 }
1008 udelay(10);
1009 }
1010
1011 return value;
1012}
1013
françois romieudaf9df62009-10-07 12:44:20 +00001014static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1015{
1016 u8 value = 0xff;
1017 unsigned int i;
1018
1019 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1020
1021 for (i = 0; i < 300; i++) {
1022 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1023 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1024 break;
1025 }
1026 udelay(100);
1027 }
1028
1029 return value;
1030}
1031
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1033{
1034 RTL_W16(IntrMask, 0x0000);
1035
1036 RTL_W16(IntrStatus, 0xffff);
1037}
1038
1039static void rtl8169_asic_down(void __iomem *ioaddr)
1040{
1041 RTL_W8(ChipCmd, 0x00);
1042 rtl8169_irq_mask_and_ack(ioaddr);
1043 RTL_R16(CPlusCmd);
1044}
1045
françois romieu4da19632011-01-03 15:07:55 +00001046static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047{
françois romieu4da19632011-01-03 15:07:55 +00001048 void __iomem *ioaddr = tp->mmio_addr;
1049
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 return RTL_R32(TBICSR) & TBIReset;
1051}
1052
françois romieu4da19632011-01-03 15:07:55 +00001053static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054{
françois romieu4da19632011-01-03 15:07:55 +00001055 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056}
1057
1058static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1059{
1060 return RTL_R32(TBICSR) & TBILinkOk;
1061}
1062
1063static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1064{
1065 return RTL_R8(PHYstatus) & LinkStatus;
1066}
1067
françois romieu4da19632011-01-03 15:07:55 +00001068static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069{
françois romieu4da19632011-01-03 15:07:55 +00001070 void __iomem *ioaddr = tp->mmio_addr;
1071
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1073}
1074
françois romieu4da19632011-01-03 15:07:55 +00001075static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076{
1077 unsigned int val;
1078
françois romieu4da19632011-01-03 15:07:55 +00001079 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1080 rtl_writephy(tp, MII_BMCR, val & 0xffff);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081}
1082
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001083static void __rtl8169_check_link_status(struct net_device *dev,
Francois Romieu07d3f512007-02-21 22:40:46 +01001084 struct rtl8169_private *tp,
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001085 void __iomem *ioaddr,
1086 bool pm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087{
1088 unsigned long flags;
1089
1090 spin_lock_irqsave(&tp->lock, flags);
1091 if (tp->link_ok(ioaddr)) {
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001092 /* This is to cancel a scheduled suspend if there's one. */
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001093 if (pm)
1094 pm_request_resume(&tp->pci_dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 netif_carrier_on(dev);
Francois Romieu1519e572011-02-03 12:02:36 +01001096 if (net_ratelimit())
1097 netif_info(tp, ifup, dev, "link up\n");
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001098 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 netif_carrier_off(dev);
Joe Perchesbf82c182010-02-09 11:49:50 +00001100 netif_info(tp, ifdown, dev, "link down\n");
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001101 if (pm)
1102 pm_schedule_suspend(&tp->pci_dev->dev, 100);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001103 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 spin_unlock_irqrestore(&tp->lock, flags);
1105}
1106
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001107static void rtl8169_check_link_status(struct net_device *dev,
1108 struct rtl8169_private *tp,
1109 void __iomem *ioaddr)
1110{
1111 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1112}
1113
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001114#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1115
1116static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1117{
1118 void __iomem *ioaddr = tp->mmio_addr;
1119 u8 options;
1120 u32 wolopts = 0;
1121
1122 options = RTL_R8(Config1);
1123 if (!(options & PMEnable))
1124 return 0;
1125
1126 options = RTL_R8(Config3);
1127 if (options & LinkUp)
1128 wolopts |= WAKE_PHY;
1129 if (options & MagicPacket)
1130 wolopts |= WAKE_MAGIC;
1131
1132 options = RTL_R8(Config5);
1133 if (options & UWF)
1134 wolopts |= WAKE_UCAST;
1135 if (options & BWF)
1136 wolopts |= WAKE_BCAST;
1137 if (options & MWF)
1138 wolopts |= WAKE_MCAST;
1139
1140 return wolopts;
1141}
1142
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001143static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1144{
1145 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001146
1147 spin_lock_irq(&tp->lock);
1148
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001149 wol->supported = WAKE_ANY;
1150 wol->wolopts = __rtl8169_get_wol(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001151
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001152 spin_unlock_irq(&tp->lock);
1153}
1154
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001155static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001156{
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001157 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu07d3f512007-02-21 22:40:46 +01001158 unsigned int i;
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001159 static const struct {
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001160 u32 opt;
1161 u16 reg;
1162 u8 mask;
1163 } cfg[] = {
1164 { WAKE_ANY, Config1, PMEnable },
1165 { WAKE_PHY, Config3, LinkUp },
1166 { WAKE_MAGIC, Config3, MagicPacket },
1167 { WAKE_UCAST, Config5, UWF },
1168 { WAKE_BCAST, Config5, BWF },
1169 { WAKE_MCAST, Config5, MWF },
1170 { WAKE_ANY, Config5, LanWake }
1171 };
1172
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001173 RTL_W8(Cfg9346, Cfg9346_Unlock);
1174
1175 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1176 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001177 if (wolopts & cfg[i].opt)
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001178 options |= cfg[i].mask;
1179 RTL_W8(cfg[i].reg, options);
1180 }
1181
1182 RTL_W8(Cfg9346, Cfg9346_Lock);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001183}
1184
1185static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1186{
1187 struct rtl8169_private *tp = netdev_priv(dev);
1188
1189 spin_lock_irq(&tp->lock);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001190
Francois Romieuf23e7fd2007-10-04 22:36:14 +02001191 if (wol->wolopts)
1192 tp->features |= RTL_FEATURE_WOL;
1193 else
1194 tp->features &= ~RTL_FEATURE_WOL;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001195 __rtl8169_set_wol(tp, wol->wolopts);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001196 spin_unlock_irq(&tp->lock);
1197
françois romieuea809072010-11-08 13:23:58 +00001198 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1199
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001200 return 0;
1201}
1202
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203static void rtl8169_get_drvinfo(struct net_device *dev,
1204 struct ethtool_drvinfo *info)
1205{
1206 struct rtl8169_private *tp = netdev_priv(dev);
1207
1208 strcpy(info->driver, MODULENAME);
1209 strcpy(info->version, RTL8169_VERSION);
1210 strcpy(info->bus_info, pci_name(tp->pci_dev));
1211}
1212
1213static int rtl8169_get_regs_len(struct net_device *dev)
1214{
1215 return R8169_REGS_SIZE;
1216}
1217
1218static int rtl8169_set_speed_tbi(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001219 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220{
1221 struct rtl8169_private *tp = netdev_priv(dev);
1222 void __iomem *ioaddr = tp->mmio_addr;
1223 int ret = 0;
1224 u32 reg;
1225
1226 reg = RTL_R32(TBICSR);
1227 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1228 (duplex == DUPLEX_FULL)) {
1229 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1230 } else if (autoneg == AUTONEG_ENABLE)
1231 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1232 else {
Joe Perchesbf82c182010-02-09 11:49:50 +00001233 netif_warn(tp, link, dev,
1234 "incorrect speed setting refused in TBI mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 ret = -EOPNOTSUPP;
1236 }
1237
1238 return ret;
1239}
1240
1241static int rtl8169_set_speed_xmii(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001242 u8 autoneg, u16 speed, u8 duplex, u32 adv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243{
1244 struct rtl8169_private *tp = netdev_priv(dev);
françois romieu3577aa12009-05-19 10:46:48 +00001245 int giga_ctrl, bmcr;
Oliver Neukum54405cd2011-01-06 21:55:13 +01001246 int rc = -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247
Hayes Wang716b50a2011-02-22 17:26:18 +08001248 rtl_writephy(tp, 0x1f, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249
1250 if (autoneg == AUTONEG_ENABLE) {
françois romieu3577aa12009-05-19 10:46:48 +00001251 int auto_nego;
1252
françois romieu4da19632011-01-03 15:07:55 +00001253 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
Oliver Neukum54405cd2011-01-06 21:55:13 +01001254 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1255 ADVERTISE_100HALF | ADVERTISE_100FULL);
1256
1257 if (adv & ADVERTISED_10baseT_Half)
1258 auto_nego |= ADVERTISE_10HALF;
1259 if (adv & ADVERTISED_10baseT_Full)
1260 auto_nego |= ADVERTISE_10FULL;
1261 if (adv & ADVERTISED_100baseT_Half)
1262 auto_nego |= ADVERTISE_100HALF;
1263 if (adv & ADVERTISED_100baseT_Full)
1264 auto_nego |= ADVERTISE_100FULL;
1265
françois romieu3577aa12009-05-19 10:46:48 +00001266 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1267
françois romieu4da19632011-01-03 15:07:55 +00001268 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
françois romieu3577aa12009-05-19 10:46:48 +00001269 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1270
1271 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1272 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1273 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1274 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1275 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1276 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1277 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1278 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
Hayes Wang5a5e4442011-02-22 17:26:21 +08001279 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1280 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1281 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
Oliver Neukum54405cd2011-01-06 21:55:13 +01001282 if (adv & ADVERTISED_1000baseT_Half)
1283 giga_ctrl |= ADVERTISE_1000HALF;
1284 if (adv & ADVERTISED_1000baseT_Full)
1285 giga_ctrl |= ADVERTISE_1000FULL;
1286 } else if (adv & (ADVERTISED_1000baseT_Half |
1287 ADVERTISED_1000baseT_Full)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00001288 netif_info(tp, link, dev,
1289 "PHY does not support 1000Mbps\n");
Oliver Neukum54405cd2011-01-06 21:55:13 +01001290 goto out;
Francois Romieubcf0bf92006-07-26 23:14:13 +02001291 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292
françois romieu3577aa12009-05-19 10:46:48 +00001293 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
Francois Romieu623a1592006-05-14 12:42:14 +02001294
françois romieu4da19632011-01-03 15:07:55 +00001295 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1296 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
françois romieu3577aa12009-05-19 10:46:48 +00001297 } else {
1298 giga_ctrl = 0;
1299
1300 if (speed == SPEED_10)
1301 bmcr = 0;
1302 else if (speed == SPEED_100)
1303 bmcr = BMCR_SPEED100;
1304 else
Oliver Neukum54405cd2011-01-06 21:55:13 +01001305 goto out;
françois romieu3577aa12009-05-19 10:46:48 +00001306
1307 if (duplex == DUPLEX_FULL)
1308 bmcr |= BMCR_FULLDPLX;
Roger So2584fbc2007-07-31 23:52:42 +02001309 }
1310
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311 tp->phy_1000_ctrl_reg = giga_ctrl;
1312
françois romieu4da19632011-01-03 15:07:55 +00001313 rtl_writephy(tp, MII_BMCR, bmcr);
françois romieu3577aa12009-05-19 10:46:48 +00001314
1315 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1316 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1317 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
françois romieu4da19632011-01-03 15:07:55 +00001318 rtl_writephy(tp, 0x17, 0x2138);
1319 rtl_writephy(tp, 0x0e, 0x0260);
françois romieu3577aa12009-05-19 10:46:48 +00001320 } else {
françois romieu4da19632011-01-03 15:07:55 +00001321 rtl_writephy(tp, 0x17, 0x2108);
1322 rtl_writephy(tp, 0x0e, 0x0000);
françois romieu3577aa12009-05-19 10:46:48 +00001323 }
1324 }
1325
Oliver Neukum54405cd2011-01-06 21:55:13 +01001326 rc = 0;
1327out:
1328 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329}
1330
1331static int rtl8169_set_speed(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001332 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001333{
1334 struct rtl8169_private *tp = netdev_priv(dev);
1335 int ret;
1336
Oliver Neukum54405cd2011-01-06 21:55:13 +01001337 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338
Francois Romieu64e4bfb2006-08-17 12:43:06 +02001339 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1341
1342 return ret;
1343}
1344
1345static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1346{
1347 struct rtl8169_private *tp = netdev_priv(dev);
1348 unsigned long flags;
1349 int ret;
1350
1351 spin_lock_irqsave(&tp->lock, flags);
Oliver Neukum54405cd2011-01-06 21:55:13 +01001352 ret = rtl8169_set_speed(dev,
1353 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354 spin_unlock_irqrestore(&tp->lock, flags);
Francois Romieu5b0384f2006-08-16 16:00:01 +02001355
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356 return ret;
1357}
1358
Michał Mirosław350fb322011-04-08 06:35:56 +00001359static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001360{
Francois Romieu2b7b4312011-04-18 22:53:24 -07001361 if (dev->mtu > TD_MSS_MAX)
Michał Mirosław350fb322011-04-08 06:35:56 +00001362 features &= ~NETIF_F_ALL_TSO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363
Michał Mirosław350fb322011-04-08 06:35:56 +00001364 return features;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365}
1366
Michał Mirosław350fb322011-04-08 06:35:56 +00001367static int rtl8169_set_features(struct net_device *dev, u32 features)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 void __iomem *ioaddr = tp->mmio_addr;
1371 unsigned long flags;
1372
1373 spin_lock_irqsave(&tp->lock, flags);
1374
Michał Mirosław350fb322011-04-08 06:35:56 +00001375 if (features & NETIF_F_RXCSUM)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 tp->cp_cmd |= RxChkSum;
1377 else
1378 tp->cp_cmd &= ~RxChkSum;
1379
Michał Mirosław350fb322011-04-08 06:35:56 +00001380 if (dev->features & NETIF_F_HW_VLAN_RX)
1381 tp->cp_cmd |= RxVlan;
1382 else
1383 tp->cp_cmd &= ~RxVlan;
1384
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385 RTL_W16(CPlusCmd, tp->cp_cmd);
1386 RTL_R16(CPlusCmd);
1387
1388 spin_unlock_irqrestore(&tp->lock, flags);
1389
1390 return 0;
1391}
1392
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1394 struct sk_buff *skb)
1395{
Jesse Grosseab6d182010-10-20 13:56:03 +00001396 return (vlan_tx_tag_present(skb)) ?
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1398}
1399
Francois Romieu7a8fc772011-03-01 17:18:33 +01001400static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401{
1402 u32 opts2 = le32_to_cpu(desc->opts2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403
Francois Romieu7a8fc772011-03-01 17:18:33 +01001404 if (opts2 & RxVlanTag)
1405 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
Eric Dumazet2edae082010-09-06 18:46:39 +00001406
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 desc->opts2 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408}
1409
Francois Romieuccdffb92008-07-26 14:26:06 +02001410static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411{
1412 struct rtl8169_private *tp = netdev_priv(dev);
1413 void __iomem *ioaddr = tp->mmio_addr;
1414 u32 status;
1415
1416 cmd->supported =
1417 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1418 cmd->port = PORT_FIBRE;
1419 cmd->transceiver = XCVR_INTERNAL;
1420
1421 status = RTL_R32(TBICSR);
1422 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1423 cmd->autoneg = !!(status & TBINwEnable);
1424
1425 cmd->speed = SPEED_1000;
1426 cmd->duplex = DUPLEX_FULL; /* Always set */
Francois Romieuccdffb92008-07-26 14:26:06 +02001427
1428 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429}
1430
Francois Romieuccdffb92008-07-26 14:26:06 +02001431static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432{
1433 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001434
Francois Romieuccdffb92008-07-26 14:26:06 +02001435 return mii_ethtool_gset(&tp->mii, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436}
1437
1438static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1439{
1440 struct rtl8169_private *tp = netdev_priv(dev);
1441 unsigned long flags;
Francois Romieuccdffb92008-07-26 14:26:06 +02001442 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443
1444 spin_lock_irqsave(&tp->lock, flags);
1445
Francois Romieuccdffb92008-07-26 14:26:06 +02001446 rc = tp->get_settings(dev, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447
1448 spin_unlock_irqrestore(&tp->lock, flags);
Francois Romieuccdffb92008-07-26 14:26:06 +02001449 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450}
1451
1452static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1453 void *p)
1454{
Francois Romieu5b0384f2006-08-16 16:00:01 +02001455 struct rtl8169_private *tp = netdev_priv(dev);
1456 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457
Francois Romieu5b0384f2006-08-16 16:00:01 +02001458 if (regs->len > R8169_REGS_SIZE)
1459 regs->len = R8169_REGS_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460
Francois Romieu5b0384f2006-08-16 16:00:01 +02001461 spin_lock_irqsave(&tp->lock, flags);
1462 memcpy_fromio(p, tp->mmio_addr, regs->len);
1463 spin_unlock_irqrestore(&tp->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464}
1465
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001466static u32 rtl8169_get_msglevel(struct net_device *dev)
1467{
1468 struct rtl8169_private *tp = netdev_priv(dev);
1469
1470 return tp->msg_enable;
1471}
1472
1473static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1474{
1475 struct rtl8169_private *tp = netdev_priv(dev);
1476
1477 tp->msg_enable = value;
1478}
1479
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001480static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1481 "tx_packets",
1482 "rx_packets",
1483 "tx_errors",
1484 "rx_errors",
1485 "rx_missed",
1486 "align_errors",
1487 "tx_single_collisions",
1488 "tx_multi_collisions",
1489 "unicast",
1490 "broadcast",
1491 "multicast",
1492 "tx_aborted",
1493 "tx_underrun",
1494};
1495
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001496static int rtl8169_get_sset_count(struct net_device *dev, int sset)
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001497{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001498 switch (sset) {
1499 case ETH_SS_STATS:
1500 return ARRAY_SIZE(rtl8169_gstrings);
1501 default:
1502 return -EOPNOTSUPP;
1503 }
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001504}
1505
Ivan Vecera355423d2009-02-06 21:49:57 -08001506static void rtl8169_update_counters(struct net_device *dev)
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001507{
1508 struct rtl8169_private *tp = netdev_priv(dev);
1509 void __iomem *ioaddr = tp->mmio_addr;
1510 struct rtl8169_counters *counters;
1511 dma_addr_t paddr;
1512 u32 cmd;
Ivan Vecera355423d2009-02-06 21:49:57 -08001513 int wait = 1000;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001514 struct device *d = &tp->pci_dev->dev;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001515
Ivan Vecera355423d2009-02-06 21:49:57 -08001516 /*
1517 * Some chips are unable to dump tally counters when the receiver
1518 * is disabled.
1519 */
1520 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1521 return;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001522
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001523 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001524 if (!counters)
1525 return;
1526
1527 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07001528 cmd = (u64)paddr & DMA_BIT_MASK(32);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001529 RTL_W32(CounterAddrLow, cmd);
1530 RTL_W32(CounterAddrLow, cmd | CounterDump);
1531
Ivan Vecera355423d2009-02-06 21:49:57 -08001532 while (wait--) {
1533 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1534 /* copy updated counters */
1535 memcpy(&tp->counters, counters, sizeof(*counters));
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001536 break;
Ivan Vecera355423d2009-02-06 21:49:57 -08001537 }
1538 udelay(10);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001539 }
1540
1541 RTL_W32(CounterAddrLow, 0);
1542 RTL_W32(CounterAddrHigh, 0);
1543
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001544 dma_free_coherent(d, sizeof(*counters), counters, paddr);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001545}
1546
Ivan Vecera355423d2009-02-06 21:49:57 -08001547static void rtl8169_get_ethtool_stats(struct net_device *dev,
1548 struct ethtool_stats *stats, u64 *data)
1549{
1550 struct rtl8169_private *tp = netdev_priv(dev);
1551
1552 ASSERT_RTNL();
1553
1554 rtl8169_update_counters(dev);
1555
1556 data[0] = le64_to_cpu(tp->counters.tx_packets);
1557 data[1] = le64_to_cpu(tp->counters.rx_packets);
1558 data[2] = le64_to_cpu(tp->counters.tx_errors);
1559 data[3] = le32_to_cpu(tp->counters.rx_errors);
1560 data[4] = le16_to_cpu(tp->counters.rx_missed);
1561 data[5] = le16_to_cpu(tp->counters.align_errors);
1562 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1563 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1564 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1565 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1566 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1567 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1568 data[12] = le16_to_cpu(tp->counters.tx_underun);
1569}
1570
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001571static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1572{
1573 switch(stringset) {
1574 case ETH_SS_STATS:
1575 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1576 break;
1577 }
1578}
1579
Jeff Garzik7282d492006-09-13 14:30:00 -04001580static const struct ethtool_ops rtl8169_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581 .get_drvinfo = rtl8169_get_drvinfo,
1582 .get_regs_len = rtl8169_get_regs_len,
1583 .get_link = ethtool_op_get_link,
1584 .get_settings = rtl8169_get_settings,
1585 .set_settings = rtl8169_set_settings,
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001586 .get_msglevel = rtl8169_get_msglevel,
1587 .set_msglevel = rtl8169_set_msglevel,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001588 .get_regs = rtl8169_get_regs,
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001589 .get_wol = rtl8169_get_wol,
1590 .set_wol = rtl8169_set_wol,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001591 .get_strings = rtl8169_get_strings,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001592 .get_sset_count = rtl8169_get_sset_count,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001593 .get_ethtool_stats = rtl8169_get_ethtool_stats,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594};
1595
Francois Romieu07d3f512007-02-21 22:40:46 +01001596static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1597 void __iomem *ioaddr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598{
Francois Romieu0e485152007-02-20 00:00:26 +01001599 /*
1600 * The driver currently handles the 8168Bf and the 8168Be identically
1601 * but they can be identified more specifically through the test below
1602 * if needed:
1603 *
1604 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
Francois Romieu01272152007-02-20 22:58:51 +01001605 *
1606 * Same thing for the 8101Eb and the 8101Ec:
1607 *
1608 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
Francois Romieu0e485152007-02-20 00:00:26 +01001609 */
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001610 static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 u32 mask;
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001612 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 int mac_version;
1614 } mac_info[] = {
hayeswang01dc7fe2011-03-21 01:50:28 +00001615 /* 8168E family. */
1616 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1617 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1618 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1619
Francois Romieu5b538df2008-07-20 16:22:45 +02001620 /* 8168D family. */
françois romieudaf9df62009-10-07 12:44:20 +00001621 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1622 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
françois romieudaf9df62009-10-07 12:44:20 +00001623 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
Francois Romieu5b538df2008-07-20 16:22:45 +02001624
françois romieue6de30d2011-01-03 15:08:37 +00001625 /* 8168DP family. */
1626 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1627 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
hayeswang4804b3b2011-03-21 01:50:29 +00001628 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
françois romieue6de30d2011-01-03 15:08:37 +00001629
Francois Romieuef808d52008-06-29 13:10:54 +02001630 /* 8168C family. */
Francois Romieu17c99292010-07-11 17:10:09 -07001631 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
Francois Romieuef3386f2008-06-29 12:24:30 +02001632 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
Francois Romieuef808d52008-06-29 13:10:54 +02001633 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
Francois Romieu7f3e3d32008-07-20 18:53:20 +02001634 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001635 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1636 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
Francois Romieu197ff762008-06-28 13:16:02 +02001637 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
Francois Romieu6fb07052008-06-29 11:54:28 +02001638 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
Francois Romieuef808d52008-06-29 13:10:54 +02001639 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001640
1641 /* 8168B family. */
1642 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1643 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1644 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1645 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1646
1647 /* 8101 family. */
hayeswang36a0e6c2011-03-21 01:50:30 +00001648 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
Hayes Wang5a5e4442011-02-22 17:26:21 +08001649 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1650 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1651 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001652 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1653 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1654 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1655 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1656 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1657 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001658 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001659 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001660 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001661 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1662 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001663 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1664 /* FIXME: where did these entries come from ? -- FR */
1665 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1666 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1667
1668 /* 8110 family. */
1669 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1670 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1671 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1672 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1673 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1674 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1675
Jean Delvaref21b75e2009-05-26 20:54:48 -07001676 /* Catch-all */
1677 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678 }, *p = mac_info;
1679 u32 reg;
1680
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001681 reg = RTL_R32(TxConfig);
1682 while ((reg & p->mask) != p->val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 p++;
1684 tp->mac_version = p->mac_version;
1685}
1686
1687static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1688{
Francois Romieubcf0bf92006-07-26 23:14:13 +02001689 dprintk("mac_version = 0x%02x\n", tp->mac_version);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001690}
1691
Francois Romieu867763c2007-08-17 18:21:58 +02001692struct phy_reg {
1693 u16 reg;
1694 u16 val;
1695};
1696
françois romieu4da19632011-01-03 15:07:55 +00001697static void rtl_writephy_batch(struct rtl8169_private *tp,
1698 const struct phy_reg *regs, int len)
Francois Romieu867763c2007-08-17 18:21:58 +02001699{
1700 while (len-- > 0) {
françois romieu4da19632011-01-03 15:07:55 +00001701 rtl_writephy(tp, regs->reg, regs->val);
Francois Romieu867763c2007-08-17 18:21:58 +02001702 regs++;
1703 }
1704}
1705
françois romieubca03d52011-01-03 15:07:31 +00001706#define PHY_READ 0x00000000
1707#define PHY_DATA_OR 0x10000000
1708#define PHY_DATA_AND 0x20000000
1709#define PHY_BJMPN 0x30000000
1710#define PHY_READ_EFUSE 0x40000000
1711#define PHY_READ_MAC_BYTE 0x50000000
1712#define PHY_WRITE_MAC_BYTE 0x60000000
1713#define PHY_CLEAR_READCOUNT 0x70000000
1714#define PHY_WRITE 0x80000000
1715#define PHY_READCOUNT_EQ_SKIP 0x90000000
1716#define PHY_COMP_EQ_SKIPN 0xa0000000
1717#define PHY_COMP_NEQ_SKIPN 0xb0000000
1718#define PHY_WRITE_PREVIOUS 0xc0000000
1719#define PHY_SKIPN 0xd0000000
1720#define PHY_DELAY_MS 0xe0000000
1721#define PHY_WRITE_ERI_WORD 0xf0000000
1722
1723static void
1724rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1725{
françois romieubca03d52011-01-03 15:07:31 +00001726 __le32 *phytable = (__le32 *)fw->data;
1727 struct net_device *dev = tp->dev;
hayeswang42b82dc2011-01-10 02:07:25 +00001728 size_t index, fw_size = fw->size / sizeof(*phytable);
1729 u32 predata, count;
françois romieubca03d52011-01-03 15:07:31 +00001730
1731 if (fw->size % sizeof(*phytable)) {
1732 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1733 return;
1734 }
1735
hayeswang42b82dc2011-01-10 02:07:25 +00001736 for (index = 0; index < fw_size; index++) {
1737 u32 action = le32_to_cpu(phytable[index]);
1738 u32 regno = (action & 0x0fff0000) >> 16;
françois romieubca03d52011-01-03 15:07:31 +00001739
hayeswang42b82dc2011-01-10 02:07:25 +00001740 switch(action & 0xf0000000) {
1741 case PHY_READ:
1742 case PHY_DATA_OR:
1743 case PHY_DATA_AND:
1744 case PHY_READ_EFUSE:
1745 case PHY_CLEAR_READCOUNT:
1746 case PHY_WRITE:
1747 case PHY_WRITE_PREVIOUS:
1748 case PHY_DELAY_MS:
françois romieubca03d52011-01-03 15:07:31 +00001749 break;
1750
hayeswang42b82dc2011-01-10 02:07:25 +00001751 case PHY_BJMPN:
1752 if (regno > index) {
1753 netif_err(tp, probe, tp->dev,
1754 "Out of range of firmware\n");
1755 return;
1756 }
1757 break;
1758 case PHY_READCOUNT_EQ_SKIP:
1759 if (index + 2 >= fw_size) {
1760 netif_err(tp, probe, tp->dev,
1761 "Out of range of firmware\n");
1762 return;
1763 }
1764 break;
1765 case PHY_COMP_EQ_SKIPN:
1766 case PHY_COMP_NEQ_SKIPN:
1767 case PHY_SKIPN:
1768 if (index + 1 + regno >= fw_size) {
1769 netif_err(tp, probe, tp->dev,
1770 "Out of range of firmware\n");
1771 return;
1772 }
1773 break;
1774
1775 case PHY_READ_MAC_BYTE:
1776 case PHY_WRITE_MAC_BYTE:
1777 case PHY_WRITE_ERI_WORD:
1778 default:
1779 netif_err(tp, probe, tp->dev,
1780 "Invalid action 0x%08x\n", action);
françois romieubca03d52011-01-03 15:07:31 +00001781 return;
1782 }
1783 }
1784
hayeswang42b82dc2011-01-10 02:07:25 +00001785 predata = 0;
1786 count = 0;
1787
1788 for (index = 0; index < fw_size; ) {
1789 u32 action = le32_to_cpu(phytable[index]);
françois romieubca03d52011-01-03 15:07:31 +00001790 u32 data = action & 0x0000ffff;
hayeswang42b82dc2011-01-10 02:07:25 +00001791 u32 regno = (action & 0x0fff0000) >> 16;
1792
1793 if (!action)
1794 break;
françois romieubca03d52011-01-03 15:07:31 +00001795
1796 switch(action & 0xf0000000) {
hayeswang42b82dc2011-01-10 02:07:25 +00001797 case PHY_READ:
1798 predata = rtl_readphy(tp, regno);
1799 count++;
1800 index++;
françois romieubca03d52011-01-03 15:07:31 +00001801 break;
hayeswang42b82dc2011-01-10 02:07:25 +00001802 case PHY_DATA_OR:
1803 predata |= data;
1804 index++;
1805 break;
1806 case PHY_DATA_AND:
1807 predata &= data;
1808 index++;
1809 break;
1810 case PHY_BJMPN:
1811 index -= regno;
1812 break;
1813 case PHY_READ_EFUSE:
1814 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1815 index++;
1816 break;
1817 case PHY_CLEAR_READCOUNT:
1818 count = 0;
1819 index++;
1820 break;
1821 case PHY_WRITE:
1822 rtl_writephy(tp, regno, data);
1823 index++;
1824 break;
1825 case PHY_READCOUNT_EQ_SKIP:
1826 if (count == data)
1827 index += 2;
1828 else
1829 index += 1;
1830 break;
1831 case PHY_COMP_EQ_SKIPN:
1832 if (predata == data)
1833 index += regno;
1834 index++;
1835 break;
1836 case PHY_COMP_NEQ_SKIPN:
1837 if (predata != data)
1838 index += regno;
1839 index++;
1840 break;
1841 case PHY_WRITE_PREVIOUS:
1842 rtl_writephy(tp, regno, predata);
1843 index++;
1844 break;
1845 case PHY_SKIPN:
1846 index += regno + 1;
1847 break;
1848 case PHY_DELAY_MS:
1849 mdelay(data);
1850 index++;
1851 break;
1852
1853 case PHY_READ_MAC_BYTE:
1854 case PHY_WRITE_MAC_BYTE:
1855 case PHY_WRITE_ERI_WORD:
françois romieubca03d52011-01-03 15:07:31 +00001856 default:
1857 BUG();
1858 }
1859 }
1860}
1861
françois romieuf1e02ed2011-01-13 13:07:53 +00001862static void rtl_release_firmware(struct rtl8169_private *tp)
1863{
François Romieu953a12c2011-04-24 17:38:48 +02001864 if (!IS_ERR_OR_NULL(tp->fw))
1865 release_firmware(tp->fw);
1866 tp->fw = RTL_FIRMWARE_UNKNOWN;
françois romieuf1e02ed2011-01-13 13:07:53 +00001867}
1868
François Romieu953a12c2011-04-24 17:38:48 +02001869static void rtl_apply_firmware(struct rtl8169_private *tp)
françois romieuf1e02ed2011-01-13 13:07:53 +00001870{
François Romieu953a12c2011-04-24 17:38:48 +02001871 const struct firmware *fw = tp->fw;
françois romieuf1e02ed2011-01-13 13:07:53 +00001872
1873 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
François Romieu953a12c2011-04-24 17:38:48 +02001874 if (!IS_ERR_OR_NULL(fw))
1875 rtl_phy_write_fw(tp, fw);
1876}
1877
1878static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1879{
1880 if (rtl_readphy(tp, reg) != val)
1881 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1882 else
1883 rtl_apply_firmware(tp);
françois romieuf1e02ed2011-01-13 13:07:53 +00001884}
1885
françois romieu4da19632011-01-03 15:07:55 +00001886static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001888 static const struct phy_reg phy_reg_init[] = {
françois romieu0b9b5712009-08-10 19:44:56 +00001889 { 0x1f, 0x0001 },
1890 { 0x06, 0x006e },
1891 { 0x08, 0x0708 },
1892 { 0x15, 0x4000 },
1893 { 0x18, 0x65c7 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894
françois romieu0b9b5712009-08-10 19:44:56 +00001895 { 0x1f, 0x0001 },
1896 { 0x03, 0x00a1 },
1897 { 0x02, 0x0008 },
1898 { 0x01, 0x0120 },
1899 { 0x00, 0x1000 },
1900 { 0x04, 0x0800 },
1901 { 0x04, 0x0000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902
françois romieu0b9b5712009-08-10 19:44:56 +00001903 { 0x03, 0xff41 },
1904 { 0x02, 0xdf60 },
1905 { 0x01, 0x0140 },
1906 { 0x00, 0x0077 },
1907 { 0x04, 0x7800 },
1908 { 0x04, 0x7000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909
françois romieu0b9b5712009-08-10 19:44:56 +00001910 { 0x03, 0x802f },
1911 { 0x02, 0x4f02 },
1912 { 0x01, 0x0409 },
1913 { 0x00, 0xf0f9 },
1914 { 0x04, 0x9800 },
1915 { 0x04, 0x9000 },
1916
1917 { 0x03, 0xdf01 },
1918 { 0x02, 0xdf20 },
1919 { 0x01, 0xff95 },
1920 { 0x00, 0xba00 },
1921 { 0x04, 0xa800 },
1922 { 0x04, 0xa000 },
1923
1924 { 0x03, 0xff41 },
1925 { 0x02, 0xdf20 },
1926 { 0x01, 0x0140 },
1927 { 0x00, 0x00bb },
1928 { 0x04, 0xb800 },
1929 { 0x04, 0xb000 },
1930
1931 { 0x03, 0xdf41 },
1932 { 0x02, 0xdc60 },
1933 { 0x01, 0x6340 },
1934 { 0x00, 0x007d },
1935 { 0x04, 0xd800 },
1936 { 0x04, 0xd000 },
1937
1938 { 0x03, 0xdf01 },
1939 { 0x02, 0xdf20 },
1940 { 0x01, 0x100a },
1941 { 0x00, 0xa0ff },
1942 { 0x04, 0xf800 },
1943 { 0x04, 0xf000 },
1944
1945 { 0x1f, 0x0000 },
1946 { 0x0b, 0x0000 },
1947 { 0x00, 0x9200 }
1948 };
1949
françois romieu4da19632011-01-03 15:07:55 +00001950 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001951}
1952
françois romieu4da19632011-01-03 15:07:55 +00001953static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu5615d9f2007-08-17 17:50:46 +02001954{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001955 static const struct phy_reg phy_reg_init[] = {
Francois Romieua441d7b2007-08-17 18:26:35 +02001956 { 0x1f, 0x0002 },
1957 { 0x01, 0x90d0 },
1958 { 0x1f, 0x0000 }
1959 };
1960
françois romieu4da19632011-01-03 15:07:55 +00001961 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5615d9f2007-08-17 17:50:46 +02001962}
1963
françois romieu4da19632011-01-03 15:07:55 +00001964static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
françois romieu2e9558562009-08-10 19:44:19 +00001965{
1966 struct pci_dev *pdev = tp->pci_dev;
1967 u16 vendor_id, device_id;
1968
1969 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1970 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1971
1972 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1973 return;
1974
françois romieu4da19632011-01-03 15:07:55 +00001975 rtl_writephy(tp, 0x1f, 0x0001);
1976 rtl_writephy(tp, 0x10, 0xf01b);
1977 rtl_writephy(tp, 0x1f, 0x0000);
françois romieu2e9558562009-08-10 19:44:19 +00001978}
1979
françois romieu4da19632011-01-03 15:07:55 +00001980static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
françois romieu2e9558562009-08-10 19:44:19 +00001981{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001982 static const struct phy_reg phy_reg_init[] = {
françois romieu2e9558562009-08-10 19:44:19 +00001983 { 0x1f, 0x0001 },
1984 { 0x04, 0x0000 },
1985 { 0x03, 0x00a1 },
1986 { 0x02, 0x0008 },
1987 { 0x01, 0x0120 },
1988 { 0x00, 0x1000 },
1989 { 0x04, 0x0800 },
1990 { 0x04, 0x9000 },
1991 { 0x03, 0x802f },
1992 { 0x02, 0x4f02 },
1993 { 0x01, 0x0409 },
1994 { 0x00, 0xf099 },
1995 { 0x04, 0x9800 },
1996 { 0x04, 0xa000 },
1997 { 0x03, 0xdf01 },
1998 { 0x02, 0xdf20 },
1999 { 0x01, 0xff95 },
2000 { 0x00, 0xba00 },
2001 { 0x04, 0xa800 },
2002 { 0x04, 0xf000 },
2003 { 0x03, 0xdf01 },
2004 { 0x02, 0xdf20 },
2005 { 0x01, 0x101a },
2006 { 0x00, 0xa0ff },
2007 { 0x04, 0xf800 },
2008 { 0x04, 0x0000 },
2009 { 0x1f, 0x0000 },
2010
2011 { 0x1f, 0x0001 },
2012 { 0x10, 0xf41b },
2013 { 0x14, 0xfb54 },
2014 { 0x18, 0xf5c7 },
2015 { 0x1f, 0x0000 },
2016
2017 { 0x1f, 0x0001 },
2018 { 0x17, 0x0cc0 },
2019 { 0x1f, 0x0000 }
2020 };
2021
françois romieu4da19632011-01-03 15:07:55 +00002022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieu2e9558562009-08-10 19:44:19 +00002023
françois romieu4da19632011-01-03 15:07:55 +00002024 rtl8169scd_hw_phy_config_quirk(tp);
françois romieu2e9558562009-08-10 19:44:19 +00002025}
2026
françois romieu4da19632011-01-03 15:07:55 +00002027static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
françois romieu8c7006a2009-08-10 19:43:29 +00002028{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002029 static const struct phy_reg phy_reg_init[] = {
françois romieu8c7006a2009-08-10 19:43:29 +00002030 { 0x1f, 0x0001 },
2031 { 0x04, 0x0000 },
2032 { 0x03, 0x00a1 },
2033 { 0x02, 0x0008 },
2034 { 0x01, 0x0120 },
2035 { 0x00, 0x1000 },
2036 { 0x04, 0x0800 },
2037 { 0x04, 0x9000 },
2038 { 0x03, 0x802f },
2039 { 0x02, 0x4f02 },
2040 { 0x01, 0x0409 },
2041 { 0x00, 0xf099 },
2042 { 0x04, 0x9800 },
2043 { 0x04, 0xa000 },
2044 { 0x03, 0xdf01 },
2045 { 0x02, 0xdf20 },
2046 { 0x01, 0xff95 },
2047 { 0x00, 0xba00 },
2048 { 0x04, 0xa800 },
2049 { 0x04, 0xf000 },
2050 { 0x03, 0xdf01 },
2051 { 0x02, 0xdf20 },
2052 { 0x01, 0x101a },
2053 { 0x00, 0xa0ff },
2054 { 0x04, 0xf800 },
2055 { 0x04, 0x0000 },
2056 { 0x1f, 0x0000 },
2057
2058 { 0x1f, 0x0001 },
2059 { 0x0b, 0x8480 },
2060 { 0x1f, 0x0000 },
2061
2062 { 0x1f, 0x0001 },
2063 { 0x18, 0x67c7 },
2064 { 0x04, 0x2000 },
2065 { 0x03, 0x002f },
2066 { 0x02, 0x4360 },
2067 { 0x01, 0x0109 },
2068 { 0x00, 0x3022 },
2069 { 0x04, 0x2800 },
2070 { 0x1f, 0x0000 },
2071
2072 { 0x1f, 0x0001 },
2073 { 0x17, 0x0cc0 },
2074 { 0x1f, 0x0000 }
2075 };
2076
françois romieu4da19632011-01-03 15:07:55 +00002077 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieu8c7006a2009-08-10 19:43:29 +00002078}
2079
françois romieu4da19632011-01-03 15:07:55 +00002080static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu236b8082008-05-30 16:11:48 +02002081{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002082 static const struct phy_reg phy_reg_init[] = {
Francois Romieu236b8082008-05-30 16:11:48 +02002083 { 0x10, 0xf41b },
2084 { 0x1f, 0x0000 }
2085 };
2086
françois romieu4da19632011-01-03 15:07:55 +00002087 rtl_writephy(tp, 0x1f, 0x0001);
2088 rtl_patchphy(tp, 0x16, 1 << 0);
Francois Romieu236b8082008-05-30 16:11:48 +02002089
françois romieu4da19632011-01-03 15:07:55 +00002090 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu236b8082008-05-30 16:11:48 +02002091}
2092
françois romieu4da19632011-01-03 15:07:55 +00002093static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu236b8082008-05-30 16:11:48 +02002094{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002095 static const struct phy_reg phy_reg_init[] = {
Francois Romieu236b8082008-05-30 16:11:48 +02002096 { 0x1f, 0x0001 },
2097 { 0x10, 0xf41b },
2098 { 0x1f, 0x0000 }
2099 };
2100
françois romieu4da19632011-01-03 15:07:55 +00002101 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu236b8082008-05-30 16:11:48 +02002102}
2103
françois romieu4da19632011-01-03 15:07:55 +00002104static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu867763c2007-08-17 18:21:58 +02002105{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002106 static const struct phy_reg phy_reg_init[] = {
Francois Romieu867763c2007-08-17 18:21:58 +02002107 { 0x1f, 0x0000 },
2108 { 0x1d, 0x0f00 },
2109 { 0x1f, 0x0002 },
2110 { 0x0c, 0x1ec8 },
2111 { 0x1f, 0x0000 }
2112 };
2113
françois romieu4da19632011-01-03 15:07:55 +00002114 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu867763c2007-08-17 18:21:58 +02002115}
2116
françois romieu4da19632011-01-03 15:07:55 +00002117static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
Francois Romieuef3386f2008-06-29 12:24:30 +02002118{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002119 static const struct phy_reg phy_reg_init[] = {
Francois Romieuef3386f2008-06-29 12:24:30 +02002120 { 0x1f, 0x0001 },
2121 { 0x1d, 0x3d98 },
2122 { 0x1f, 0x0000 }
2123 };
2124
françois romieu4da19632011-01-03 15:07:55 +00002125 rtl_writephy(tp, 0x1f, 0x0000);
2126 rtl_patchphy(tp, 0x14, 1 << 5);
2127 rtl_patchphy(tp, 0x0d, 1 << 5);
Francois Romieuef3386f2008-06-29 12:24:30 +02002128
françois romieu4da19632011-01-03 15:07:55 +00002129 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuef3386f2008-06-29 12:24:30 +02002130}
2131
françois romieu4da19632011-01-03 15:07:55 +00002132static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu867763c2007-08-17 18:21:58 +02002133{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002134 static const struct phy_reg phy_reg_init[] = {
Francois Romieua3f80672007-10-18 14:35:11 +02002135 { 0x1f, 0x0001 },
2136 { 0x12, 0x2300 },
Francois Romieu867763c2007-08-17 18:21:58 +02002137 { 0x1f, 0x0002 },
2138 { 0x00, 0x88d4 },
2139 { 0x01, 0x82b1 },
2140 { 0x03, 0x7002 },
2141 { 0x08, 0x9e30 },
2142 { 0x09, 0x01f0 },
2143 { 0x0a, 0x5500 },
2144 { 0x0c, 0x00c8 },
2145 { 0x1f, 0x0003 },
2146 { 0x12, 0xc096 },
2147 { 0x16, 0x000a },
Francois Romieuf50d4272008-05-30 16:07:07 +02002148 { 0x1f, 0x0000 },
2149 { 0x1f, 0x0000 },
2150 { 0x09, 0x2000 },
2151 { 0x09, 0x0000 }
Francois Romieu867763c2007-08-17 18:21:58 +02002152 };
2153
françois romieu4da19632011-01-03 15:07:55 +00002154 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuf50d4272008-05-30 16:07:07 +02002155
françois romieu4da19632011-01-03 15:07:55 +00002156 rtl_patchphy(tp, 0x14, 1 << 5);
2157 rtl_patchphy(tp, 0x0d, 1 << 5);
2158 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu867763c2007-08-17 18:21:58 +02002159}
2160
françois romieu4da19632011-01-03 15:07:55 +00002161static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu7da97ec2007-10-18 15:20:43 +02002162{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002163 static const struct phy_reg phy_reg_init[] = {
Francois Romieuf50d4272008-05-30 16:07:07 +02002164 { 0x1f, 0x0001 },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002165 { 0x12, 0x2300 },
Francois Romieuf50d4272008-05-30 16:07:07 +02002166 { 0x03, 0x802f },
2167 { 0x02, 0x4f02 },
2168 { 0x01, 0x0409 },
2169 { 0x00, 0xf099 },
2170 { 0x04, 0x9800 },
2171 { 0x04, 0x9000 },
2172 { 0x1d, 0x3d98 },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002173 { 0x1f, 0x0002 },
2174 { 0x0c, 0x7eb8 },
Francois Romieuf50d4272008-05-30 16:07:07 +02002175 { 0x06, 0x0761 },
2176 { 0x1f, 0x0003 },
2177 { 0x16, 0x0f0a },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002178 { 0x1f, 0x0000 }
2179 };
2180
françois romieu4da19632011-01-03 15:07:55 +00002181 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuf50d4272008-05-30 16:07:07 +02002182
françois romieu4da19632011-01-03 15:07:55 +00002183 rtl_patchphy(tp, 0x16, 1 << 0);
2184 rtl_patchphy(tp, 0x14, 1 << 5);
2185 rtl_patchphy(tp, 0x0d, 1 << 5);
2186 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu7da97ec2007-10-18 15:20:43 +02002187}
2188
françois romieu4da19632011-01-03 15:07:55 +00002189static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu197ff762008-06-28 13:16:02 +02002190{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002191 static const struct phy_reg phy_reg_init[] = {
Francois Romieu197ff762008-06-28 13:16:02 +02002192 { 0x1f, 0x0001 },
2193 { 0x12, 0x2300 },
2194 { 0x1d, 0x3d98 },
2195 { 0x1f, 0x0002 },
2196 { 0x0c, 0x7eb8 },
2197 { 0x06, 0x5461 },
2198 { 0x1f, 0x0003 },
2199 { 0x16, 0x0f0a },
2200 { 0x1f, 0x0000 }
2201 };
2202
françois romieu4da19632011-01-03 15:07:55 +00002203 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu197ff762008-06-28 13:16:02 +02002204
françois romieu4da19632011-01-03 15:07:55 +00002205 rtl_patchphy(tp, 0x16, 1 << 0);
2206 rtl_patchphy(tp, 0x14, 1 << 5);
2207 rtl_patchphy(tp, 0x0d, 1 << 5);
2208 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu197ff762008-06-28 13:16:02 +02002209}
2210
françois romieu4da19632011-01-03 15:07:55 +00002211static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu6fb07052008-06-29 11:54:28 +02002212{
françois romieu4da19632011-01-03 15:07:55 +00002213 rtl8168c_3_hw_phy_config(tp);
Francois Romieu6fb07052008-06-29 11:54:28 +02002214}
2215
françois romieubca03d52011-01-03 15:07:31 +00002216static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu5b538df2008-07-20 16:22:45 +02002217{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002218 static const struct phy_reg phy_reg_init_0[] = {
françois romieubca03d52011-01-03 15:07:31 +00002219 /* Channel Estimation */
Francois Romieu5b538df2008-07-20 16:22:45 +02002220 { 0x1f, 0x0001 },
françois romieudaf9df62009-10-07 12:44:20 +00002221 { 0x06, 0x4064 },
2222 { 0x07, 0x2863 },
2223 { 0x08, 0x059c },
2224 { 0x09, 0x26b4 },
2225 { 0x0a, 0x6a19 },
2226 { 0x0b, 0xdcc8 },
2227 { 0x10, 0xf06d },
2228 { 0x14, 0x7f68 },
2229 { 0x18, 0x7fd9 },
2230 { 0x1c, 0xf0ff },
2231 { 0x1d, 0x3d9c },
Francois Romieu5b538df2008-07-20 16:22:45 +02002232 { 0x1f, 0x0003 },
françois romieudaf9df62009-10-07 12:44:20 +00002233 { 0x12, 0xf49f },
2234 { 0x13, 0x070b },
2235 { 0x1a, 0x05ad },
françois romieubca03d52011-01-03 15:07:31 +00002236 { 0x14, 0x94c0 },
2237
2238 /*
2239 * Tx Error Issue
2240 * enhance line driver power
2241 */
Francois Romieu5b538df2008-07-20 16:22:45 +02002242 { 0x1f, 0x0002 },
françois romieudaf9df62009-10-07 12:44:20 +00002243 { 0x06, 0x5561 },
Francois Romieu5b538df2008-07-20 16:22:45 +02002244 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002245 { 0x05, 0x8332 },
françois romieubca03d52011-01-03 15:07:31 +00002246 { 0x06, 0x5561 },
2247
2248 /*
2249 * Can not link to 1Gbps with bad cable
2250 * Decrease SNR threshold form 21.07dB to 19.04dB
2251 */
2252 { 0x1f, 0x0001 },
2253 { 0x17, 0x0cc0 },
françois romieudaf9df62009-10-07 12:44:20 +00002254
2255 { 0x1f, 0x0000 },
françois romieubca03d52011-01-03 15:07:31 +00002256 { 0x0d, 0xf880 }
Francois Romieu5b538df2008-07-20 16:22:45 +02002257 };
françois romieubca03d52011-01-03 15:07:31 +00002258 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu5b538df2008-07-20 16:22:45 +02002259
françois romieu4da19632011-01-03 15:07:55 +00002260 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
Francois Romieu5b538df2008-07-20 16:22:45 +02002261
françois romieubca03d52011-01-03 15:07:31 +00002262 /*
2263 * Rx Error Issue
2264 * Fine Tune Switching regulator parameter
2265 */
françois romieu4da19632011-01-03 15:07:55 +00002266 rtl_writephy(tp, 0x1f, 0x0002);
2267 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2268 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
françois romieudaf9df62009-10-07 12:44:20 +00002269
françois romieudaf9df62009-10-07 12:44:20 +00002270 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002271 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002272 { 0x1f, 0x0002 },
2273 { 0x05, 0x669a },
Francois Romieu5b538df2008-07-20 16:22:45 +02002274 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002275 { 0x05, 0x8330 },
2276 { 0x06, 0x669a },
2277 { 0x1f, 0x0002 }
2278 };
2279 int val;
2280
françois romieu4da19632011-01-03 15:07:55 +00002281 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002282
françois romieu4da19632011-01-03 15:07:55 +00002283 val = rtl_readphy(tp, 0x0d);
françois romieudaf9df62009-10-07 12:44:20 +00002284
2285 if ((val & 0x00ff) != 0x006c) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002286 static const u32 set[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002287 0x0065, 0x0066, 0x0067, 0x0068,
2288 0x0069, 0x006a, 0x006b, 0x006c
2289 };
2290 int i;
2291
françois romieu4da19632011-01-03 15:07:55 +00002292 rtl_writephy(tp, 0x1f, 0x0002);
françois romieudaf9df62009-10-07 12:44:20 +00002293
2294 val &= 0xff00;
2295 for (i = 0; i < ARRAY_SIZE(set); i++)
françois romieu4da19632011-01-03 15:07:55 +00002296 rtl_writephy(tp, 0x0d, val | set[i]);
françois romieudaf9df62009-10-07 12:44:20 +00002297 }
2298 } else {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002299 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002300 { 0x1f, 0x0002 },
2301 { 0x05, 0x6662 },
Francois Romieu5b538df2008-07-20 16:22:45 +02002302 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002303 { 0x05, 0x8330 },
2304 { 0x06, 0x6662 }
Francois Romieu5b538df2008-07-20 16:22:45 +02002305 };
2306
françois romieu4da19632011-01-03 15:07:55 +00002307 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5b538df2008-07-20 16:22:45 +02002308 }
2309
françois romieubca03d52011-01-03 15:07:31 +00002310 /* RSET couple improve */
françois romieu4da19632011-01-03 15:07:55 +00002311 rtl_writephy(tp, 0x1f, 0x0002);
2312 rtl_patchphy(tp, 0x0d, 0x0300);
2313 rtl_patchphy(tp, 0x0f, 0x0010);
françois romieudaf9df62009-10-07 12:44:20 +00002314
françois romieubca03d52011-01-03 15:07:31 +00002315 /* Fine tune PLL performance */
françois romieu4da19632011-01-03 15:07:55 +00002316 rtl_writephy(tp, 0x1f, 0x0002);
2317 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2318 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
françois romieudaf9df62009-10-07 12:44:20 +00002319
françois romieu4da19632011-01-03 15:07:55 +00002320 rtl_writephy(tp, 0x1f, 0x0005);
2321 rtl_writephy(tp, 0x05, 0x001b);
François Romieu953a12c2011-04-24 17:38:48 +02002322
2323 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
françois romieubca03d52011-01-03 15:07:31 +00002324
françois romieu4da19632011-01-03 15:07:55 +00002325 rtl_writephy(tp, 0x1f, 0x0000);
françois romieudaf9df62009-10-07 12:44:20 +00002326}
2327
françois romieubca03d52011-01-03 15:07:31 +00002328static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
françois romieudaf9df62009-10-07 12:44:20 +00002329{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002330 static const struct phy_reg phy_reg_init_0[] = {
françois romieubca03d52011-01-03 15:07:31 +00002331 /* Channel Estimation */
françois romieudaf9df62009-10-07 12:44:20 +00002332 { 0x1f, 0x0001 },
2333 { 0x06, 0x4064 },
2334 { 0x07, 0x2863 },
2335 { 0x08, 0x059c },
2336 { 0x09, 0x26b4 },
2337 { 0x0a, 0x6a19 },
2338 { 0x0b, 0xdcc8 },
2339 { 0x10, 0xf06d },
2340 { 0x14, 0x7f68 },
2341 { 0x18, 0x7fd9 },
2342 { 0x1c, 0xf0ff },
2343 { 0x1d, 0x3d9c },
2344 { 0x1f, 0x0003 },
2345 { 0x12, 0xf49f },
2346 { 0x13, 0x070b },
2347 { 0x1a, 0x05ad },
2348 { 0x14, 0x94c0 },
2349
françois romieubca03d52011-01-03 15:07:31 +00002350 /*
2351 * Tx Error Issue
2352 * enhance line driver power
2353 */
françois romieudaf9df62009-10-07 12:44:20 +00002354 { 0x1f, 0x0002 },
2355 { 0x06, 0x5561 },
2356 { 0x1f, 0x0005 },
2357 { 0x05, 0x8332 },
françois romieubca03d52011-01-03 15:07:31 +00002358 { 0x06, 0x5561 },
2359
2360 /*
2361 * Can not link to 1Gbps with bad cable
2362 * Decrease SNR threshold form 21.07dB to 19.04dB
2363 */
2364 { 0x1f, 0x0001 },
2365 { 0x17, 0x0cc0 },
françois romieudaf9df62009-10-07 12:44:20 +00002366
2367 { 0x1f, 0x0000 },
françois romieubca03d52011-01-03 15:07:31 +00002368 { 0x0d, 0xf880 }
françois romieudaf9df62009-10-07 12:44:20 +00002369 };
françois romieubca03d52011-01-03 15:07:31 +00002370 void __iomem *ioaddr = tp->mmio_addr;
françois romieudaf9df62009-10-07 12:44:20 +00002371
françois romieu4da19632011-01-03 15:07:55 +00002372 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
françois romieudaf9df62009-10-07 12:44:20 +00002373
2374 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002375 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002376 { 0x1f, 0x0002 },
2377 { 0x05, 0x669a },
2378 { 0x1f, 0x0005 },
2379 { 0x05, 0x8330 },
2380 { 0x06, 0x669a },
2381
2382 { 0x1f, 0x0002 }
2383 };
2384 int val;
2385
françois romieu4da19632011-01-03 15:07:55 +00002386 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002387
françois romieu4da19632011-01-03 15:07:55 +00002388 val = rtl_readphy(tp, 0x0d);
françois romieudaf9df62009-10-07 12:44:20 +00002389 if ((val & 0x00ff) != 0x006c) {
Joe Perchesb6bc7652010-12-21 02:16:08 -08002390 static const u32 set[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002391 0x0065, 0x0066, 0x0067, 0x0068,
2392 0x0069, 0x006a, 0x006b, 0x006c
2393 };
2394 int i;
2395
françois romieu4da19632011-01-03 15:07:55 +00002396 rtl_writephy(tp, 0x1f, 0x0002);
françois romieudaf9df62009-10-07 12:44:20 +00002397
2398 val &= 0xff00;
2399 for (i = 0; i < ARRAY_SIZE(set); i++)
françois romieu4da19632011-01-03 15:07:55 +00002400 rtl_writephy(tp, 0x0d, val | set[i]);
françois romieudaf9df62009-10-07 12:44:20 +00002401 }
2402 } else {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002403 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002404 { 0x1f, 0x0002 },
2405 { 0x05, 0x2642 },
2406 { 0x1f, 0x0005 },
2407 { 0x05, 0x8330 },
2408 { 0x06, 0x2642 }
2409 };
2410
françois romieu4da19632011-01-03 15:07:55 +00002411 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002412 }
2413
françois romieubca03d52011-01-03 15:07:31 +00002414 /* Fine tune PLL performance */
françois romieu4da19632011-01-03 15:07:55 +00002415 rtl_writephy(tp, 0x1f, 0x0002);
2416 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2417 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
françois romieudaf9df62009-10-07 12:44:20 +00002418
françois romieubca03d52011-01-03 15:07:31 +00002419 /* Switching regulator Slew rate */
françois romieu4da19632011-01-03 15:07:55 +00002420 rtl_writephy(tp, 0x1f, 0x0002);
2421 rtl_patchphy(tp, 0x0f, 0x0017);
françois romieudaf9df62009-10-07 12:44:20 +00002422
françois romieu4da19632011-01-03 15:07:55 +00002423 rtl_writephy(tp, 0x1f, 0x0005);
2424 rtl_writephy(tp, 0x05, 0x001b);
François Romieu953a12c2011-04-24 17:38:48 +02002425
2426 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
françois romieubca03d52011-01-03 15:07:31 +00002427
françois romieu4da19632011-01-03 15:07:55 +00002428 rtl_writephy(tp, 0x1f, 0x0000);
françois romieudaf9df62009-10-07 12:44:20 +00002429}
2430
françois romieu4da19632011-01-03 15:07:55 +00002431static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
françois romieudaf9df62009-10-07 12:44:20 +00002432{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002433 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002434 { 0x1f, 0x0002 },
2435 { 0x10, 0x0008 },
2436 { 0x0d, 0x006c },
2437
2438 { 0x1f, 0x0000 },
2439 { 0x0d, 0xf880 },
2440
2441 { 0x1f, 0x0001 },
2442 { 0x17, 0x0cc0 },
2443
2444 { 0x1f, 0x0001 },
2445 { 0x0b, 0xa4d8 },
2446 { 0x09, 0x281c },
2447 { 0x07, 0x2883 },
2448 { 0x0a, 0x6b35 },
2449 { 0x1d, 0x3da4 },
2450 { 0x1c, 0xeffd },
2451 { 0x14, 0x7f52 },
2452 { 0x18, 0x7fc6 },
2453 { 0x08, 0x0601 },
2454 { 0x06, 0x4063 },
2455 { 0x10, 0xf074 },
2456 { 0x1f, 0x0003 },
2457 { 0x13, 0x0789 },
2458 { 0x12, 0xf4bd },
2459 { 0x1a, 0x04fd },
2460 { 0x14, 0x84b0 },
2461 { 0x1f, 0x0000 },
2462 { 0x00, 0x9200 },
2463
2464 { 0x1f, 0x0005 },
2465 { 0x01, 0x0340 },
2466 { 0x1f, 0x0001 },
2467 { 0x04, 0x4000 },
2468 { 0x03, 0x1d21 },
2469 { 0x02, 0x0c32 },
2470 { 0x01, 0x0200 },
2471 { 0x00, 0x5554 },
2472 { 0x04, 0x4800 },
2473 { 0x04, 0x4000 },
2474 { 0x04, 0xf000 },
2475 { 0x03, 0xdf01 },
2476 { 0x02, 0xdf20 },
2477 { 0x01, 0x101a },
2478 { 0x00, 0xa0ff },
2479 { 0x04, 0xf800 },
2480 { 0x04, 0xf000 },
2481 { 0x1f, 0x0000 },
2482
2483 { 0x1f, 0x0007 },
2484 { 0x1e, 0x0023 },
2485 { 0x16, 0x0000 },
2486 { 0x1f, 0x0000 }
2487 };
2488
françois romieu4da19632011-01-03 15:07:55 +00002489 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5b538df2008-07-20 16:22:45 +02002490}
2491
françois romieue6de30d2011-01-03 15:08:37 +00002492static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2493{
2494 static const struct phy_reg phy_reg_init[] = {
2495 { 0x1f, 0x0001 },
2496 { 0x17, 0x0cc0 },
2497
2498 { 0x1f, 0x0007 },
2499 { 0x1e, 0x002d },
2500 { 0x18, 0x0040 },
2501 { 0x1f, 0x0000 }
2502 };
2503
2504 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2505 rtl_patchphy(tp, 0x0d, 1 << 5);
2506}
2507
hayeswang01dc7fe2011-03-21 01:50:28 +00002508static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2509{
2510 static const struct phy_reg phy_reg_init[] = {
2511 /* Enable Delay cap */
2512 { 0x1f, 0x0005 },
2513 { 0x05, 0x8b80 },
2514 { 0x06, 0xc896 },
2515 { 0x1f, 0x0000 },
2516
2517 /* Channel estimation fine tune */
2518 { 0x1f, 0x0001 },
2519 { 0x0b, 0x6c20 },
2520 { 0x07, 0x2872 },
2521 { 0x1c, 0xefff },
2522 { 0x1f, 0x0003 },
2523 { 0x14, 0x6420 },
2524 { 0x1f, 0x0000 },
2525
2526 /* Update PFM & 10M TX idle timer */
2527 { 0x1f, 0x0007 },
2528 { 0x1e, 0x002f },
2529 { 0x15, 0x1919 },
2530 { 0x1f, 0x0000 },
2531
2532 { 0x1f, 0x0007 },
2533 { 0x1e, 0x00ac },
2534 { 0x18, 0x0006 },
2535 { 0x1f, 0x0000 }
2536 };
2537
2538 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2539
2540 /* DCO enable for 10M IDLE Power */
2541 rtl_writephy(tp, 0x1f, 0x0007);
2542 rtl_writephy(tp, 0x1e, 0x0023);
2543 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2544 rtl_writephy(tp, 0x1f, 0x0000);
2545
2546 /* For impedance matching */
2547 rtl_writephy(tp, 0x1f, 0x0002);
2548 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2549 rtl_writephy(tp, 0x1F, 0x0000);
2550
2551 /* PHY auto speed down */
2552 rtl_writephy(tp, 0x1f, 0x0007);
2553 rtl_writephy(tp, 0x1e, 0x002d);
2554 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2555 rtl_writephy(tp, 0x1f, 0x0000);
2556 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2557
2558 rtl_writephy(tp, 0x1f, 0x0005);
2559 rtl_writephy(tp, 0x05, 0x8b86);
2560 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2561 rtl_writephy(tp, 0x1f, 0x0000);
2562
2563 rtl_writephy(tp, 0x1f, 0x0005);
2564 rtl_writephy(tp, 0x05, 0x8b85);
2565 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2566 rtl_writephy(tp, 0x1f, 0x0007);
2567 rtl_writephy(tp, 0x1e, 0x0020);
2568 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2569 rtl_writephy(tp, 0x1f, 0x0006);
2570 rtl_writephy(tp, 0x00, 0x5a00);
2571 rtl_writephy(tp, 0x1f, 0x0000);
2572 rtl_writephy(tp, 0x0d, 0x0007);
2573 rtl_writephy(tp, 0x0e, 0x003c);
2574 rtl_writephy(tp, 0x0d, 0x4007);
2575 rtl_writephy(tp, 0x0e, 0x0000);
2576 rtl_writephy(tp, 0x0d, 0x0000);
2577}
2578
2579static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2580{
David S. Miller2bd93d72011-04-26 12:16:46 -07002581 rtl_apply_firmware(tp);
hayeswang01dc7fe2011-03-21 01:50:28 +00002582
2583 rtl8168e_hw_phy_config(tp);
2584}
2585
2586static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2587{
David S. Miller2bd93d72011-04-26 12:16:46 -07002588 rtl_apply_firmware(tp);
hayeswang01dc7fe2011-03-21 01:50:28 +00002589
2590 rtl8168e_hw_phy_config(tp);
2591}
2592
françois romieu4da19632011-01-03 15:07:55 +00002593static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu2857ffb2008-08-02 21:08:49 +02002594{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002595 static const struct phy_reg phy_reg_init[] = {
Francois Romieu2857ffb2008-08-02 21:08:49 +02002596 { 0x1f, 0x0003 },
2597 { 0x08, 0x441d },
2598 { 0x01, 0x9100 },
2599 { 0x1f, 0x0000 }
2600 };
2601
françois romieu4da19632011-01-03 15:07:55 +00002602 rtl_writephy(tp, 0x1f, 0x0000);
2603 rtl_patchphy(tp, 0x11, 1 << 12);
2604 rtl_patchphy(tp, 0x19, 1 << 13);
2605 rtl_patchphy(tp, 0x10, 1 << 15);
Francois Romieu2857ffb2008-08-02 21:08:49 +02002606
françois romieu4da19632011-01-03 15:07:55 +00002607 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu2857ffb2008-08-02 21:08:49 +02002608}
2609
Hayes Wang5a5e4442011-02-22 17:26:21 +08002610static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2611{
2612 static const struct phy_reg phy_reg_init[] = {
2613 { 0x1f, 0x0005 },
2614 { 0x1a, 0x0000 },
2615 { 0x1f, 0x0000 },
2616
2617 { 0x1f, 0x0004 },
2618 { 0x1c, 0x0000 },
2619 { 0x1f, 0x0000 },
2620
2621 { 0x1f, 0x0001 },
2622 { 0x15, 0x7701 },
2623 { 0x1f, 0x0000 }
2624 };
2625
2626 /* Disable ALDPS before ram code */
2627 rtl_writephy(tp, 0x1f, 0x0000);
2628 rtl_writephy(tp, 0x18, 0x0310);
2629 msleep(100);
2630
François Romieu953a12c2011-04-24 17:38:48 +02002631 rtl_apply_firmware(tp);
Hayes Wang5a5e4442011-02-22 17:26:21 +08002632
2633 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2634}
2635
Francois Romieu5615d9f2007-08-17 17:50:46 +02002636static void rtl_hw_phy_config(struct net_device *dev)
2637{
2638 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieu5615d9f2007-08-17 17:50:46 +02002639
2640 rtl8169_print_mac_version(tp);
2641
2642 switch (tp->mac_version) {
2643 case RTL_GIGA_MAC_VER_01:
2644 break;
2645 case RTL_GIGA_MAC_VER_02:
2646 case RTL_GIGA_MAC_VER_03:
françois romieu4da19632011-01-03 15:07:55 +00002647 rtl8169s_hw_phy_config(tp);
Francois Romieu5615d9f2007-08-17 17:50:46 +02002648 break;
2649 case RTL_GIGA_MAC_VER_04:
françois romieu4da19632011-01-03 15:07:55 +00002650 rtl8169sb_hw_phy_config(tp);
Francois Romieu5615d9f2007-08-17 17:50:46 +02002651 break;
françois romieu2e9558562009-08-10 19:44:19 +00002652 case RTL_GIGA_MAC_VER_05:
françois romieu4da19632011-01-03 15:07:55 +00002653 rtl8169scd_hw_phy_config(tp);
françois romieu2e9558562009-08-10 19:44:19 +00002654 break;
françois romieu8c7006a2009-08-10 19:43:29 +00002655 case RTL_GIGA_MAC_VER_06:
françois romieu4da19632011-01-03 15:07:55 +00002656 rtl8169sce_hw_phy_config(tp);
françois romieu8c7006a2009-08-10 19:43:29 +00002657 break;
Francois Romieu2857ffb2008-08-02 21:08:49 +02002658 case RTL_GIGA_MAC_VER_07:
2659 case RTL_GIGA_MAC_VER_08:
2660 case RTL_GIGA_MAC_VER_09:
françois romieu4da19632011-01-03 15:07:55 +00002661 rtl8102e_hw_phy_config(tp);
Francois Romieu2857ffb2008-08-02 21:08:49 +02002662 break;
Francois Romieu236b8082008-05-30 16:11:48 +02002663 case RTL_GIGA_MAC_VER_11:
françois romieu4da19632011-01-03 15:07:55 +00002664 rtl8168bb_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02002665 break;
2666 case RTL_GIGA_MAC_VER_12:
françois romieu4da19632011-01-03 15:07:55 +00002667 rtl8168bef_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02002668 break;
2669 case RTL_GIGA_MAC_VER_17:
françois romieu4da19632011-01-03 15:07:55 +00002670 rtl8168bef_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02002671 break;
Francois Romieu867763c2007-08-17 18:21:58 +02002672 case RTL_GIGA_MAC_VER_18:
françois romieu4da19632011-01-03 15:07:55 +00002673 rtl8168cp_1_hw_phy_config(tp);
Francois Romieu867763c2007-08-17 18:21:58 +02002674 break;
2675 case RTL_GIGA_MAC_VER_19:
françois romieu4da19632011-01-03 15:07:55 +00002676 rtl8168c_1_hw_phy_config(tp);
Francois Romieu867763c2007-08-17 18:21:58 +02002677 break;
Francois Romieu7da97ec2007-10-18 15:20:43 +02002678 case RTL_GIGA_MAC_VER_20:
françois romieu4da19632011-01-03 15:07:55 +00002679 rtl8168c_2_hw_phy_config(tp);
Francois Romieu7da97ec2007-10-18 15:20:43 +02002680 break;
Francois Romieu197ff762008-06-28 13:16:02 +02002681 case RTL_GIGA_MAC_VER_21:
françois romieu4da19632011-01-03 15:07:55 +00002682 rtl8168c_3_hw_phy_config(tp);
Francois Romieu197ff762008-06-28 13:16:02 +02002683 break;
Francois Romieu6fb07052008-06-29 11:54:28 +02002684 case RTL_GIGA_MAC_VER_22:
françois romieu4da19632011-01-03 15:07:55 +00002685 rtl8168c_4_hw_phy_config(tp);
Francois Romieu6fb07052008-06-29 11:54:28 +02002686 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02002687 case RTL_GIGA_MAC_VER_23:
Francois Romieu7f3e3d32008-07-20 18:53:20 +02002688 case RTL_GIGA_MAC_VER_24:
françois romieu4da19632011-01-03 15:07:55 +00002689 rtl8168cp_2_hw_phy_config(tp);
Francois Romieuef3386f2008-06-29 12:24:30 +02002690 break;
Francois Romieu5b538df2008-07-20 16:22:45 +02002691 case RTL_GIGA_MAC_VER_25:
françois romieubca03d52011-01-03 15:07:31 +00002692 rtl8168d_1_hw_phy_config(tp);
françois romieudaf9df62009-10-07 12:44:20 +00002693 break;
2694 case RTL_GIGA_MAC_VER_26:
françois romieubca03d52011-01-03 15:07:31 +00002695 rtl8168d_2_hw_phy_config(tp);
françois romieudaf9df62009-10-07 12:44:20 +00002696 break;
2697 case RTL_GIGA_MAC_VER_27:
françois romieu4da19632011-01-03 15:07:55 +00002698 rtl8168d_3_hw_phy_config(tp);
Francois Romieu5b538df2008-07-20 16:22:45 +02002699 break;
françois romieue6de30d2011-01-03 15:08:37 +00002700 case RTL_GIGA_MAC_VER_28:
2701 rtl8168d_4_hw_phy_config(tp);
2702 break;
Hayes Wang5a5e4442011-02-22 17:26:21 +08002703 case RTL_GIGA_MAC_VER_29:
2704 case RTL_GIGA_MAC_VER_30:
2705 rtl8105e_hw_phy_config(tp);
2706 break;
hayeswang01dc7fe2011-03-21 01:50:28 +00002707 case RTL_GIGA_MAC_VER_32:
2708 rtl8168e_1_hw_phy_config(tp);
2709 break;
2710 case RTL_GIGA_MAC_VER_33:
2711 rtl8168e_2_hw_phy_config(tp);
2712 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02002713
Francois Romieu5615d9f2007-08-17 17:50:46 +02002714 default:
2715 break;
2716 }
2717}
2718
Linus Torvalds1da177e2005-04-16 15:20:36 -07002719static void rtl8169_phy_timer(unsigned long __opaque)
2720{
2721 struct net_device *dev = (struct net_device *)__opaque;
2722 struct rtl8169_private *tp = netdev_priv(dev);
2723 struct timer_list *timer = &tp->timer;
2724 void __iomem *ioaddr = tp->mmio_addr;
2725 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2726
Francois Romieubcf0bf92006-07-26 23:14:13 +02002727 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002728
Francois Romieu64e4bfb2006-08-17 12:43:06 +02002729 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002730 return;
2731
2732 spin_lock_irq(&tp->lock);
2733
françois romieu4da19632011-01-03 15:07:55 +00002734 if (tp->phy_reset_pending(tp)) {
Francois Romieu5b0384f2006-08-16 16:00:01 +02002735 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002736 * A busy loop could burn quite a few cycles on nowadays CPU.
2737 * Let's delay the execution of the timer for a few ticks.
2738 */
2739 timeout = HZ/10;
2740 goto out_mod_timer;
2741 }
2742
2743 if (tp->link_ok(ioaddr))
2744 goto out_unlock;
2745
Joe Perchesbf82c182010-02-09 11:49:50 +00002746 netif_warn(tp, link, dev, "PHY reset until link up\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002747
françois romieu4da19632011-01-03 15:07:55 +00002748 tp->phy_reset_enable(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002749
2750out_mod_timer:
2751 mod_timer(timer, jiffies + timeout);
2752out_unlock:
2753 spin_unlock_irq(&tp->lock);
2754}
2755
2756static inline void rtl8169_delete_timer(struct net_device *dev)
2757{
2758 struct rtl8169_private *tp = netdev_priv(dev);
2759 struct timer_list *timer = &tp->timer;
2760
Francois Romieue179bb72007-08-17 15:05:21 +02002761 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002762 return;
2763
2764 del_timer_sync(timer);
2765}
2766
2767static inline void rtl8169_request_timer(struct net_device *dev)
2768{
2769 struct rtl8169_private *tp = netdev_priv(dev);
2770 struct timer_list *timer = &tp->timer;
2771
Francois Romieue179bb72007-08-17 15:05:21 +02002772 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002773 return;
2774
Francois Romieu2efa53f2007-03-09 00:00:05 +01002775 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002776}
2777
2778#ifdef CONFIG_NET_POLL_CONTROLLER
2779/*
2780 * Polling 'interrupt' - used by things like netconsole to send skbs
2781 * without having to re-enable interrupts. It's not called while
2782 * the interrupt routine is executing.
2783 */
2784static void rtl8169_netpoll(struct net_device *dev)
2785{
2786 struct rtl8169_private *tp = netdev_priv(dev);
2787 struct pci_dev *pdev = tp->pci_dev;
2788
2789 disable_irq(pdev->irq);
David Howells7d12e782006-10-05 14:55:46 +01002790 rtl8169_interrupt(pdev->irq, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002791 enable_irq(pdev->irq);
2792}
2793#endif
2794
2795static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2796 void __iomem *ioaddr)
2797{
2798 iounmap(ioaddr);
2799 pci_release_regions(pdev);
françois romieu87aeec72010-04-26 11:42:06 +00002800 pci_clear_mwi(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002801 pci_disable_device(pdev);
2802 free_netdev(dev);
2803}
2804
Francois Romieubf793292006-11-01 00:53:05 +01002805static void rtl8169_phy_reset(struct net_device *dev,
2806 struct rtl8169_private *tp)
2807{
Francois Romieu07d3f512007-02-21 22:40:46 +01002808 unsigned int i;
Francois Romieubf793292006-11-01 00:53:05 +01002809
françois romieu4da19632011-01-03 15:07:55 +00002810 tp->phy_reset_enable(tp);
Francois Romieubf793292006-11-01 00:53:05 +01002811 for (i = 0; i < 100; i++) {
françois romieu4da19632011-01-03 15:07:55 +00002812 if (!tp->phy_reset_pending(tp))
Francois Romieubf793292006-11-01 00:53:05 +01002813 return;
2814 msleep(1);
2815 }
Joe Perchesbf82c182010-02-09 11:49:50 +00002816 netif_err(tp, link, dev, "PHY reset failed\n");
Francois Romieubf793292006-11-01 00:53:05 +01002817}
2818
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002819static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820{
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002821 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002822
Francois Romieu5615d9f2007-08-17 17:50:46 +02002823 rtl_hw_phy_config(dev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002824
Marcus Sundberg773328942008-07-10 21:28:08 +02002825 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2826 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2827 RTL_W8(0x82, 0x01);
2828 }
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002829
Francois Romieu6dccd162007-02-13 23:38:05 +01002830 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2831
2832 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2833 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002834
Francois Romieubcf0bf92006-07-26 23:14:13 +02002835 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002836 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2837 RTL_W8(0x82, 0x01);
2838 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
françois romieu4da19632011-01-03 15:07:55 +00002839 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002840 }
2841
Francois Romieubf793292006-11-01 00:53:05 +01002842 rtl8169_phy_reset(dev, tp);
2843
Oliver Neukum54405cd2011-01-06 21:55:13 +01002844 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2845 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2846 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
Eric Dumazetdb552b32011-03-19 16:39:11 +01002847 (tp->mii.supports_gmii ?
Oliver Neukum54405cd2011-01-06 21:55:13 +01002848 ADVERTISED_1000baseT_Half |
Eric Dumazetdb552b32011-03-19 16:39:11 +01002849 ADVERTISED_1000baseT_Full : 0));
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002850
Joe Perchesbf82c182010-02-09 11:49:50 +00002851 if (RTL_R8(PHYstatus) & TBI_Enable)
2852 netif_info(tp, link, dev, "TBI auto-negotiating\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002853}
2854
Francois Romieu773d2022007-01-31 23:47:43 +01002855static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2856{
2857 void __iomem *ioaddr = tp->mmio_addr;
2858 u32 high;
2859 u32 low;
2860
2861 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2862 high = addr[4] | (addr[5] << 8);
2863
2864 spin_lock_irq(&tp->lock);
2865
2866 RTL_W8(Cfg9346, Cfg9346_Unlock);
françois romieu908ba2b2010-04-26 11:42:58 +00002867
Francois Romieu773d2022007-01-31 23:47:43 +01002868 RTL_W32(MAC4, high);
françois romieu908ba2b2010-04-26 11:42:58 +00002869 RTL_R32(MAC4);
2870
Francois Romieu78f1cd02010-03-27 19:35:46 -07002871 RTL_W32(MAC0, low);
françois romieu908ba2b2010-04-26 11:42:58 +00002872 RTL_R32(MAC0);
2873
Francois Romieu773d2022007-01-31 23:47:43 +01002874 RTL_W8(Cfg9346, Cfg9346_Lock);
2875
2876 spin_unlock_irq(&tp->lock);
2877}
2878
2879static int rtl_set_mac_address(struct net_device *dev, void *p)
2880{
2881 struct rtl8169_private *tp = netdev_priv(dev);
2882 struct sockaddr *addr = p;
2883
2884 if (!is_valid_ether_addr(addr->sa_data))
2885 return -EADDRNOTAVAIL;
2886
2887 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2888
2889 rtl_rar_set(tp, dev->dev_addr);
2890
2891 return 0;
2892}
2893
Francois Romieu5f787a12006-08-17 13:02:36 +02002894static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2895{
2896 struct rtl8169_private *tp = netdev_priv(dev);
2897 struct mii_ioctl_data *data = if_mii(ifr);
2898
Francois Romieu8b4ab282008-11-19 22:05:25 -08002899 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2900}
Francois Romieu5f787a12006-08-17 13:02:36 +02002901
Francois Romieu8b4ab282008-11-19 22:05:25 -08002902static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2903{
Francois Romieu5f787a12006-08-17 13:02:36 +02002904 switch (cmd) {
2905 case SIOCGMIIPHY:
2906 data->phy_id = 32; /* Internal PHY */
2907 return 0;
2908
2909 case SIOCGMIIREG:
françois romieu4da19632011-01-03 15:07:55 +00002910 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
Francois Romieu5f787a12006-08-17 13:02:36 +02002911 return 0;
2912
2913 case SIOCSMIIREG:
françois romieu4da19632011-01-03 15:07:55 +00002914 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
Francois Romieu5f787a12006-08-17 13:02:36 +02002915 return 0;
2916 }
2917 return -EOPNOTSUPP;
2918}
2919
Francois Romieu8b4ab282008-11-19 22:05:25 -08002920static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2921{
2922 return -EOPNOTSUPP;
2923}
2924
Francois Romieu0e485152007-02-20 00:00:26 +01002925static const struct rtl_cfg_info {
2926 void (*hw_start)(struct net_device *);
2927 unsigned int region;
2928 unsigned int align;
2929 u16 intr_event;
2930 u16 napi_event;
Francois Romieuccdffb92008-07-26 14:26:06 +02002931 unsigned features;
Jean Delvaref21b75e2009-05-26 20:54:48 -07002932 u8 default_ver;
Francois Romieu0e485152007-02-20 00:00:26 +01002933} rtl_cfg_infos [] = {
2934 [RTL_CFG_0] = {
2935 .hw_start = rtl_hw_start_8169,
2936 .region = 1,
Francois Romieue9f63f32007-02-28 23:16:57 +01002937 .align = 0,
Francois Romieu0e485152007-02-20 00:00:26 +01002938 .intr_event = SYSErr | LinkChg | RxOverflow |
2939 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
Francois Romieufbac58f2007-10-04 22:51:38 +02002940 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
Jean Delvaref21b75e2009-05-26 20:54:48 -07002941 .features = RTL_FEATURE_GMII,
2942 .default_ver = RTL_GIGA_MAC_VER_01,
Francois Romieu0e485152007-02-20 00:00:26 +01002943 },
2944 [RTL_CFG_1] = {
2945 .hw_start = rtl_hw_start_8168,
2946 .region = 2,
2947 .align = 8,
françois romieu53f57352010-11-08 13:23:05 +00002948 .intr_event = SYSErr | LinkChg | RxOverflow |
Francois Romieu0e485152007-02-20 00:00:26 +01002949 TxErr | TxOK | RxOK | RxErr,
Francois Romieufbac58f2007-10-04 22:51:38 +02002950 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
Jean Delvaref21b75e2009-05-26 20:54:48 -07002951 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2952 .default_ver = RTL_GIGA_MAC_VER_11,
Francois Romieu0e485152007-02-20 00:00:26 +01002953 },
2954 [RTL_CFG_2] = {
2955 .hw_start = rtl_hw_start_8101,
2956 .region = 2,
2957 .align = 8,
2958 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2959 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
Francois Romieufbac58f2007-10-04 22:51:38 +02002960 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
Jean Delvaref21b75e2009-05-26 20:54:48 -07002961 .features = RTL_FEATURE_MSI,
2962 .default_ver = RTL_GIGA_MAC_VER_13,
Francois Romieu0e485152007-02-20 00:00:26 +01002963 }
2964};
2965
Francois Romieufbac58f2007-10-04 22:51:38 +02002966/* Cfg9346_Unlock assumed. */
2967static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2968 const struct rtl_cfg_info *cfg)
2969{
2970 unsigned msi = 0;
2971 u8 cfg2;
2972
2973 cfg2 = RTL_R8(Config2) & ~MSIEnable;
Francois Romieuccdffb92008-07-26 14:26:06 +02002974 if (cfg->features & RTL_FEATURE_MSI) {
Francois Romieufbac58f2007-10-04 22:51:38 +02002975 if (pci_enable_msi(pdev)) {
2976 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2977 } else {
2978 cfg2 |= MSIEnable;
2979 msi = RTL_FEATURE_MSI;
2980 }
2981 }
2982 RTL_W8(Config2, cfg2);
2983 return msi;
2984}
2985
2986static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2987{
2988 if (tp->features & RTL_FEATURE_MSI) {
2989 pci_disable_msi(pdev);
2990 tp->features &= ~RTL_FEATURE_MSI;
2991 }
2992}
2993
Francois Romieu8b4ab282008-11-19 22:05:25 -08002994static const struct net_device_ops rtl8169_netdev_ops = {
2995 .ndo_open = rtl8169_open,
2996 .ndo_stop = rtl8169_close,
2997 .ndo_get_stats = rtl8169_get_stats,
Stephen Hemminger00829822008-11-20 20:14:53 -08002998 .ndo_start_xmit = rtl8169_start_xmit,
Francois Romieu8b4ab282008-11-19 22:05:25 -08002999 .ndo_tx_timeout = rtl8169_tx_timeout,
3000 .ndo_validate_addr = eth_validate_addr,
3001 .ndo_change_mtu = rtl8169_change_mtu,
Michał Mirosław350fb322011-04-08 06:35:56 +00003002 .ndo_fix_features = rtl8169_fix_features,
3003 .ndo_set_features = rtl8169_set_features,
Francois Romieu8b4ab282008-11-19 22:05:25 -08003004 .ndo_set_mac_address = rtl_set_mac_address,
3005 .ndo_do_ioctl = rtl8169_ioctl,
3006 .ndo_set_multicast_list = rtl_set_rx_mode,
Francois Romieu8b4ab282008-11-19 22:05:25 -08003007#ifdef CONFIG_NET_POLL_CONTROLLER
3008 .ndo_poll_controller = rtl8169_netpoll,
3009#endif
3010
3011};
3012
françois romieuc0e45c12011-01-03 15:08:04 +00003013static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3014{
3015 struct mdio_ops *ops = &tp->mdio_ops;
3016
3017 switch (tp->mac_version) {
3018 case RTL_GIGA_MAC_VER_27:
3019 ops->write = r8168dp_1_mdio_write;
3020 ops->read = r8168dp_1_mdio_read;
3021 break;
françois romieue6de30d2011-01-03 15:08:37 +00003022 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003023 case RTL_GIGA_MAC_VER_31:
françois romieue6de30d2011-01-03 15:08:37 +00003024 ops->write = r8168dp_2_mdio_write;
3025 ops->read = r8168dp_2_mdio_read;
3026 break;
françois romieuc0e45c12011-01-03 15:08:04 +00003027 default:
3028 ops->write = r8169_mdio_write;
3029 ops->read = r8169_mdio_read;
3030 break;
3031 }
3032}
3033
françois romieu065c27c2011-01-03 15:08:12 +00003034static void r810x_phy_power_down(struct rtl8169_private *tp)
3035{
3036 rtl_writephy(tp, 0x1f, 0x0000);
3037 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3038}
3039
3040static void r810x_phy_power_up(struct rtl8169_private *tp)
3041{
3042 rtl_writephy(tp, 0x1f, 0x0000);
3043 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3044}
3045
3046static void r810x_pll_power_down(struct rtl8169_private *tp)
3047{
3048 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3049 rtl_writephy(tp, 0x1f, 0x0000);
3050 rtl_writephy(tp, MII_BMCR, 0x0000);
3051 return;
3052 }
3053
3054 r810x_phy_power_down(tp);
3055}
3056
3057static void r810x_pll_power_up(struct rtl8169_private *tp)
3058{
3059 r810x_phy_power_up(tp);
3060}
3061
3062static void r8168_phy_power_up(struct rtl8169_private *tp)
3063{
3064 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00003065 switch (tp->mac_version) {
3066 case RTL_GIGA_MAC_VER_11:
3067 case RTL_GIGA_MAC_VER_12:
3068 case RTL_GIGA_MAC_VER_17:
3069 case RTL_GIGA_MAC_VER_18:
3070 case RTL_GIGA_MAC_VER_19:
3071 case RTL_GIGA_MAC_VER_20:
3072 case RTL_GIGA_MAC_VER_21:
3073 case RTL_GIGA_MAC_VER_22:
3074 case RTL_GIGA_MAC_VER_23:
3075 case RTL_GIGA_MAC_VER_24:
3076 case RTL_GIGA_MAC_VER_25:
3077 case RTL_GIGA_MAC_VER_26:
3078 case RTL_GIGA_MAC_VER_27:
3079 case RTL_GIGA_MAC_VER_28:
3080 case RTL_GIGA_MAC_VER_31:
3081 rtl_writephy(tp, 0x0e, 0x0000);
3082 break;
3083 default:
3084 break;
3085 }
françois romieu065c27c2011-01-03 15:08:12 +00003086 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3087}
3088
3089static void r8168_phy_power_down(struct rtl8169_private *tp)
3090{
3091 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00003092 switch (tp->mac_version) {
3093 case RTL_GIGA_MAC_VER_32:
3094 case RTL_GIGA_MAC_VER_33:
3095 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3096 break;
3097
3098 case RTL_GIGA_MAC_VER_11:
3099 case RTL_GIGA_MAC_VER_12:
3100 case RTL_GIGA_MAC_VER_17:
3101 case RTL_GIGA_MAC_VER_18:
3102 case RTL_GIGA_MAC_VER_19:
3103 case RTL_GIGA_MAC_VER_20:
3104 case RTL_GIGA_MAC_VER_21:
3105 case RTL_GIGA_MAC_VER_22:
3106 case RTL_GIGA_MAC_VER_23:
3107 case RTL_GIGA_MAC_VER_24:
3108 case RTL_GIGA_MAC_VER_25:
3109 case RTL_GIGA_MAC_VER_26:
3110 case RTL_GIGA_MAC_VER_27:
3111 case RTL_GIGA_MAC_VER_28:
3112 case RTL_GIGA_MAC_VER_31:
3113 rtl_writephy(tp, 0x0e, 0x0200);
3114 default:
3115 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3116 break;
3117 }
françois romieu065c27c2011-01-03 15:08:12 +00003118}
3119
3120static void r8168_pll_power_down(struct rtl8169_private *tp)
3121{
3122 void __iomem *ioaddr = tp->mmio_addr;
3123
Hayes Wang5d2e1952011-02-22 17:26:22 +08003124 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
hayeswang4804b3b2011-03-21 01:50:29 +00003125 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3126 (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3127 r8168dp_check_dash(tp)) {
françois romieu065c27c2011-01-03 15:08:12 +00003128 return;
Hayes Wang5d2e1952011-02-22 17:26:22 +08003129 }
françois romieu065c27c2011-01-03 15:08:12 +00003130
3131 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
3132 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
3133 (RTL_R16(CPlusCmd) & ASF)) {
3134 return;
3135 }
3136
hayeswang01dc7fe2011-03-21 01:50:28 +00003137 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3138 tp->mac_version == RTL_GIGA_MAC_VER_33)
3139 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3140
françois romieu065c27c2011-01-03 15:08:12 +00003141 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3142 rtl_writephy(tp, 0x1f, 0x0000);
3143 rtl_writephy(tp, MII_BMCR, 0x0000);
3144
3145 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3146 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3147 return;
3148 }
3149
3150 r8168_phy_power_down(tp);
3151
3152 switch (tp->mac_version) {
3153 case RTL_GIGA_MAC_VER_25:
3154 case RTL_GIGA_MAC_VER_26:
Hayes Wang5d2e1952011-02-22 17:26:22 +08003155 case RTL_GIGA_MAC_VER_27:
3156 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003157 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003158 case RTL_GIGA_MAC_VER_32:
3159 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003160 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3161 break;
3162 }
3163}
3164
3165static void r8168_pll_power_up(struct rtl8169_private *tp)
3166{
3167 void __iomem *ioaddr = tp->mmio_addr;
3168
Hayes Wang5d2e1952011-02-22 17:26:22 +08003169 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
hayeswang4804b3b2011-03-21 01:50:29 +00003170 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3171 (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3172 r8168dp_check_dash(tp)) {
françois romieu065c27c2011-01-03 15:08:12 +00003173 return;
Hayes Wang5d2e1952011-02-22 17:26:22 +08003174 }
françois romieu065c27c2011-01-03 15:08:12 +00003175
3176 switch (tp->mac_version) {
3177 case RTL_GIGA_MAC_VER_25:
3178 case RTL_GIGA_MAC_VER_26:
Hayes Wang5d2e1952011-02-22 17:26:22 +08003179 case RTL_GIGA_MAC_VER_27:
3180 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003181 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003182 case RTL_GIGA_MAC_VER_32:
3183 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003184 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3185 break;
3186 }
3187
3188 r8168_phy_power_up(tp);
3189}
3190
3191static void rtl_pll_power_op(struct rtl8169_private *tp,
3192 void (*op)(struct rtl8169_private *))
3193{
3194 if (op)
3195 op(tp);
3196}
3197
3198static void rtl_pll_power_down(struct rtl8169_private *tp)
3199{
3200 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3201}
3202
3203static void rtl_pll_power_up(struct rtl8169_private *tp)
3204{
3205 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3206}
3207
3208static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3209{
3210 struct pll_power_ops *ops = &tp->pll_power_ops;
3211
3212 switch (tp->mac_version) {
3213 case RTL_GIGA_MAC_VER_07:
3214 case RTL_GIGA_MAC_VER_08:
3215 case RTL_GIGA_MAC_VER_09:
3216 case RTL_GIGA_MAC_VER_10:
3217 case RTL_GIGA_MAC_VER_16:
Hayes Wang5a5e4442011-02-22 17:26:21 +08003218 case RTL_GIGA_MAC_VER_29:
3219 case RTL_GIGA_MAC_VER_30:
françois romieu065c27c2011-01-03 15:08:12 +00003220 ops->down = r810x_pll_power_down;
3221 ops->up = r810x_pll_power_up;
3222 break;
3223
3224 case RTL_GIGA_MAC_VER_11:
3225 case RTL_GIGA_MAC_VER_12:
3226 case RTL_GIGA_MAC_VER_17:
3227 case RTL_GIGA_MAC_VER_18:
3228 case RTL_GIGA_MAC_VER_19:
3229 case RTL_GIGA_MAC_VER_20:
3230 case RTL_GIGA_MAC_VER_21:
3231 case RTL_GIGA_MAC_VER_22:
3232 case RTL_GIGA_MAC_VER_23:
3233 case RTL_GIGA_MAC_VER_24:
3234 case RTL_GIGA_MAC_VER_25:
3235 case RTL_GIGA_MAC_VER_26:
3236 case RTL_GIGA_MAC_VER_27:
françois romieue6de30d2011-01-03 15:08:37 +00003237 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003238 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003239 case RTL_GIGA_MAC_VER_32:
3240 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003241 ops->down = r8168_pll_power_down;
3242 ops->up = r8168_pll_power_up;
3243 break;
3244
3245 default:
3246 ops->down = NULL;
3247 ops->up = NULL;
3248 break;
3249 }
3250}
3251
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003252static int __devinit
3253rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3254{
Francois Romieu0e485152007-02-20 00:00:26 +01003255 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3256 const unsigned int region = cfg->region;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003257 struct rtl8169_private *tp;
Francois Romieuccdffb92008-07-26 14:26:06 +02003258 struct mii_if_info *mii;
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003259 struct net_device *dev;
3260 void __iomem *ioaddr;
Francois Romieu2b7b4312011-04-18 22:53:24 -07003261 int chipset, i;
Francois Romieu07d3f512007-02-21 22:40:46 +01003262 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003263
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003264 if (netif_msg_drv(&debug)) {
3265 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3266 MODULENAME, RTL8169_VERSION);
3267 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003268
Linus Torvalds1da177e2005-04-16 15:20:36 -07003269 dev = alloc_etherdev(sizeof (*tp));
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003270 if (!dev) {
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003271 if (netif_msg_drv(&debug))
Jeff Garzik9b91cf92006-06-27 11:39:50 -04003272 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003273 rc = -ENOMEM;
3274 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003275 }
3276
Linus Torvalds1da177e2005-04-16 15:20:36 -07003277 SET_NETDEV_DEV(dev, &pdev->dev);
Francois Romieu8b4ab282008-11-19 22:05:25 -08003278 dev->netdev_ops = &rtl8169_netdev_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003279 tp = netdev_priv(dev);
David Howellsc4028952006-11-22 14:57:56 +00003280 tp->dev = dev;
Ivan Vecera21e197f2008-04-17 22:48:41 +02003281 tp->pci_dev = pdev;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003282 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003283
Francois Romieuccdffb92008-07-26 14:26:06 +02003284 mii = &tp->mii;
3285 mii->dev = dev;
3286 mii->mdio_read = rtl_mdio_read;
3287 mii->mdio_write = rtl_mdio_write;
3288 mii->phy_id_mask = 0x1f;
3289 mii->reg_num_mask = 0x1f;
3290 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3291
Stanislaw Gruszkaba04c7c2011-02-22 02:00:11 +00003292 /* disable ASPM completely as that cause random device stop working
3293 * problems as well as full system hangs for some PCIe devices users */
3294 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3295 PCIE_LINK_STATE_CLKPM);
3296
Linus Torvalds1da177e2005-04-16 15:20:36 -07003297 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3298 rc = pci_enable_device(pdev);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003299 if (rc < 0) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003300 netif_err(tp, probe, dev, "enable failure\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003301 goto err_out_free_dev_1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003302 }
3303
françois romieu87aeec72010-04-26 11:42:06 +00003304 if (pci_set_mwi(pdev) < 0)
3305 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003306
Linus Torvalds1da177e2005-04-16 15:20:36 -07003307 /* make sure PCI base addr 1 is MMIO */
Francois Romieubcf0bf92006-07-26 23:14:13 +02003308 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003309 netif_err(tp, probe, dev,
3310 "region #%d not an MMIO resource, aborting\n",
3311 region);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003312 rc = -ENODEV;
françois romieu87aeec72010-04-26 11:42:06 +00003313 goto err_out_mwi_2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003314 }
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003315
Linus Torvalds1da177e2005-04-16 15:20:36 -07003316 /* check for weird/broken PCI region reporting */
Francois Romieubcf0bf92006-07-26 23:14:13 +02003317 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003318 netif_err(tp, probe, dev,
3319 "Invalid PCI region size(s), aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003320 rc = -ENODEV;
françois romieu87aeec72010-04-26 11:42:06 +00003321 goto err_out_mwi_2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003322 }
3323
3324 rc = pci_request_regions(pdev, MODULENAME);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003325 if (rc < 0) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003326 netif_err(tp, probe, dev, "could not request regions\n");
françois romieu87aeec72010-04-26 11:42:06 +00003327 goto err_out_mwi_2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003328 }
3329
Hayes Wangd24e9aa2011-02-22 17:26:19 +08003330 tp->cp_cmd = RxChkSum;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003331
3332 if ((sizeof(dma_addr_t) > 4) &&
David S. Miller4300e8c2010-03-26 10:23:30 -07003333 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003334 tp->cp_cmd |= PCIDAC;
3335 dev->features |= NETIF_F_HIGHDMA;
3336 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07003337 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003338 if (rc < 0) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003339 netif_err(tp, probe, dev, "DMA configuration failed\n");
françois romieu87aeec72010-04-26 11:42:06 +00003340 goto err_out_free_res_3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003341 }
3342 }
3343
Linus Torvalds1da177e2005-04-16 15:20:36 -07003344 /* ioremap MMIO region */
Francois Romieubcf0bf92006-07-26 23:14:13 +02003345 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003346 if (!ioaddr) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003347 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003348 rc = -EIO;
françois romieu87aeec72010-04-26 11:42:06 +00003349 goto err_out_free_res_3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003350 }
3351
David S. Miller4300e8c2010-03-26 10:23:30 -07003352 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3353 if (!tp->pcie_cap)
3354 netif_info(tp, probe, dev, "no PCI Express capability\n");
3355
Karsten Wiesed78ad8c2009-04-02 01:06:01 -07003356 RTL_W16(IntrMask, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003357
3358 /* Soft reset the chip. */
3359 RTL_W8(ChipCmd, CmdReset);
3360
3361 /* Check that the chip has finished the reset. */
Francois Romieu07d3f512007-02-21 22:40:46 +01003362 for (i = 0; i < 100; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003363 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3364 break;
Francois Romieub518fa82006-08-16 15:23:13 +02003365 msleep_interruptible(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003366 }
3367
Karsten Wiesed78ad8c2009-04-02 01:06:01 -07003368 RTL_W16(IntrStatus, 0xffff);
3369
françois romieuca52efd2009-07-24 12:34:19 +00003370 pci_set_master(pdev);
3371
Linus Torvalds1da177e2005-04-16 15:20:36 -07003372 /* Identify chip attached to board */
3373 rtl8169_get_mac_version(tp, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003374
Francois Romieu7a8fc772011-03-01 17:18:33 +01003375 /*
3376 * Pretend we are using VLANs; This bypasses a nasty bug where
3377 * Interrupts stop flowing on high load on 8110SCd controllers.
3378 */
3379 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3380 tp->cp_cmd |= RxVlan;
3381
françois romieuc0e45c12011-01-03 15:08:04 +00003382 rtl_init_mdio_ops(tp);
françois romieu065c27c2011-01-03 15:08:12 +00003383 rtl_init_pll_power_ops(tp);
françois romieuc0e45c12011-01-03 15:08:04 +00003384
Jean Delvaref21b75e2009-05-26 20:54:48 -07003385 /* Use appropriate default if unknown */
3386 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003387 netif_notice(tp, probe, dev,
3388 "unknown MAC, using family default\n");
Jean Delvaref21b75e2009-05-26 20:54:48 -07003389 tp->mac_version = cfg->default_ver;
3390 }
3391
Linus Torvalds1da177e2005-04-16 15:20:36 -07003392 rtl8169_print_mac_version(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003393
Roel Kluincee60c32008-04-17 22:35:54 +02003394 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003395 if (tp->mac_version == rtl_chip_info[i].mac_version)
3396 break;
3397 }
Roel Kluincee60c32008-04-17 22:35:54 +02003398 if (i == ARRAY_SIZE(rtl_chip_info)) {
Jean Delvaref21b75e2009-05-26 20:54:48 -07003399 dev_err(&pdev->dev,
3400 "driver bug, MAC version not found in rtl_chip_info\n");
françois romieu87aeec72010-04-26 11:42:06 +00003401 goto err_out_msi_4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003402 }
Francois Romieu2b7b4312011-04-18 22:53:24 -07003403 chipset = i;
3404 tp->txd_version = rtl_chip_info[chipset].txd_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003405
Francois Romieu5d06a992006-02-23 00:47:58 +01003406 RTL_W8(Cfg9346, Cfg9346_Unlock);
3407 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3408 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
Bruno Prémont20037fa2008-10-08 17:05:03 -07003409 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3410 tp->features |= RTL_FEATURE_WOL;
3411 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3412 tp->features |= RTL_FEATURE_WOL;
Francois Romieufbac58f2007-10-04 22:51:38 +02003413 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
Francois Romieu5d06a992006-02-23 00:47:58 +01003414 RTL_W8(Cfg9346, Cfg9346_Lock);
3415
Francois Romieu66ec5d42007-11-06 22:56:10 +01003416 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3417 (RTL_R8(PHYstatus) & TBI_Enable)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003418 tp->set_speed = rtl8169_set_speed_tbi;
3419 tp->get_settings = rtl8169_gset_tbi;
3420 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3421 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3422 tp->link_ok = rtl8169_tbi_link_ok;
Francois Romieu8b4ab282008-11-19 22:05:25 -08003423 tp->do_ioctl = rtl_tbi_ioctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003424
Francois Romieu64e4bfb2006-08-17 12:43:06 +02003425 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003426 } else {
3427 tp->set_speed = rtl8169_set_speed_xmii;
3428 tp->get_settings = rtl8169_gset_xmii;
3429 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3430 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3431 tp->link_ok = rtl8169_xmii_link_ok;
Francois Romieu8b4ab282008-11-19 22:05:25 -08003432 tp->do_ioctl = rtl_xmii_ioctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003433 }
3434
Francois Romieudf58ef52008-10-09 14:35:58 -07003435 spin_lock_init(&tp->lock);
3436
Petr Vandrovec738e1e62008-10-12 20:58:29 -07003437 tp->mmio_addr = ioaddr;
3438
Ivan Vecera7bf6bf42008-09-23 22:46:29 +00003439 /* Get MAC address */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003440 for (i = 0; i < MAC_ADDR_LEN; i++)
3441 dev->dev_addr[i] = RTL_R8(MAC0 + i);
John W. Linville6d6525b2005-09-12 10:48:57 -04003442 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003443
Linus Torvalds1da177e2005-04-16 15:20:36 -07003444 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003445 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3446 dev->irq = pdev->irq;
3447 dev->base_addr = (unsigned long) ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003448
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003449 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003450
Michał Mirosław350fb322011-04-08 06:35:56 +00003451 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3452 * properly for all devices */
3453 dev->features |= NETIF_F_RXCSUM |
3454 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3455
3456 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3457 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3458 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3459 NETIF_F_HIGHDMA;
3460
3461 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3462 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3463 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003464
3465 tp->intr_mask = 0xffff;
Francois Romieu0e485152007-02-20 00:00:26 +01003466 tp->hw_start = cfg->hw_start;
3467 tp->intr_event = cfg->intr_event;
3468 tp->napi_event = cfg->napi_event;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003469
Francois Romieu2efa53f2007-03-09 00:00:05 +01003470 init_timer(&tp->timer);
3471 tp->timer.data = (unsigned long) dev;
3472 tp->timer.function = rtl8169_phy_timer;
3473
François Romieu953a12c2011-04-24 17:38:48 +02003474 tp->fw = RTL_FIRMWARE_UNKNOWN;
3475
Linus Torvalds1da177e2005-04-16 15:20:36 -07003476 rc = register_netdev(dev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003477 if (rc < 0)
françois romieu87aeec72010-04-26 11:42:06 +00003478 goto err_out_msi_4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003479
3480 pci_set_drvdata(pdev, dev);
3481
Joe Perchesbf82c182010-02-09 11:49:50 +00003482 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
Francois Romieu2b7b4312011-04-18 22:53:24 -07003483 rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
Joe Perchesbf82c182010-02-09 11:49:50 +00003484 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003485
françois romieue6de30d2011-01-03 15:08:37 +00003486 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
hayeswang4804b3b2011-03-21 01:50:29 +00003487 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3488 (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
françois romieub646d902011-01-03 15:08:21 +00003489 rtl8168_driver_start(tp);
françois romieue6de30d2011-01-03 15:08:37 +00003490 }
françois romieub646d902011-01-03 15:08:21 +00003491
Bruno Prémont8b76ab32008-10-08 17:06:25 -07003492 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003493
Alan Sternf3ec4f82010-06-08 15:23:51 -04003494 if (pci_dev_run_wake(pdev))
3495 pm_runtime_put_noidle(&pdev->dev);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003496
Ivan Vecera0d672e92011-02-15 02:08:39 +00003497 netif_carrier_off(dev);
3498
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003499out:
3500 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003501
françois romieu87aeec72010-04-26 11:42:06 +00003502err_out_msi_4:
Francois Romieufbac58f2007-10-04 22:51:38 +02003503 rtl_disable_msi(pdev, tp);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003504 iounmap(ioaddr);
françois romieu87aeec72010-04-26 11:42:06 +00003505err_out_free_res_3:
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003506 pci_release_regions(pdev);
françois romieu87aeec72010-04-26 11:42:06 +00003507err_out_mwi_2:
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003508 pci_clear_mwi(pdev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003509 pci_disable_device(pdev);
3510err_out_free_dev_1:
3511 free_netdev(dev);
3512 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003513}
3514
Francois Romieu07d3f512007-02-21 22:40:46 +01003515static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003516{
3517 struct net_device *dev = pci_get_drvdata(pdev);
3518 struct rtl8169_private *tp = netdev_priv(dev);
3519
françois romieue6de30d2011-01-03 15:08:37 +00003520 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
hayeswang4804b3b2011-03-21 01:50:29 +00003521 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3522 (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
françois romieub646d902011-01-03 15:08:21 +00003523 rtl8168_driver_stop(tp);
françois romieue6de30d2011-01-03 15:08:37 +00003524 }
françois romieub646d902011-01-03 15:08:21 +00003525
Tejun Heo23f333a2010-12-12 16:45:14 +01003526 cancel_delayed_work_sync(&tp->task);
Francois Romieueb2a0212007-02-15 23:37:21 +01003527
Linus Torvalds1da177e2005-04-16 15:20:36 -07003528 unregister_netdev(dev);
Ivan Veceracc098dc2009-11-29 23:12:52 -08003529
François Romieu953a12c2011-04-24 17:38:48 +02003530 rtl_release_firmware(tp);
3531
Alan Sternf3ec4f82010-06-08 15:23:51 -04003532 if (pci_dev_run_wake(pdev))
3533 pm_runtime_get_noresume(&pdev->dev);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003534
Ivan Veceracc098dc2009-11-29 23:12:52 -08003535 /* restore original MAC address */
3536 rtl_rar_set(tp, dev->perm_addr);
3537
Francois Romieufbac58f2007-10-04 22:51:38 +02003538 rtl_disable_msi(pdev, tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003539 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3540 pci_set_drvdata(pdev, NULL);
3541}
3542
François Romieu953a12c2011-04-24 17:38:48 +02003543static void rtl_request_firmware(struct rtl8169_private *tp)
3544{
3545 int i;
3546
3547 /* Return early if the firmware is already loaded / cached. */
3548 if (!IS_ERR(tp->fw))
3549 goto out;
3550
3551 for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
3552 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
3553
3554 if (info->mac_version == tp->mac_version) {
3555 const char *name = info->fw_name;
3556 int rc;
3557
3558 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3559 if (rc < 0) {
3560 netif_warn(tp, ifup, tp->dev, "unable to load "
3561 "firmware patch %s (%d)\n", name, rc);
3562 goto out_disable_request_firmware;
3563 }
3564 goto out;
3565 }
3566 }
3567
3568out_disable_request_firmware:
3569 tp->fw = NULL;
3570out:
3571 return;
3572}
3573
Linus Torvalds1da177e2005-04-16 15:20:36 -07003574static int rtl8169_open(struct net_device *dev)
3575{
3576 struct rtl8169_private *tp = netdev_priv(dev);
françois romieueee3a962011-01-08 02:17:26 +00003577 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003578 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu99f252b2007-04-02 22:59:59 +02003579 int retval = -ENOMEM;
3580
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003581 pm_runtime_get_sync(&pdev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003582
Neil Hormanc0cd8842010-03-29 13:16:02 -07003583 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003584 * Rx and Tx desscriptors needs 256 bytes alignment.
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003585 * dma_alloc_coherent provides more.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003586 */
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003587 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3588 &tp->TxPhyAddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003589 if (!tp->TxDescArray)
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003590 goto err_pm_runtime_put;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003591
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003592 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3593 &tp->RxPhyAddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003594 if (!tp->RxDescArray)
Francois Romieu99f252b2007-04-02 22:59:59 +02003595 goto err_free_tx_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003596
3597 retval = rtl8169_init_ring(dev);
3598 if (retval < 0)
Francois Romieu99f252b2007-04-02 22:59:59 +02003599 goto err_free_rx_1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003600
David Howellsc4028952006-11-22 14:57:56 +00003601 INIT_DELAYED_WORK(&tp->task, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003602
Francois Romieu99f252b2007-04-02 22:59:59 +02003603 smp_mb();
3604
François Romieu953a12c2011-04-24 17:38:48 +02003605 rtl_request_firmware(tp);
3606
Francois Romieufbac58f2007-10-04 22:51:38 +02003607 retval = request_irq(dev->irq, rtl8169_interrupt,
3608 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
Francois Romieu99f252b2007-04-02 22:59:59 +02003609 dev->name, dev);
3610 if (retval < 0)
François Romieu953a12c2011-04-24 17:38:48 +02003611 goto err_release_fw_2;
Francois Romieu99f252b2007-04-02 22:59:59 +02003612
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003613 napi_enable(&tp->napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003614
françois romieueee3a962011-01-08 02:17:26 +00003615 rtl8169_init_phy(dev, tp);
3616
Michał Mirosław350fb322011-04-08 06:35:56 +00003617 rtl8169_set_features(dev, dev->features);
françois romieueee3a962011-01-08 02:17:26 +00003618
françois romieu065c27c2011-01-03 15:08:12 +00003619 rtl_pll_power_up(tp);
3620
Francois Romieu07ce4062007-02-23 23:36:39 +01003621 rtl_hw_start(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003622
3623 rtl8169_request_timer(dev);
3624
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003625 tp->saved_wolopts = 0;
3626 pm_runtime_put_noidle(&pdev->dev);
3627
françois romieueee3a962011-01-08 02:17:26 +00003628 rtl8169_check_link_status(dev, tp, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003629out:
3630 return retval;
3631
François Romieu953a12c2011-04-24 17:38:48 +02003632err_release_fw_2:
3633 rtl_release_firmware(tp);
Francois Romieu99f252b2007-04-02 22:59:59 +02003634 rtl8169_rx_clear(tp);
3635err_free_rx_1:
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003636 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3637 tp->RxPhyAddr);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003638 tp->RxDescArray = NULL;
Francois Romieu99f252b2007-04-02 22:59:59 +02003639err_free_tx_0:
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003640 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3641 tp->TxPhyAddr);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003642 tp->TxDescArray = NULL;
3643err_pm_runtime_put:
3644 pm_runtime_put_noidle(&pdev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003645 goto out;
3646}
3647
françois romieue6de30d2011-01-03 15:08:37 +00003648static void rtl8169_hw_reset(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003649{
françois romieue6de30d2011-01-03 15:08:37 +00003650 void __iomem *ioaddr = tp->mmio_addr;
3651
Linus Torvalds1da177e2005-04-16 15:20:36 -07003652 /* Disable interrupts */
3653 rtl8169_irq_mask_and_ack(ioaddr);
3654
Hayes Wang5d2e1952011-02-22 17:26:22 +08003655 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
hayeswang4804b3b2011-03-21 01:50:29 +00003656 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3657 tp->mac_version == RTL_GIGA_MAC_VER_31) {
françois romieue6de30d2011-01-03 15:08:37 +00003658 while (RTL_R8(TxPoll) & NPQ)
3659 udelay(20);
3660
3661 }
3662
Linus Torvalds1da177e2005-04-16 15:20:36 -07003663 /* Reset the chipset */
3664 RTL_W8(ChipCmd, CmdReset);
3665
3666 /* PCI commit */
3667 RTL_R8(ChipCmd);
3668}
3669
Francois Romieu7f796d832007-06-11 23:04:41 +02003670static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
Francois Romieu9cb427b2006-11-02 00:10:16 +01003671{
3672 void __iomem *ioaddr = tp->mmio_addr;
3673 u32 cfg = rtl8169_rx_config;
3674
Francois Romieu2b7b4312011-04-18 22:53:24 -07003675 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
Francois Romieu9cb427b2006-11-02 00:10:16 +01003676 RTL_W32(RxConfig, cfg);
3677
3678 /* Set DMA burst size and Interframe Gap Time */
3679 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3680 (InterFrameGap << TxInterFrameGapShift));
3681}
3682
Francois Romieu07ce4062007-02-23 23:36:39 +01003683static void rtl_hw_start(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003684{
3685 struct rtl8169_private *tp = netdev_priv(dev);
3686 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu07d3f512007-02-21 22:40:46 +01003687 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003688
3689 /* Soft reset the chip. */
3690 RTL_W8(ChipCmd, CmdReset);
3691
3692 /* Check that the chip has finished the reset. */
Francois Romieu07d3f512007-02-21 22:40:46 +01003693 for (i = 0; i < 100; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003694 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3695 break;
Francois Romieub518fa82006-08-16 15:23:13 +02003696 msleep_interruptible(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003697 }
3698
Francois Romieu07ce4062007-02-23 23:36:39 +01003699 tp->hw_start(dev);
3700
Francois Romieu07ce4062007-02-23 23:36:39 +01003701 netif_start_queue(dev);
3702}
3703
3704
Francois Romieu7f796d832007-06-11 23:04:41 +02003705static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3706 void __iomem *ioaddr)
3707{
3708 /*
3709 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3710 * register to be written before TxDescAddrLow to work.
3711 * Switching from MMIO to I/O access fixes the issue as well.
3712 */
3713 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07003714 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
Francois Romieu7f796d832007-06-11 23:04:41 +02003715 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07003716 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
Francois Romieu7f796d832007-06-11 23:04:41 +02003717}
3718
3719static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3720{
3721 u16 cmd;
3722
3723 cmd = RTL_R16(CPlusCmd);
3724 RTL_W16(CPlusCmd, cmd);
3725 return cmd;
3726}
3727
Eric Dumazetfdd7b4c2009-06-09 04:01:02 -07003728static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
Francois Romieu7f796d832007-06-11 23:04:41 +02003729{
3730 /* Low hurts. Let's disable the filtering. */
Raimonds Cicans207d6e82009-10-26 10:52:37 +00003731 RTL_W16(RxMaxSize, rx_buf_sz + 1);
Francois Romieu7f796d832007-06-11 23:04:41 +02003732}
3733
Francois Romieu6dccd162007-02-13 23:38:05 +01003734static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3735{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003736 static const struct {
Francois Romieu6dccd162007-02-13 23:38:05 +01003737 u32 mac_version;
3738 u32 clk;
3739 u32 val;
3740 } cfg2_info [] = {
3741 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3742 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3743 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3744 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3745 }, *p = cfg2_info;
3746 unsigned int i;
3747 u32 clk;
3748
3749 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
Francois Romieucadf1852008-01-03 23:38:38 +01003750 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
Francois Romieu6dccd162007-02-13 23:38:05 +01003751 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3752 RTL_W32(0x7c, p->val);
3753 break;
3754 }
3755 }
3756}
3757
Francois Romieu07ce4062007-02-23 23:36:39 +01003758static void rtl_hw_start_8169(struct net_device *dev)
3759{
3760 struct rtl8169_private *tp = netdev_priv(dev);
3761 void __iomem *ioaddr = tp->mmio_addr;
3762 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu07ce4062007-02-23 23:36:39 +01003763
Francois Romieu9cb427b2006-11-02 00:10:16 +01003764 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3765 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3766 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3767 }
3768
Linus Torvalds1da177e2005-04-16 15:20:36 -07003769 RTL_W8(Cfg9346, Cfg9346_Unlock);
Francois Romieu9cb427b2006-11-02 00:10:16 +01003770 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3771 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3772 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3773 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3774 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3775
françois romieuf0298f82011-01-03 15:07:42 +00003776 RTL_W8(EarlyTxThres, NoEarlyTx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003777
Eric Dumazet6f0333b2010-10-11 11:17:47 +00003778 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003779
Francois Romieuc946b302007-10-04 00:42:50 +02003780 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3781 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3782 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3783 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3784 rtl_set_rx_tx_config_registers(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003785
Francois Romieu7f796d832007-06-11 23:04:41 +02003786 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
Francois Romieubcf0bf92006-07-26 23:14:13 +02003787
3788 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3789 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
Joe Perches06fa7352007-10-18 21:15:00 +02003790 dprintk("Set MAC Reg C+CR Offset 0xE0. "
Linus Torvalds1da177e2005-04-16 15:20:36 -07003791 "Bit-3 and bit-14 MUST be 1\n");
Francois Romieubcf0bf92006-07-26 23:14:13 +02003792 tp->cp_cmd |= (1 << 14);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003793 }
3794
Francois Romieubcf0bf92006-07-26 23:14:13 +02003795 RTL_W16(CPlusCmd, tp->cp_cmd);
3796
Francois Romieu6dccd162007-02-13 23:38:05 +01003797 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3798
Linus Torvalds1da177e2005-04-16 15:20:36 -07003799 /*
3800 * Undocumented corner. Supposedly:
3801 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3802 */
3803 RTL_W16(IntrMitigate, 0x0000);
3804
Francois Romieu7f796d832007-06-11 23:04:41 +02003805 rtl_set_rx_tx_desc_registers(tp, ioaddr);
Francois Romieu9cb427b2006-11-02 00:10:16 +01003806
Francois Romieuc946b302007-10-04 00:42:50 +02003807 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3808 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3809 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3810 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3811 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3812 rtl_set_rx_tx_config_registers(tp);
3813 }
3814
Linus Torvalds1da177e2005-04-16 15:20:36 -07003815 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieub518fa82006-08-16 15:23:13 +02003816
3817 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3818 RTL_R8(IntrMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003819
3820 RTL_W32(RxMissed, 0);
3821
Francois Romieu07ce4062007-02-23 23:36:39 +01003822 rtl_set_rx_mode(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003823
3824 /* no early-rx interrupts */
3825 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
Francois Romieu6dccd162007-02-13 23:38:05 +01003826
3827 /* Enable all known interrupts by setting the interrupt mask. */
Francois Romieu0e485152007-02-20 00:00:26 +01003828 RTL_W16(IntrMask, tp->intr_event);
Francois Romieu07ce4062007-02-23 23:36:39 +01003829}
Linus Torvalds1da177e2005-04-16 15:20:36 -07003830
Francois Romieu9c14cea2008-07-05 00:21:15 +02003831static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
Francois Romieu458a9f62008-08-02 15:50:02 +02003832{
Francois Romieu9c14cea2008-07-05 00:21:15 +02003833 struct net_device *dev = pci_get_drvdata(pdev);
3834 struct rtl8169_private *tp = netdev_priv(dev);
3835 int cap = tp->pcie_cap;
Francois Romieu458a9f62008-08-02 15:50:02 +02003836
Francois Romieu9c14cea2008-07-05 00:21:15 +02003837 if (cap) {
3838 u16 ctl;
3839
3840 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3841 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3842 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3843 }
Francois Romieu458a9f62008-08-02 15:50:02 +02003844}
3845
françois romieu650e8d52011-01-03 15:08:29 +00003846static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
Francois Romieudacf8152008-08-02 20:44:13 +02003847{
3848 u32 csi;
3849
3850 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
françois romieu650e8d52011-01-03 15:08:29 +00003851 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3852}
3853
françois romieue6de30d2011-01-03 15:08:37 +00003854static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3855{
3856 rtl_csi_access_enable(ioaddr, 0x17000000);
3857}
3858
françois romieu650e8d52011-01-03 15:08:29 +00003859static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3860{
3861 rtl_csi_access_enable(ioaddr, 0x27000000);
Francois Romieudacf8152008-08-02 20:44:13 +02003862}
3863
3864struct ephy_info {
3865 unsigned int offset;
3866 u16 mask;
3867 u16 bits;
3868};
3869
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003870static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
Francois Romieudacf8152008-08-02 20:44:13 +02003871{
3872 u16 w;
3873
3874 while (len-- > 0) {
3875 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3876 rtl_ephy_write(ioaddr, e->offset, w);
3877 e++;
3878 }
3879}
3880
Francois Romieub726e492008-06-28 12:22:59 +02003881static void rtl_disable_clock_request(struct pci_dev *pdev)
3882{
3883 struct net_device *dev = pci_get_drvdata(pdev);
3884 struct rtl8169_private *tp = netdev_priv(dev);
3885 int cap = tp->pcie_cap;
3886
3887 if (cap) {
3888 u16 ctl;
3889
3890 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3891 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3892 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3893 }
3894}
3895
françois romieue6de30d2011-01-03 15:08:37 +00003896static void rtl_enable_clock_request(struct pci_dev *pdev)
3897{
3898 struct net_device *dev = pci_get_drvdata(pdev);
3899 struct rtl8169_private *tp = netdev_priv(dev);
3900 int cap = tp->pcie_cap;
3901
3902 if (cap) {
3903 u16 ctl;
3904
3905 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3906 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3907 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3908 }
3909}
3910
Francois Romieub726e492008-06-28 12:22:59 +02003911#define R8168_CPCMD_QUIRK_MASK (\
3912 EnableBist | \
3913 Mac_dbgo_oe | \
3914 Force_half_dup | \
3915 Force_rxflow_en | \
3916 Force_txflow_en | \
3917 Cxpl_dbg_sel | \
3918 ASF | \
3919 PktCntrDisable | \
3920 Mac_dbgo_sel)
3921
Francois Romieu219a1e92008-06-28 11:58:39 +02003922static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3923{
Francois Romieub726e492008-06-28 12:22:59 +02003924 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3925
3926 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3927
Francois Romieu2e68ae42008-06-28 12:00:55 +02003928 rtl_tx_performance_tweak(pdev,
3929 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
Francois Romieu219a1e92008-06-28 11:58:39 +02003930}
3931
3932static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3933{
3934 rtl_hw_start_8168bb(ioaddr, pdev);
Francois Romieub726e492008-06-28 12:22:59 +02003935
françois romieuf0298f82011-01-03 15:07:42 +00003936 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieub726e492008-06-28 12:22:59 +02003937
3938 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
Francois Romieu219a1e92008-06-28 11:58:39 +02003939}
3940
3941static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3942{
Francois Romieub726e492008-06-28 12:22:59 +02003943 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3944
3945 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3946
Francois Romieu219a1e92008-06-28 11:58:39 +02003947 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
Francois Romieub726e492008-06-28 12:22:59 +02003948
3949 rtl_disable_clock_request(pdev);
3950
3951 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
Francois Romieu219a1e92008-06-28 11:58:39 +02003952}
3953
Francois Romieuef3386f2008-06-29 12:24:30 +02003954static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
Francois Romieu219a1e92008-06-28 11:58:39 +02003955{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003956 static const struct ephy_info e_info_8168cp[] = {
Francois Romieub726e492008-06-28 12:22:59 +02003957 { 0x01, 0, 0x0001 },
3958 { 0x02, 0x0800, 0x1000 },
3959 { 0x03, 0, 0x0042 },
3960 { 0x06, 0x0080, 0x0000 },
3961 { 0x07, 0, 0x2000 }
3962 };
3963
françois romieu650e8d52011-01-03 15:08:29 +00003964 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02003965
3966 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3967
Francois Romieu219a1e92008-06-28 11:58:39 +02003968 __rtl_hw_start_8168cp(ioaddr, pdev);
3969}
3970
Francois Romieuef3386f2008-06-29 12:24:30 +02003971static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3972{
françois romieu650e8d52011-01-03 15:08:29 +00003973 rtl_csi_access_enable_2(ioaddr);
Francois Romieuef3386f2008-06-29 12:24:30 +02003974
3975 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3976
3977 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3978
3979 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3980}
3981
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003982static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3983{
françois romieu650e8d52011-01-03 15:08:29 +00003984 rtl_csi_access_enable_2(ioaddr);
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003985
3986 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3987
3988 /* Magic. */
3989 RTL_W8(DBG_REG, 0x20);
3990
françois romieuf0298f82011-01-03 15:07:42 +00003991 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003992
3993 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3994
3995 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3996}
3997
Francois Romieu219a1e92008-06-28 11:58:39 +02003998static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3999{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004000 static const struct ephy_info e_info_8168c_1[] = {
Francois Romieub726e492008-06-28 12:22:59 +02004001 { 0x02, 0x0800, 0x1000 },
4002 { 0x03, 0, 0x0002 },
4003 { 0x06, 0x0080, 0x0000 }
4004 };
4005
françois romieu650e8d52011-01-03 15:08:29 +00004006 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02004007
4008 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4009
4010 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4011
Francois Romieu219a1e92008-06-28 11:58:39 +02004012 __rtl_hw_start_8168cp(ioaddr, pdev);
4013}
4014
4015static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4016{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004017 static const struct ephy_info e_info_8168c_2[] = {
Francois Romieub726e492008-06-28 12:22:59 +02004018 { 0x01, 0, 0x0001 },
4019 { 0x03, 0x0400, 0x0220 }
4020 };
4021
françois romieu650e8d52011-01-03 15:08:29 +00004022 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02004023
4024 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4025
Francois Romieu219a1e92008-06-28 11:58:39 +02004026 __rtl_hw_start_8168cp(ioaddr, pdev);
4027}
4028
Francois Romieu197ff762008-06-28 13:16:02 +02004029static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4030{
4031 rtl_hw_start_8168c_2(ioaddr, pdev);
4032}
4033
Francois Romieu6fb07052008-06-29 11:54:28 +02004034static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4035{
françois romieu650e8d52011-01-03 15:08:29 +00004036 rtl_csi_access_enable_2(ioaddr);
Francois Romieu6fb07052008-06-29 11:54:28 +02004037
4038 __rtl_hw_start_8168cp(ioaddr, pdev);
4039}
4040
Francois Romieu5b538df2008-07-20 16:22:45 +02004041static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4042{
françois romieu650e8d52011-01-03 15:08:29 +00004043 rtl_csi_access_enable_2(ioaddr);
Francois Romieu5b538df2008-07-20 16:22:45 +02004044
4045 rtl_disable_clock_request(pdev);
4046
françois romieuf0298f82011-01-03 15:07:42 +00004047 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu5b538df2008-07-20 16:22:45 +02004048
4049 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4050
4051 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4052}
4053
hayeswang4804b3b2011-03-21 01:50:29 +00004054static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4055{
4056 rtl_csi_access_enable_1(ioaddr);
4057
4058 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4059
4060 RTL_W8(MaxTxPacketSize, TxPacketMax);
4061
4062 rtl_disable_clock_request(pdev);
4063}
4064
françois romieue6de30d2011-01-03 15:08:37 +00004065static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4066{
4067 static const struct ephy_info e_info_8168d_4[] = {
4068 { 0x0b, ~0, 0x48 },
4069 { 0x19, 0x20, 0x50 },
4070 { 0x0c, ~0, 0x20 }
4071 };
4072 int i;
4073
4074 rtl_csi_access_enable_1(ioaddr);
4075
4076 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4077
4078 RTL_W8(MaxTxPacketSize, TxPacketMax);
4079
4080 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4081 const struct ephy_info *e = e_info_8168d_4 + i;
4082 u16 w;
4083
4084 w = rtl_ephy_read(ioaddr, e->offset);
4085 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4086 }
4087
4088 rtl_enable_clock_request(pdev);
4089}
4090
hayeswang01dc7fe2011-03-21 01:50:28 +00004091static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4092{
4093 static const struct ephy_info e_info_8168e[] = {
4094 { 0x00, 0x0200, 0x0100 },
4095 { 0x00, 0x0000, 0x0004 },
4096 { 0x06, 0x0002, 0x0001 },
4097 { 0x06, 0x0000, 0x0030 },
4098 { 0x07, 0x0000, 0x2000 },
4099 { 0x00, 0x0000, 0x0020 },
4100 { 0x03, 0x5800, 0x2000 },
4101 { 0x03, 0x0000, 0x0001 },
4102 { 0x01, 0x0800, 0x1000 },
4103 { 0x07, 0x0000, 0x4000 },
4104 { 0x1e, 0x0000, 0x2000 },
4105 { 0x19, 0xffff, 0xfe6c },
4106 { 0x0a, 0x0000, 0x0040 }
4107 };
4108
4109 rtl_csi_access_enable_2(ioaddr);
4110
4111 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4112
4113 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4114
4115 RTL_W8(MaxTxPacketSize, TxPacketMax);
4116
4117 rtl_disable_clock_request(pdev);
4118
4119 /* Reset tx FIFO pointer */
4120 RTL_W32(MISC, RTL_R32(MISC) | txpla_rst);
4121 RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst);
4122
4123 RTL_W8(Config5, RTL_R8(Config5) & ~spi_en);
4124}
4125
Francois Romieu07ce4062007-02-23 23:36:39 +01004126static void rtl_hw_start_8168(struct net_device *dev)
4127{
Francois Romieu2dd99532007-06-11 23:22:52 +02004128 struct rtl8169_private *tp = netdev_priv(dev);
4129 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu0e485152007-02-20 00:00:26 +01004130 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu2dd99532007-06-11 23:22:52 +02004131
4132 RTL_W8(Cfg9346, Cfg9346_Unlock);
4133
françois romieuf0298f82011-01-03 15:07:42 +00004134 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu2dd99532007-06-11 23:22:52 +02004135
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004136 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Francois Romieu2dd99532007-06-11 23:22:52 +02004137
Francois Romieu0e485152007-02-20 00:00:26 +01004138 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
Francois Romieu2dd99532007-06-11 23:22:52 +02004139
4140 RTL_W16(CPlusCmd, tp->cp_cmd);
4141
Francois Romieu0e485152007-02-20 00:00:26 +01004142 RTL_W16(IntrMitigate, 0x5151);
4143
4144 /* Work around for RxFIFO overflow. */
Ivan Vecerab5ba6d12011-01-27 12:24:11 +01004145 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4146 tp->mac_version == RTL_GIGA_MAC_VER_22) {
Francois Romieu0e485152007-02-20 00:00:26 +01004147 tp->intr_event |= RxFIFOOver | PCSTimeout;
4148 tp->intr_event &= ~RxOverflow;
4149 }
Francois Romieu2dd99532007-06-11 23:22:52 +02004150
4151 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4152
Francois Romieub8363902008-06-01 12:31:57 +02004153 rtl_set_rx_mode(dev);
4154
4155 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4156 (InterFrameGap << TxInterFrameGapShift));
Francois Romieu2dd99532007-06-11 23:22:52 +02004157
4158 RTL_R8(IntrMask);
4159
Francois Romieu219a1e92008-06-28 11:58:39 +02004160 switch (tp->mac_version) {
4161 case RTL_GIGA_MAC_VER_11:
4162 rtl_hw_start_8168bb(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004163 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004164
4165 case RTL_GIGA_MAC_VER_12:
4166 case RTL_GIGA_MAC_VER_17:
4167 rtl_hw_start_8168bef(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004168 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004169
4170 case RTL_GIGA_MAC_VER_18:
Francois Romieuef3386f2008-06-29 12:24:30 +02004171 rtl_hw_start_8168cp_1(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004172 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004173
4174 case RTL_GIGA_MAC_VER_19:
4175 rtl_hw_start_8168c_1(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004176 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004177
4178 case RTL_GIGA_MAC_VER_20:
4179 rtl_hw_start_8168c_2(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004180 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004181
Francois Romieu197ff762008-06-28 13:16:02 +02004182 case RTL_GIGA_MAC_VER_21:
4183 rtl_hw_start_8168c_3(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004184 break;
Francois Romieu197ff762008-06-28 13:16:02 +02004185
Francois Romieu6fb07052008-06-29 11:54:28 +02004186 case RTL_GIGA_MAC_VER_22:
4187 rtl_hw_start_8168c_4(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004188 break;
Francois Romieu6fb07052008-06-29 11:54:28 +02004189
Francois Romieuef3386f2008-06-29 12:24:30 +02004190 case RTL_GIGA_MAC_VER_23:
4191 rtl_hw_start_8168cp_2(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004192 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02004193
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004194 case RTL_GIGA_MAC_VER_24:
4195 rtl_hw_start_8168cp_3(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004196 break;
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004197
Francois Romieu5b538df2008-07-20 16:22:45 +02004198 case RTL_GIGA_MAC_VER_25:
françois romieudaf9df62009-10-07 12:44:20 +00004199 case RTL_GIGA_MAC_VER_26:
4200 case RTL_GIGA_MAC_VER_27:
Francois Romieu5b538df2008-07-20 16:22:45 +02004201 rtl_hw_start_8168d(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004202 break;
Francois Romieu5b538df2008-07-20 16:22:45 +02004203
françois romieue6de30d2011-01-03 15:08:37 +00004204 case RTL_GIGA_MAC_VER_28:
4205 rtl_hw_start_8168d_4(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004206 break;
4207 case RTL_GIGA_MAC_VER_31:
4208 rtl_hw_start_8168dp(ioaddr, pdev);
4209 break;
4210
hayeswang01dc7fe2011-03-21 01:50:28 +00004211 case RTL_GIGA_MAC_VER_32:
4212 case RTL_GIGA_MAC_VER_33:
4213 rtl_hw_start_8168e(ioaddr, pdev);
4214 break;
françois romieue6de30d2011-01-03 15:08:37 +00004215
Francois Romieu219a1e92008-06-28 11:58:39 +02004216 default:
4217 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4218 dev->name, tp->mac_version);
hayeswang4804b3b2011-03-21 01:50:29 +00004219 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004220 }
Francois Romieu2dd99532007-06-11 23:22:52 +02004221
Francois Romieu0e485152007-02-20 00:00:26 +01004222 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4223
Francois Romieub8363902008-06-01 12:31:57 +02004224 RTL_W8(Cfg9346, Cfg9346_Lock);
4225
Francois Romieu2dd99532007-06-11 23:22:52 +02004226 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
Francois Romieu6dccd162007-02-13 23:38:05 +01004227
Francois Romieu0e485152007-02-20 00:00:26 +01004228 RTL_W16(IntrMask, tp->intr_event);
Francois Romieu07ce4062007-02-23 23:36:39 +01004229}
Linus Torvalds1da177e2005-04-16 15:20:36 -07004230
Francois Romieu2857ffb2008-08-02 21:08:49 +02004231#define R810X_CPCMD_QUIRK_MASK (\
4232 EnableBist | \
4233 Mac_dbgo_oe | \
4234 Force_half_dup | \
françois romieu5edcc532009-08-10 19:41:52 +00004235 Force_rxflow_en | \
Francois Romieu2857ffb2008-08-02 21:08:49 +02004236 Force_txflow_en | \
4237 Cxpl_dbg_sel | \
4238 ASF | \
4239 PktCntrDisable | \
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004240 Mac_dbgo_sel)
Francois Romieu2857ffb2008-08-02 21:08:49 +02004241
4242static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4243{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004244 static const struct ephy_info e_info_8102e_1[] = {
Francois Romieu2857ffb2008-08-02 21:08:49 +02004245 { 0x01, 0, 0x6e65 },
4246 { 0x02, 0, 0x091f },
4247 { 0x03, 0, 0xc2f9 },
4248 { 0x06, 0, 0xafb5 },
4249 { 0x07, 0, 0x0e00 },
4250 { 0x19, 0, 0xec80 },
4251 { 0x01, 0, 0x2e65 },
4252 { 0x01, 0, 0x6e65 }
4253 };
4254 u8 cfg1;
4255
françois romieu650e8d52011-01-03 15:08:29 +00004256 rtl_csi_access_enable_2(ioaddr);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004257
4258 RTL_W8(DBG_REG, FIX_NAK_1);
4259
4260 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4261
4262 RTL_W8(Config1,
4263 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4264 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4265
4266 cfg1 = RTL_R8(Config1);
4267 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4268 RTL_W8(Config1, cfg1 & ~LEDS0);
4269
Francois Romieu2857ffb2008-08-02 21:08:49 +02004270 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4271}
4272
4273static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4274{
françois romieu650e8d52011-01-03 15:08:29 +00004275 rtl_csi_access_enable_2(ioaddr);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004276
4277 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4278
4279 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4280 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004281}
4282
4283static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4284{
4285 rtl_hw_start_8102e_2(ioaddr, pdev);
4286
4287 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4288}
4289
Hayes Wang5a5e4442011-02-22 17:26:21 +08004290static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4291{
4292 static const struct ephy_info e_info_8105e_1[] = {
4293 { 0x07, 0, 0x4000 },
4294 { 0x19, 0, 0x0200 },
4295 { 0x19, 0, 0x0020 },
4296 { 0x1e, 0, 0x2000 },
4297 { 0x03, 0, 0x0001 },
4298 { 0x19, 0, 0x0100 },
4299 { 0x19, 0, 0x0004 },
4300 { 0x0a, 0, 0x0020 }
4301 };
4302
4303 /* Force LAN exit from ASPM if Rx/Tx are not idel */
4304 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4305
4306 /* disable Early Tally Counter */
4307 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4308
4309 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4310 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4311
4312 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4313}
4314
4315static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4316{
4317 rtl_hw_start_8105e_1(ioaddr, pdev);
4318 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4319}
4320
Francois Romieu07ce4062007-02-23 23:36:39 +01004321static void rtl_hw_start_8101(struct net_device *dev)
4322{
Francois Romieucdf1a602007-06-11 23:29:50 +02004323 struct rtl8169_private *tp = netdev_priv(dev);
4324 void __iomem *ioaddr = tp->mmio_addr;
4325 struct pci_dev *pdev = tp->pci_dev;
4326
Francois Romieue3cf0cc2007-08-17 14:55:46 +02004327 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4328 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
Francois Romieu9c14cea2008-07-05 00:21:15 +02004329 int cap = tp->pcie_cap;
4330
4331 if (cap) {
4332 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4333 PCI_EXP_DEVCTL_NOSNOOP_EN);
4334 }
Francois Romieucdf1a602007-06-11 23:29:50 +02004335 }
4336
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004337 RTL_W8(Cfg9346, Cfg9346_Unlock);
4338
Francois Romieu2857ffb2008-08-02 21:08:49 +02004339 switch (tp->mac_version) {
4340 case RTL_GIGA_MAC_VER_07:
4341 rtl_hw_start_8102e_1(ioaddr, pdev);
4342 break;
4343
4344 case RTL_GIGA_MAC_VER_08:
4345 rtl_hw_start_8102e_3(ioaddr, pdev);
4346 break;
4347
4348 case RTL_GIGA_MAC_VER_09:
4349 rtl_hw_start_8102e_2(ioaddr, pdev);
4350 break;
Hayes Wang5a5e4442011-02-22 17:26:21 +08004351
4352 case RTL_GIGA_MAC_VER_29:
4353 rtl_hw_start_8105e_1(ioaddr, pdev);
4354 break;
4355 case RTL_GIGA_MAC_VER_30:
4356 rtl_hw_start_8105e_2(ioaddr, pdev);
4357 break;
Francois Romieucdf1a602007-06-11 23:29:50 +02004358 }
4359
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004360 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieucdf1a602007-06-11 23:29:50 +02004361
françois romieuf0298f82011-01-03 15:07:42 +00004362 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieucdf1a602007-06-11 23:29:50 +02004363
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004364 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Francois Romieucdf1a602007-06-11 23:29:50 +02004365
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004366 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
Francois Romieucdf1a602007-06-11 23:29:50 +02004367 RTL_W16(CPlusCmd, tp->cp_cmd);
4368
4369 RTL_W16(IntrMitigate, 0x0000);
4370
4371 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4372
4373 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4374 rtl_set_rx_tx_config_registers(tp);
4375
Francois Romieucdf1a602007-06-11 23:29:50 +02004376 RTL_R8(IntrMask);
4377
Francois Romieucdf1a602007-06-11 23:29:50 +02004378 rtl_set_rx_mode(dev);
4379
4380 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
Francois Romieu6dccd162007-02-13 23:38:05 +01004381
Francois Romieu0e485152007-02-20 00:00:26 +01004382 RTL_W16(IntrMask, tp->intr_event);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004383}
4384
4385static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4386{
Linus Torvalds1da177e2005-04-16 15:20:36 -07004387 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4388 return -EINVAL;
4389
4390 dev->mtu = new_mtu;
Michał Mirosław350fb322011-04-08 06:35:56 +00004391 netdev_update_features(dev);
4392
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00004393 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004394}
4395
4396static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4397{
Al Viro95e09182007-12-22 18:55:39 +00004398 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004399 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4400}
4401
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004402static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4403 void **data_buff, struct RxDesc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004404{
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004405 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
Stanislaw Gruszka231aee62010-10-20 22:25:38 +00004406 DMA_FROM_DEVICE);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004407
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004408 kfree(*data_buff);
4409 *data_buff = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004410 rtl8169_make_unusable_by_asic(desc);
4411}
4412
4413static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4414{
4415 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4416
4417 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4418}
4419
4420static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4421 u32 rx_buf_sz)
4422{
4423 desc->addr = cpu_to_le64(mapping);
4424 wmb();
4425 rtl8169_mark_to_asic(desc, rx_buf_sz);
4426}
4427
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004428static inline void *rtl8169_align(void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004429{
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004430 return (void *)ALIGN((long)data, 16);
4431}
4432
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004433static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4434 struct RxDesc *desc)
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004435{
4436 void *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004437 dma_addr_t mapping;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004438 struct device *d = &tp->pci_dev->dev;
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004439 struct net_device *dev = tp->dev;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004440 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004441
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004442 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4443 if (!data)
4444 return NULL;
Francois Romieue9f63f32007-02-28 23:16:57 +01004445
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004446 if (rtl8169_align(data) != data) {
4447 kfree(data);
4448 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4449 if (!data)
4450 return NULL;
4451 }
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004452
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004453 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
Stanislaw Gruszka231aee62010-10-20 22:25:38 +00004454 DMA_FROM_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004455 if (unlikely(dma_mapping_error(d, mapping))) {
4456 if (net_ratelimit())
4457 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004458 goto err_out;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004459 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004460
4461 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004462 return data;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004463
4464err_out:
4465 kfree(data);
4466 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004467}
4468
4469static void rtl8169_rx_clear(struct rtl8169_private *tp)
4470{
Francois Romieu07d3f512007-02-21 22:40:46 +01004471 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004472
4473 for (i = 0; i < NUM_RX_DESC; i++) {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004474 if (tp->Rx_databuff[i]) {
4475 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004476 tp->RxDescArray + i);
4477 }
4478 }
4479}
4480
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004481static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004482{
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004483 desc->opts1 |= cpu_to_le32(RingEnd);
4484}
Francois Romieu5b0384f2006-08-16 16:00:01 +02004485
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004486static int rtl8169_rx_fill(struct rtl8169_private *tp)
4487{
4488 unsigned int i;
4489
4490 for (i = 0; i < NUM_RX_DESC; i++) {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004491 void *data;
Francois Romieu4ae47c22007-06-16 23:28:45 +02004492
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004493 if (tp->Rx_databuff[i])
Linus Torvalds1da177e2005-04-16 15:20:36 -07004494 continue;
Francois Romieubcf0bf92006-07-26 23:14:13 +02004495
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004496 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004497 if (!data) {
4498 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004499 goto err_out;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004500 }
4501 tp->Rx_databuff[i] = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004502 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004503
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004504 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4505 return 0;
4506
4507err_out:
4508 rtl8169_rx_clear(tp);
4509 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004510}
4511
4512static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4513{
4514 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4515}
4516
4517static int rtl8169_init_ring(struct net_device *dev)
4518{
4519 struct rtl8169_private *tp = netdev_priv(dev);
4520
4521 rtl8169_init_ring_indexes(tp);
4522
4523 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004524 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004525
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004526 return rtl8169_rx_fill(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004527}
4528
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004529static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004530 struct TxDesc *desc)
4531{
4532 unsigned int len = tx_skb->len;
4533
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004534 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4535
Linus Torvalds1da177e2005-04-16 15:20:36 -07004536 desc->opts1 = 0x00;
4537 desc->opts2 = 0x00;
4538 desc->addr = 0x00;
4539 tx_skb->len = 0;
4540}
4541
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004542static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4543 unsigned int n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004544{
4545 unsigned int i;
4546
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004547 for (i = 0; i < n; i++) {
4548 unsigned int entry = (start + i) % NUM_TX_DESC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004549 struct ring_info *tx_skb = tp->tx_skb + entry;
4550 unsigned int len = tx_skb->len;
4551
4552 if (len) {
4553 struct sk_buff *skb = tx_skb->skb;
4554
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004555 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004556 tp->TxDescArray + entry);
4557 if (skb) {
Stanislaw Gruszkacac4b222010-10-20 22:25:40 +00004558 tp->dev->stats.tx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004559 dev_kfree_skb(skb);
4560 tx_skb->skb = NULL;
4561 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004562 }
4563 }
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004564}
4565
4566static void rtl8169_tx_clear(struct rtl8169_private *tp)
4567{
4568 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004569 tp->cur_tx = tp->dirty_tx = 0;
4570}
4571
David Howellsc4028952006-11-22 14:57:56 +00004572static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004573{
4574 struct rtl8169_private *tp = netdev_priv(dev);
4575
David Howellsc4028952006-11-22 14:57:56 +00004576 PREPARE_DELAYED_WORK(&tp->task, task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004577 schedule_delayed_work(&tp->task, 4);
4578}
4579
4580static void rtl8169_wait_for_quiescence(struct net_device *dev)
4581{
4582 struct rtl8169_private *tp = netdev_priv(dev);
4583 void __iomem *ioaddr = tp->mmio_addr;
4584
4585 synchronize_irq(dev->irq);
4586
4587 /* Wait for any pending NAPI task to complete */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004588 napi_disable(&tp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004589
4590 rtl8169_irq_mask_and_ack(ioaddr);
4591
David S. Millerd1d08d12008-01-07 20:53:33 -08004592 tp->intr_mask = 0xffff;
4593 RTL_W16(IntrMask, tp->intr_event);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004594 napi_enable(&tp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004595}
4596
David Howellsc4028952006-11-22 14:57:56 +00004597static void rtl8169_reinit_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004598{
David Howellsc4028952006-11-22 14:57:56 +00004599 struct rtl8169_private *tp =
4600 container_of(work, struct rtl8169_private, task.work);
4601 struct net_device *dev = tp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004602 int ret;
4603
Francois Romieueb2a0212007-02-15 23:37:21 +01004604 rtnl_lock();
4605
4606 if (!netif_running(dev))
4607 goto out_unlock;
4608
4609 rtl8169_wait_for_quiescence(dev);
4610 rtl8169_close(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004611
4612 ret = rtl8169_open(dev);
4613 if (unlikely(ret < 0)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00004614 if (net_ratelimit())
4615 netif_err(tp, drv, dev,
4616 "reinit failure (status = %d). Rescheduling\n",
4617 ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004618 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4619 }
Francois Romieueb2a0212007-02-15 23:37:21 +01004620
4621out_unlock:
4622 rtnl_unlock();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004623}
4624
David Howellsc4028952006-11-22 14:57:56 +00004625static void rtl8169_reset_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004626{
David Howellsc4028952006-11-22 14:57:56 +00004627 struct rtl8169_private *tp =
4628 container_of(work, struct rtl8169_private, task.work);
4629 struct net_device *dev = tp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004630
Francois Romieueb2a0212007-02-15 23:37:21 +01004631 rtnl_lock();
4632
Linus Torvalds1da177e2005-04-16 15:20:36 -07004633 if (!netif_running(dev))
Francois Romieueb2a0212007-02-15 23:37:21 +01004634 goto out_unlock;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004635
4636 rtl8169_wait_for_quiescence(dev);
4637
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004638 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004639 rtl8169_tx_clear(tp);
4640
4641 if (tp->dirty_rx == tp->cur_rx) {
4642 rtl8169_init_ring_indexes(tp);
Francois Romieu07ce4062007-02-23 23:36:39 +01004643 rtl_hw_start(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004644 netif_wake_queue(dev);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004645 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004646 } else {
Joe Perchesbf82c182010-02-09 11:49:50 +00004647 if (net_ratelimit())
4648 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07004649 rtl8169_schedule_work(dev, rtl8169_reset_task);
4650 }
Francois Romieueb2a0212007-02-15 23:37:21 +01004651
4652out_unlock:
4653 rtnl_unlock();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004654}
4655
4656static void rtl8169_tx_timeout(struct net_device *dev)
4657{
4658 struct rtl8169_private *tp = netdev_priv(dev);
4659
françois romieue6de30d2011-01-03 15:08:37 +00004660 rtl8169_hw_reset(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004661
4662 /* Let's wait a bit while any (async) irq lands on */
4663 rtl8169_schedule_work(dev, rtl8169_reset_task);
4664}
4665
4666static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
Francois Romieu2b7b4312011-04-18 22:53:24 -07004667 u32 *opts)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004668{
4669 struct skb_shared_info *info = skb_shinfo(skb);
4670 unsigned int cur_frag, entry;
Jeff Garzika6343af2007-07-17 05:39:58 -04004671 struct TxDesc * uninitialized_var(txd);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004672 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004673
4674 entry = tp->cur_tx;
4675 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4676 skb_frag_t *frag = info->frags + cur_frag;
4677 dma_addr_t mapping;
4678 u32 status, len;
4679 void *addr;
4680
4681 entry = (entry + 1) % NUM_TX_DESC;
4682
4683 txd = tp->TxDescArray + entry;
4684 len = frag->size;
4685 addr = ((void *) page_address(frag->page)) + frag->page_offset;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004686 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004687 if (unlikely(dma_mapping_error(d, mapping))) {
4688 if (net_ratelimit())
4689 netif_err(tp, drv, tp->dev,
4690 "Failed to map TX fragments DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004691 goto err_out;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004692 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004693
4694 /* anti gcc 2.95.3 bugware (sic) */
Francois Romieu2b7b4312011-04-18 22:53:24 -07004695 status = opts[0] | len |
4696 (RingEnd * !((entry + 1) % NUM_TX_DESC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004697
4698 txd->opts1 = cpu_to_le32(status);
Francois Romieu2b7b4312011-04-18 22:53:24 -07004699 txd->opts2 = cpu_to_le32(opts[1]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004700 txd->addr = cpu_to_le64(mapping);
4701
4702 tp->tx_skb[entry].len = len;
4703 }
4704
4705 if (cur_frag) {
4706 tp->tx_skb[entry].skb = skb;
4707 txd->opts1 |= cpu_to_le32(LastFrag);
4708 }
4709
4710 return cur_frag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004711
4712err_out:
4713 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4714 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004715}
4716
Francois Romieu2b7b4312011-04-18 22:53:24 -07004717static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4718 struct sk_buff *skb, u32 *opts)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004719{
Francois Romieu2b7b4312011-04-18 22:53:24 -07004720 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
Michał Mirosław350fb322011-04-08 06:35:56 +00004721 u32 mss = skb_shinfo(skb)->gso_size;
Francois Romieu2b7b4312011-04-18 22:53:24 -07004722 int offset = info->opts_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004723
Francois Romieu2b7b4312011-04-18 22:53:24 -07004724 if (mss) {
4725 opts[0] |= TD_LSO;
4726 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4727 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07004728 const struct iphdr *ip = ip_hdr(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004729
4730 if (ip->protocol == IPPROTO_TCP)
Francois Romieu2b7b4312011-04-18 22:53:24 -07004731 opts[offset] |= info->checksum.tcp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004732 else if (ip->protocol == IPPROTO_UDP)
Francois Romieu2b7b4312011-04-18 22:53:24 -07004733 opts[offset] |= info->checksum.udp;
4734 else
4735 WARN_ON_ONCE(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004736 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004737}
4738
Stephen Hemminger613573252009-08-31 19:50:58 +00004739static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4740 struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004741{
4742 struct rtl8169_private *tp = netdev_priv(dev);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004743 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004744 struct TxDesc *txd = tp->TxDescArray + entry;
4745 void __iomem *ioaddr = tp->mmio_addr;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004746 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004747 dma_addr_t mapping;
4748 u32 status, len;
Francois Romieu2b7b4312011-04-18 22:53:24 -07004749 u32 opts[2];
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004750 int frags;
Francois Romieu5b0384f2006-08-16 16:00:01 +02004751
Linus Torvalds1da177e2005-04-16 15:20:36 -07004752 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00004753 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004754 goto err_stop_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004755 }
4756
4757 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004758 goto err_stop_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004759
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004760 len = skb_headlen(skb);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004761 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004762 if (unlikely(dma_mapping_error(d, mapping))) {
4763 if (net_ratelimit())
4764 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004765 goto err_dma_0;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004766 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004767
4768 tp->tx_skb[entry].len = len;
4769 txd->addr = cpu_to_le64(mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004770
Francois Romieu2b7b4312011-04-18 22:53:24 -07004771 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4772 opts[0] = DescOwn;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004773
Francois Romieu2b7b4312011-04-18 22:53:24 -07004774 rtl8169_tso_csum(tp, skb, opts);
4775
4776 frags = rtl8169_xmit_frags(tp, skb, opts);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004777 if (frags < 0)
4778 goto err_dma_1;
4779 else if (frags)
Francois Romieu2b7b4312011-04-18 22:53:24 -07004780 opts[0] |= FirstFrag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004781 else {
Francois Romieu2b7b4312011-04-18 22:53:24 -07004782 opts[0] |= FirstFrag | LastFrag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004783 tp->tx_skb[entry].skb = skb;
4784 }
4785
Francois Romieu2b7b4312011-04-18 22:53:24 -07004786 txd->opts2 = cpu_to_le32(opts[1]);
4787
Linus Torvalds1da177e2005-04-16 15:20:36 -07004788 wmb();
4789
4790 /* anti gcc 2.95.3 bugware (sic) */
Francois Romieu2b7b4312011-04-18 22:53:24 -07004791 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004792 txd->opts1 = cpu_to_le32(status);
4793
Linus Torvalds1da177e2005-04-16 15:20:36 -07004794 tp->cur_tx += frags + 1;
4795
David Dillow4c020a92010-03-03 16:33:10 +00004796 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004797
Francois Romieu275391a2007-02-23 23:50:28 +01004798 RTL_W8(TxPoll, NPQ); /* set polling bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004799
4800 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4801 netif_stop_queue(dev);
4802 smp_rmb();
4803 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4804 netif_wake_queue(dev);
4805 }
4806
Stephen Hemminger613573252009-08-31 19:50:58 +00004807 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004808
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004809err_dma_1:
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004810 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004811err_dma_0:
4812 dev_kfree_skb(skb);
4813 dev->stats.tx_dropped++;
4814 return NETDEV_TX_OK;
4815
4816err_stop_0:
Linus Torvalds1da177e2005-04-16 15:20:36 -07004817 netif_stop_queue(dev);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004818 dev->stats.tx_dropped++;
Stephen Hemminger613573252009-08-31 19:50:58 +00004819 return NETDEV_TX_BUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004820}
4821
4822static void rtl8169_pcierr_interrupt(struct net_device *dev)
4823{
4824 struct rtl8169_private *tp = netdev_priv(dev);
4825 struct pci_dev *pdev = tp->pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004826 u16 pci_status, pci_cmd;
4827
4828 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4829 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4830
Joe Perchesbf82c182010-02-09 11:49:50 +00004831 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4832 pci_cmd, pci_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004833
4834 /*
4835 * The recovery sequence below admits a very elaborated explanation:
4836 * - it seems to work;
Francois Romieud03902b2006-11-23 00:00:42 +01004837 * - I did not see what else could be done;
4838 * - it makes iop3xx happy.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004839 *
4840 * Feel free to adjust to your needs.
4841 */
Francois Romieua27993f2006-12-18 00:04:19 +01004842 if (pdev->broken_parity_status)
Francois Romieud03902b2006-11-23 00:00:42 +01004843 pci_cmd &= ~PCI_COMMAND_PARITY;
4844 else
4845 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4846
4847 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004848
4849 pci_write_config_word(pdev, PCI_STATUS,
4850 pci_status & (PCI_STATUS_DETECTED_PARITY |
4851 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4852 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4853
4854 /* The infamous DAC f*ckup only happens at boot time */
4855 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
françois romieue6de30d2011-01-03 15:08:37 +00004856 void __iomem *ioaddr = tp->mmio_addr;
4857
Joe Perchesbf82c182010-02-09 11:49:50 +00004858 netif_info(tp, intr, dev, "disabling PCI DAC\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07004859 tp->cp_cmd &= ~PCIDAC;
4860 RTL_W16(CPlusCmd, tp->cp_cmd);
4861 dev->features &= ~NETIF_F_HIGHDMA;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004862 }
4863
françois romieue6de30d2011-01-03 15:08:37 +00004864 rtl8169_hw_reset(tp);
Francois Romieud03902b2006-11-23 00:00:42 +01004865
4866 rtl8169_schedule_work(dev, rtl8169_reinit_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004867}
4868
Francois Romieu07d3f512007-02-21 22:40:46 +01004869static void rtl8169_tx_interrupt(struct net_device *dev,
4870 struct rtl8169_private *tp,
4871 void __iomem *ioaddr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004872{
4873 unsigned int dirty_tx, tx_left;
4874
Linus Torvalds1da177e2005-04-16 15:20:36 -07004875 dirty_tx = tp->dirty_tx;
4876 smp_rmb();
4877 tx_left = tp->cur_tx - dirty_tx;
4878
4879 while (tx_left > 0) {
4880 unsigned int entry = dirty_tx % NUM_TX_DESC;
4881 struct ring_info *tx_skb = tp->tx_skb + entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004882 u32 status;
4883
4884 rmb();
4885 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4886 if (status & DescOwn)
4887 break;
4888
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004889 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4890 tp->TxDescArray + entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004891 if (status & LastFrag) {
Stanislaw Gruszkacac4b222010-10-20 22:25:40 +00004892 dev->stats.tx_packets++;
4893 dev->stats.tx_bytes += tx_skb->skb->len;
Eric Dumazet87433bf2009-06-09 22:55:53 +00004894 dev_kfree_skb(tx_skb->skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004895 tx_skb->skb = NULL;
4896 }
4897 dirty_tx++;
4898 tx_left--;
4899 }
4900
4901 if (tp->dirty_tx != dirty_tx) {
4902 tp->dirty_tx = dirty_tx;
4903 smp_wmb();
4904 if (netif_queue_stopped(dev) &&
4905 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4906 netif_wake_queue(dev);
4907 }
Francois Romieud78ae2d2007-08-26 20:08:19 +02004908 /*
4909 * 8168 hack: TxPoll requests are lost when the Tx packets are
4910 * too close. Let's kick an extra TxPoll request when a burst
4911 * of start_xmit activity is detected (if it is not detected,
4912 * it is slow enough). -- FR
4913 */
4914 smp_rmb();
4915 if (tp->cur_tx != dirty_tx)
4916 RTL_W8(TxPoll, NPQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004917 }
4918}
4919
Francois Romieu126fa4b2005-05-12 20:09:17 -04004920static inline int rtl8169_fragmented_frame(u32 status)
4921{
4922 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4923}
4924
Eric Dumazetadea1ac72010-09-05 20:04:05 -07004925static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004926{
Linus Torvalds1da177e2005-04-16 15:20:36 -07004927 u32 status = opts1 & RxProtoMask;
4928
4929 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
Shan Weid5d3ebe2010-11-12 00:15:25 +00004930 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004931 skb->ip_summed = CHECKSUM_UNNECESSARY;
4932 else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07004933 skb_checksum_none_assert(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004934}
4935
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004936static struct sk_buff *rtl8169_try_rx_copy(void *data,
4937 struct rtl8169_private *tp,
4938 int pkt_size,
4939 dma_addr_t addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004940{
Stephen Hemmingerb4496552007-06-17 01:06:49 +02004941 struct sk_buff *skb;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004942 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004943
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004944 data = rtl8169_align(data);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004945 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004946 prefetch(data);
4947 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4948 if (skb)
4949 memcpy(skb->data, data, pkt_size);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004950 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4951
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004952 return skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004953}
4954
Eric Dumazet630b9432010-03-31 02:08:31 +00004955/*
4956 * Warning : rtl8169_rx_interrupt() might be called :
4957 * 1) from NAPI (softirq) context
4958 * (polling = 1 : we should call netif_receive_skb())
4959 * 2) from process context (rtl8169_reset_task())
4960 * (polling = 0 : we must call netif_rx() instead)
4961 */
Francois Romieu07d3f512007-02-21 22:40:46 +01004962static int rtl8169_rx_interrupt(struct net_device *dev,
4963 struct rtl8169_private *tp,
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004964 void __iomem *ioaddr, u32 budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004965{
4966 unsigned int cur_rx, rx_left;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004967 unsigned int count;
Eric Dumazet630b9432010-03-31 02:08:31 +00004968 int polling = (budget != ~(u32)0) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004969
Linus Torvalds1da177e2005-04-16 15:20:36 -07004970 cur_rx = tp->cur_rx;
4971 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
Francois Romieu865c6522008-05-11 14:51:00 +02004972 rx_left = min(rx_left, budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004973
Richard Dawe4dcb7d32005-05-27 21:12:00 +02004974 for (; rx_left > 0; rx_left--, cur_rx++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004975 unsigned int entry = cur_rx % NUM_RX_DESC;
Francois Romieu126fa4b2005-05-12 20:09:17 -04004976 struct RxDesc *desc = tp->RxDescArray + entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004977 u32 status;
4978
4979 rmb();
Francois Romieu126fa4b2005-05-12 20:09:17 -04004980 status = le32_to_cpu(desc->opts1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004981
4982 if (status & DescOwn)
4983 break;
Richard Dawe4dcb7d32005-05-27 21:12:00 +02004984 if (unlikely(status & RxRES)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00004985 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4986 status);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004987 dev->stats.rx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004988 if (status & (RxRWT | RxRUNT))
Francois Romieucebf8cc2007-10-18 12:06:54 +02004989 dev->stats.rx_length_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004990 if (status & RxCRC)
Francois Romieucebf8cc2007-10-18 12:06:54 +02004991 dev->stats.rx_crc_errors++;
Francois Romieu9dccf612006-05-14 12:31:17 +02004992 if (status & RxFOVF) {
4993 rtl8169_schedule_work(dev, rtl8169_reset_task);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004994 dev->stats.rx_fifo_errors++;
Francois Romieu9dccf612006-05-14 12:31:17 +02004995 }
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004996 rtl8169_mark_to_asic(desc, rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004997 } else {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004998 struct sk_buff *skb;
Stephen Hemmingerb4496552007-06-17 01:06:49 +02004999 dma_addr_t addr = le64_to_cpu(desc->addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005000 int pkt_size = (status & 0x00001FFF) - 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005001
Francois Romieu126fa4b2005-05-12 20:09:17 -04005002 /*
5003 * The driver does not support incoming fragmented
5004 * frames. They are seen as a symptom of over-mtu
5005 * sized frames.
5006 */
5007 if (unlikely(rtl8169_fragmented_frame(status))) {
Francois Romieucebf8cc2007-10-18 12:06:54 +02005008 dev->stats.rx_dropped++;
5009 dev->stats.rx_length_errors++;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005010 rtl8169_mark_to_asic(desc, rx_buf_sz);
Richard Dawe4dcb7d32005-05-27 21:12:00 +02005011 continue;
Francois Romieu126fa4b2005-05-12 20:09:17 -04005012 }
5013
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005014 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5015 tp, pkt_size, addr);
5016 rtl8169_mark_to_asic(desc, rx_buf_sz);
5017 if (!skb) {
5018 dev->stats.rx_dropped++;
5019 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005020 }
5021
Eric Dumazetadea1ac72010-09-05 20:04:05 -07005022 rtl8169_rx_csum(skb, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005023 skb_put(skb, pkt_size);
5024 skb->protocol = eth_type_trans(skb, dev);
5025
Francois Romieu7a8fc772011-03-01 17:18:33 +01005026 rtl8169_rx_vlan_tag(desc, skb);
5027
5028 if (likely(polling))
5029 napi_gro_receive(&tp->napi, skb);
5030 else
5031 netif_rx(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005032
Francois Romieucebf8cc2007-10-18 12:06:54 +02005033 dev->stats.rx_bytes += pkt_size;
5034 dev->stats.rx_packets++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005035 }
Francois Romieu6dccd162007-02-13 23:38:05 +01005036
5037 /* Work around for AMD plateform. */
Al Viro95e09182007-12-22 18:55:39 +00005038 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
Francois Romieu6dccd162007-02-13 23:38:05 +01005039 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5040 desc->opts2 = 0;
5041 cur_rx++;
5042 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005043 }
5044
5045 count = cur_rx - tp->cur_rx;
5046 tp->cur_rx = cur_rx;
5047
Eric Dumazet6f0333b2010-10-11 11:17:47 +00005048 tp->dirty_rx += count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005049
5050 return count;
5051}
5052
Francois Romieu07d3f512007-02-21 22:40:46 +01005053static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005054{
Francois Romieu07d3f512007-02-21 22:40:46 +01005055 struct net_device *dev = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005056 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005057 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005058 int handled = 0;
Francois Romieu865c6522008-05-11 14:51:00 +02005059 int status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005060
David Dillowf11a3772009-05-22 15:29:34 +00005061 /* loop handling interrupts until we have no new ones or
5062 * we hit a invalid/hotplug case.
5063 */
Francois Romieu865c6522008-05-11 14:51:00 +02005064 status = RTL_R16(IntrStatus);
David Dillowf11a3772009-05-22 15:29:34 +00005065 while (status && status != 0xffff) {
5066 handled = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005067
David Dillowf11a3772009-05-22 15:29:34 +00005068 /* Handle all of the error cases first. These will reset
5069 * the chip, so just exit the loop.
5070 */
5071 if (unlikely(!netif_running(dev))) {
5072 rtl8169_asic_down(ioaddr);
5073 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005074 }
David Dillowf11a3772009-05-22 15:29:34 +00005075
Francois Romieu1519e572011-02-03 12:02:36 +01005076 if (unlikely(status & RxFIFOOver)) {
5077 switch (tp->mac_version) {
5078 /* Work around for rx fifo overflow */
5079 case RTL_GIGA_MAC_VER_11:
5080 case RTL_GIGA_MAC_VER_22:
5081 case RTL_GIGA_MAC_VER_26:
5082 netif_stop_queue(dev);
5083 rtl8169_tx_timeout(dev);
5084 goto done;
Francois Romieuf60ac8e2011-02-03 17:27:52 +01005085 /* Testers needed. */
5086 case RTL_GIGA_MAC_VER_17:
5087 case RTL_GIGA_MAC_VER_19:
5088 case RTL_GIGA_MAC_VER_20:
5089 case RTL_GIGA_MAC_VER_21:
5090 case RTL_GIGA_MAC_VER_23:
5091 case RTL_GIGA_MAC_VER_24:
5092 case RTL_GIGA_MAC_VER_27:
5093 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00005094 case RTL_GIGA_MAC_VER_31:
Francois Romieu1519e572011-02-03 12:02:36 +01005095 /* Experimental science. Pktgen proof. */
5096 case RTL_GIGA_MAC_VER_12:
5097 case RTL_GIGA_MAC_VER_25:
5098 if (status == RxFIFOOver)
5099 goto done;
5100 break;
5101 default:
5102 break;
5103 }
David Dillowf11a3772009-05-22 15:29:34 +00005104 }
5105
5106 if (unlikely(status & SYSErr)) {
5107 rtl8169_pcierr_interrupt(dev);
5108 break;
5109 }
5110
5111 if (status & LinkChg)
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00005112 __rtl8169_check_link_status(dev, tp, ioaddr, true);
David Dillowf11a3772009-05-22 15:29:34 +00005113
5114 /* We need to see the lastest version of tp->intr_mask to
5115 * avoid ignoring an MSI interrupt and having to wait for
5116 * another event which may never come.
5117 */
5118 smp_rmb();
5119 if (status & tp->intr_mask & tp->napi_event) {
5120 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5121 tp->intr_mask = ~tp->napi_event;
5122
5123 if (likely(napi_schedule_prep(&tp->napi)))
5124 __napi_schedule(&tp->napi);
Joe Perchesbf82c182010-02-09 11:49:50 +00005125 else
5126 netif_info(tp, intr, dev,
5127 "interrupt %04x in poll\n", status);
David Dillowf11a3772009-05-22 15:29:34 +00005128 }
5129
5130 /* We only get a new MSI interrupt when all active irq
5131 * sources on the chip have been acknowledged. So, ack
5132 * everything we've seen and check if new sources have become
5133 * active to avoid blocking all interrupts from the chip.
5134 */
5135 RTL_W16(IntrStatus,
5136 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5137 status = RTL_R16(IntrStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005138 }
Francois Romieu1519e572011-02-03 12:02:36 +01005139done:
Linus Torvalds1da177e2005-04-16 15:20:36 -07005140 return IRQ_RETVAL(handled);
5141}
5142
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005143static int rtl8169_poll(struct napi_struct *napi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005144{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005145 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5146 struct net_device *dev = tp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005147 void __iomem *ioaddr = tp->mmio_addr;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005148 int work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005149
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005150 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005151 rtl8169_tx_interrupt(dev, tp, ioaddr);
5152
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005153 if (work_done < budget) {
Ben Hutchings288379f2009-01-19 16:43:59 -08005154 napi_complete(napi);
David Dillowf11a3772009-05-22 15:29:34 +00005155
5156 /* We need for force the visibility of tp->intr_mask
5157 * for other CPUs, as we can loose an MSI interrupt
5158 * and potentially wait for a retransmit timeout if we don't.
5159 * The posted write to IntrMask is safe, as it will
5160 * eventually make it to the chip and we won't loose anything
5161 * until it does.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005162 */
David Dillowf11a3772009-05-22 15:29:34 +00005163 tp->intr_mask = 0xffff;
David Dillow4c020a92010-03-03 16:33:10 +00005164 wmb();
Francois Romieu0e485152007-02-20 00:00:26 +01005165 RTL_W16(IntrMask, tp->intr_event);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005166 }
5167
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005168 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005169}
Linus Torvalds1da177e2005-04-16 15:20:36 -07005170
Francois Romieu523a6092008-09-10 22:28:56 +02005171static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5172{
5173 struct rtl8169_private *tp = netdev_priv(dev);
5174
5175 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5176 return;
5177
5178 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5179 RTL_W32(RxMissed, 0);
5180}
5181
Linus Torvalds1da177e2005-04-16 15:20:36 -07005182static void rtl8169_down(struct net_device *dev)
5183{
5184 struct rtl8169_private *tp = netdev_priv(dev);
5185 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005186
5187 rtl8169_delete_timer(dev);
5188
5189 netif_stop_queue(dev);
5190
Stephen Hemminger93dd79e2007-10-28 17:14:06 +01005191 napi_disable(&tp->napi);
Stephen Hemminger93dd79e2007-10-28 17:14:06 +01005192
Linus Torvalds1da177e2005-04-16 15:20:36 -07005193 spin_lock_irq(&tp->lock);
5194
5195 rtl8169_asic_down(ioaddr);
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00005196 /*
5197 * At this point device interrupts can not be enabled in any function,
5198 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5199 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5200 */
Francois Romieu523a6092008-09-10 22:28:56 +02005201 rtl8169_rx_missed(dev, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005202
5203 spin_unlock_irq(&tp->lock);
5204
5205 synchronize_irq(dev->irq);
5206
Linus Torvalds1da177e2005-04-16 15:20:36 -07005207 /* Give a racing hard_start_xmit a few cycles to complete. */
Paul E. McKenneyfbd568a3e2005-05-01 08:59:04 -07005208 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005209
Linus Torvalds1da177e2005-04-16 15:20:36 -07005210 rtl8169_tx_clear(tp);
5211
5212 rtl8169_rx_clear(tp);
françois romieu065c27c2011-01-03 15:08:12 +00005213
5214 rtl_pll_power_down(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005215}
5216
5217static int rtl8169_close(struct net_device *dev)
5218{
5219 struct rtl8169_private *tp = netdev_priv(dev);
5220 struct pci_dev *pdev = tp->pci_dev;
5221
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005222 pm_runtime_get_sync(&pdev->dev);
5223
Ivan Vecera355423d2009-02-06 21:49:57 -08005224 /* update counters before going down */
5225 rtl8169_update_counters(dev);
5226
Linus Torvalds1da177e2005-04-16 15:20:36 -07005227 rtl8169_down(dev);
5228
5229 free_irq(dev->irq, dev);
5230
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00005231 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5232 tp->RxPhyAddr);
5233 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5234 tp->TxPhyAddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005235 tp->TxDescArray = NULL;
5236 tp->RxDescArray = NULL;
5237
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005238 pm_runtime_put_sync(&pdev->dev);
5239
Linus Torvalds1da177e2005-04-16 15:20:36 -07005240 return 0;
5241}
5242
Francois Romieu07ce4062007-02-23 23:36:39 +01005243static void rtl_set_rx_mode(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005244{
5245 struct rtl8169_private *tp = netdev_priv(dev);
5246 void __iomem *ioaddr = tp->mmio_addr;
5247 unsigned long flags;
5248 u32 mc_filter[2]; /* Multicast hash filter */
Francois Romieu07d3f512007-02-21 22:40:46 +01005249 int rx_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005250 u32 tmp = 0;
5251
5252 if (dev->flags & IFF_PROMISC) {
5253 /* Unconditionally log net taps. */
Joe Perchesbf82c182010-02-09 11:49:50 +00005254 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005255 rx_mode =
5256 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5257 AcceptAllPhys;
5258 mc_filter[1] = mc_filter[0] = 0xffffffff;
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00005259 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
Joe Perches8e95a202009-12-03 07:58:21 +00005260 (dev->flags & IFF_ALLMULTI)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005261 /* Too many to filter perfectly -- accept all multicasts. */
5262 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5263 mc_filter[1] = mc_filter[0] = 0xffffffff;
5264 } else {
Jiri Pirko22bedad2010-04-01 21:22:57 +00005265 struct netdev_hw_addr *ha;
Francois Romieu07d3f512007-02-21 22:40:46 +01005266
Linus Torvalds1da177e2005-04-16 15:20:36 -07005267 rx_mode = AcceptBroadcast | AcceptMyPhys;
5268 mc_filter[1] = mc_filter[0] = 0;
Jiri Pirko22bedad2010-04-01 21:22:57 +00005269 netdev_for_each_mc_addr(ha, dev) {
5270 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005271 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5272 rx_mode |= AcceptMulticast;
5273 }
5274 }
5275
5276 spin_lock_irqsave(&tp->lock, flags);
5277
5278 tmp = rtl8169_rx_config | rx_mode |
Francois Romieu2b7b4312011-04-18 22:53:24 -07005279 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005280
Francois Romieuf887cce2008-07-17 22:24:18 +02005281 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
Francois Romieu1087f4f2007-12-26 22:46:05 +01005282 u32 data = mc_filter[0];
5283
5284 mc_filter[0] = swab32(mc_filter[1]);
5285 mc_filter[1] = swab32(data);
Francois Romieubcf0bf92006-07-26 23:14:13 +02005286 }
5287
Linus Torvalds1da177e2005-04-16 15:20:36 -07005288 RTL_W32(MAR0 + 4, mc_filter[1]);
Francois Romieu78f1cd02010-03-27 19:35:46 -07005289 RTL_W32(MAR0 + 0, mc_filter[0]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005290
Francois Romieu57a9f232007-06-04 22:10:15 +02005291 RTL_W32(RxConfig, tmp);
5292
Linus Torvalds1da177e2005-04-16 15:20:36 -07005293 spin_unlock_irqrestore(&tp->lock, flags);
5294}
5295
5296/**
5297 * rtl8169_get_stats - Get rtl8169 read/write statistics
5298 * @dev: The Ethernet Device to get statistics for
5299 *
5300 * Get TX/RX statistics for rtl8169
5301 */
5302static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5303{
5304 struct rtl8169_private *tp = netdev_priv(dev);
5305 void __iomem *ioaddr = tp->mmio_addr;
5306 unsigned long flags;
5307
5308 if (netif_running(dev)) {
5309 spin_lock_irqsave(&tp->lock, flags);
Francois Romieu523a6092008-09-10 22:28:56 +02005310 rtl8169_rx_missed(dev, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005311 spin_unlock_irqrestore(&tp->lock, flags);
5312 }
Francois Romieu5b0384f2006-08-16 16:00:01 +02005313
Francois Romieucebf8cc2007-10-18 12:06:54 +02005314 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005315}
5316
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005317static void rtl8169_net_suspend(struct net_device *dev)
Francois Romieu5d06a992006-02-23 00:47:58 +01005318{
françois romieu065c27c2011-01-03 15:08:12 +00005319 struct rtl8169_private *tp = netdev_priv(dev);
5320
Francois Romieu5d06a992006-02-23 00:47:58 +01005321 if (!netif_running(dev))
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005322 return;
Francois Romieu5d06a992006-02-23 00:47:58 +01005323
françois romieu065c27c2011-01-03 15:08:12 +00005324 rtl_pll_power_down(tp);
5325
Francois Romieu5d06a992006-02-23 00:47:58 +01005326 netif_device_detach(dev);
5327 netif_stop_queue(dev);
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005328}
Francois Romieu5d06a992006-02-23 00:47:58 +01005329
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005330#ifdef CONFIG_PM
5331
5332static int rtl8169_suspend(struct device *device)
5333{
5334 struct pci_dev *pdev = to_pci_dev(device);
5335 struct net_device *dev = pci_get_drvdata(pdev);
5336
5337 rtl8169_net_suspend(dev);
Francois Romieu1371fa62007-04-02 23:01:11 +02005338
Francois Romieu5d06a992006-02-23 00:47:58 +01005339 return 0;
5340}
5341
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005342static void __rtl8169_resume(struct net_device *dev)
5343{
françois romieu065c27c2011-01-03 15:08:12 +00005344 struct rtl8169_private *tp = netdev_priv(dev);
5345
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005346 netif_device_attach(dev);
françois romieu065c27c2011-01-03 15:08:12 +00005347
5348 rtl_pll_power_up(tp);
5349
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005350 rtl8169_schedule_work(dev, rtl8169_reset_task);
5351}
5352
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005353static int rtl8169_resume(struct device *device)
Francois Romieu5d06a992006-02-23 00:47:58 +01005354{
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005355 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieu5d06a992006-02-23 00:47:58 +01005356 struct net_device *dev = pci_get_drvdata(pdev);
Stanislaw Gruszkafccec102010-10-20 22:25:42 +00005357 struct rtl8169_private *tp = netdev_priv(dev);
5358
5359 rtl8169_init_phy(dev, tp);
Francois Romieu5d06a992006-02-23 00:47:58 +01005360
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005361 if (netif_running(dev))
5362 __rtl8169_resume(dev);
Francois Romieu5d06a992006-02-23 00:47:58 +01005363
Francois Romieu5d06a992006-02-23 00:47:58 +01005364 return 0;
5365}
5366
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005367static int rtl8169_runtime_suspend(struct device *device)
5368{
5369 struct pci_dev *pdev = to_pci_dev(device);
5370 struct net_device *dev = pci_get_drvdata(pdev);
5371 struct rtl8169_private *tp = netdev_priv(dev);
5372
5373 if (!tp->TxDescArray)
5374 return 0;
5375
5376 spin_lock_irq(&tp->lock);
5377 tp->saved_wolopts = __rtl8169_get_wol(tp);
5378 __rtl8169_set_wol(tp, WAKE_ANY);
5379 spin_unlock_irq(&tp->lock);
5380
5381 rtl8169_net_suspend(dev);
5382
5383 return 0;
5384}
5385
5386static int rtl8169_runtime_resume(struct device *device)
5387{
5388 struct pci_dev *pdev = to_pci_dev(device);
5389 struct net_device *dev = pci_get_drvdata(pdev);
5390 struct rtl8169_private *tp = netdev_priv(dev);
5391
5392 if (!tp->TxDescArray)
5393 return 0;
5394
5395 spin_lock_irq(&tp->lock);
5396 __rtl8169_set_wol(tp, tp->saved_wolopts);
5397 tp->saved_wolopts = 0;
5398 spin_unlock_irq(&tp->lock);
5399
Stanislaw Gruszkafccec102010-10-20 22:25:42 +00005400 rtl8169_init_phy(dev, tp);
5401
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005402 __rtl8169_resume(dev);
5403
5404 return 0;
5405}
5406
5407static int rtl8169_runtime_idle(struct device *device)
5408{
5409 struct pci_dev *pdev = to_pci_dev(device);
5410 struct net_device *dev = pci_get_drvdata(pdev);
5411 struct rtl8169_private *tp = netdev_priv(dev);
5412
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00005413 return tp->TxDescArray ? -EBUSY : 0;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005414}
5415
Alexey Dobriyan47145212009-12-14 18:00:08 -08005416static const struct dev_pm_ops rtl8169_pm_ops = {
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005417 .suspend = rtl8169_suspend,
5418 .resume = rtl8169_resume,
5419 .freeze = rtl8169_suspend,
5420 .thaw = rtl8169_resume,
5421 .poweroff = rtl8169_suspend,
5422 .restore = rtl8169_resume,
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005423 .runtime_suspend = rtl8169_runtime_suspend,
5424 .runtime_resume = rtl8169_runtime_resume,
5425 .runtime_idle = rtl8169_runtime_idle,
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005426};
5427
5428#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5429
5430#else /* !CONFIG_PM */
5431
5432#define RTL8169_PM_OPS NULL
5433
5434#endif /* !CONFIG_PM */
5435
Francois Romieu1765f952008-09-13 17:21:40 +02005436static void rtl_shutdown(struct pci_dev *pdev)
5437{
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005438 struct net_device *dev = pci_get_drvdata(pdev);
françois romieu4bb3f522009-06-17 11:41:45 +00005439 struct rtl8169_private *tp = netdev_priv(dev);
5440 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu1765f952008-09-13 17:21:40 +02005441
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005442 rtl8169_net_suspend(dev);
5443
Ivan Veceracc098dc2009-11-29 23:12:52 -08005444 /* restore original MAC address */
5445 rtl_rar_set(tp, dev->perm_addr);
5446
françois romieu4bb3f522009-06-17 11:41:45 +00005447 spin_lock_irq(&tp->lock);
5448
5449 rtl8169_asic_down(ioaddr);
5450
5451 spin_unlock_irq(&tp->lock);
5452
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005453 if (system_state == SYSTEM_POWER_OFF) {
françois romieuca52efd2009-07-24 12:34:19 +00005454 /* WoL fails with some 8168 when the receiver is disabled. */
5455 if (tp->features & RTL_FEATURE_WOL) {
5456 pci_clear_master(pdev);
5457
5458 RTL_W8(ChipCmd, CmdRxEnb);
5459 /* PCI commit */
5460 RTL_R8(ChipCmd);
5461 }
5462
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005463 pci_wake_from_d3(pdev, true);
5464 pci_set_power_state(pdev, PCI_D3hot);
5465 }
5466}
Francois Romieu5d06a992006-02-23 00:47:58 +01005467
Linus Torvalds1da177e2005-04-16 15:20:36 -07005468static struct pci_driver rtl8169_pci_driver = {
5469 .name = MODULENAME,
5470 .id_table = rtl8169_pci_tbl,
5471 .probe = rtl8169_init_one,
5472 .remove = __devexit_p(rtl8169_remove_one),
Francois Romieu1765f952008-09-13 17:21:40 +02005473 .shutdown = rtl_shutdown,
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005474 .driver.pm = RTL8169_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005475};
5476
Francois Romieu07d3f512007-02-21 22:40:46 +01005477static int __init rtl8169_init_module(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005478{
Jeff Garzik29917622006-08-19 17:48:59 -04005479 return pci_register_driver(&rtl8169_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005480}
5481
Francois Romieu07d3f512007-02-21 22:40:46 +01005482static void __exit rtl8169_cleanup_module(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005483{
5484 pci_unregister_driver(&rtl8169_pci_driver);
5485}
5486
5487module_init(rtl8169_init_module);
5488module_exit(rtl8169_cleanup_module);