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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/flush.c
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/mm.h>
12#include <linux/pagemap.h>
13
14#include <asm/cacheflush.h>
Russell King46097c72008-08-10 18:10:19 +010015#include <asm/cachetype.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <asm/system.h>
Russell King8d802d22005-05-10 17:31:43 +010017#include <asm/tlbflush.h>
18
Russell King1b2e2b72006-08-21 17:06:38 +010019#include "mm.h"
20
Russell King8d802d22005-05-10 17:31:43 +010021#ifdef CONFIG_CPU_CACHE_VIPT
Russell Kingd7b6b352005-09-08 15:32:23 +010022
Catalin Marinas481467d2005-09-30 16:07:04 +010023#define ALIAS_FLUSH_START 0xffff4000
24
Catalin Marinas481467d2005-09-30 16:07:04 +010025static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
26{
27 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
Catalin Marinas141fa402006-03-10 22:26:47 +000028 const int zero = 0;
Catalin Marinas481467d2005-09-30 16:07:04 +010029
Russell Kingad1ae2f2006-12-13 14:34:43 +000030 set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0);
Catalin Marinas481467d2005-09-30 16:07:04 +010031 flush_tlb_kernel_page(to);
32
33 asm( "mcrr p15, 0, %1, %0, c14\n"
Russell Kingdf71dfd2009-10-24 22:36:36 +010034 " mcr p15, 0, %2, c7, c10, 4"
Catalin Marinas481467d2005-09-30 16:07:04 +010035 :
Catalin Marinas141fa402006-03-10 22:26:47 +000036 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
Catalin Marinas481467d2005-09-30 16:07:04 +010037 : "cc");
Russell Kingdf71dfd2009-10-24 22:36:36 +010038 __flush_icache_all();
Catalin Marinas481467d2005-09-30 16:07:04 +010039}
40
Russell Kingd7b6b352005-09-08 15:32:23 +010041void flush_cache_mm(struct mm_struct *mm)
42{
43 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000044 vivt_flush_cache_mm(mm);
Russell Kingd7b6b352005-09-08 15:32:23 +010045 return;
46 }
47
48 if (cache_is_vipt_aliasing()) {
49 asm( "mcr p15, 0, %0, c7, c14, 0\n"
Russell Kingdf71dfd2009-10-24 22:36:36 +010050 " mcr p15, 0, %0, c7, c10, 4"
Russell Kingd7b6b352005-09-08 15:32:23 +010051 :
52 : "r" (0)
53 : "cc");
Russell Kingdf71dfd2009-10-24 22:36:36 +010054 __flush_icache_all();
Russell Kingd7b6b352005-09-08 15:32:23 +010055 }
56}
57
58void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
59{
60 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000061 vivt_flush_cache_range(vma, start, end);
Russell Kingd7b6b352005-09-08 15:32:23 +010062 return;
63 }
64
65 if (cache_is_vipt_aliasing()) {
66 asm( "mcr p15, 0, %0, c7, c14, 0\n"
Russell Kingdf71dfd2009-10-24 22:36:36 +010067 " mcr p15, 0, %0, c7, c10, 4"
Russell Kingd7b6b352005-09-08 15:32:23 +010068 :
69 : "r" (0)
70 : "cc");
Russell Kingdf71dfd2009-10-24 22:36:36 +010071 __flush_icache_all();
Russell Kingd7b6b352005-09-08 15:32:23 +010072 }
73}
74
75void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
76{
77 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000078 vivt_flush_cache_page(vma, user_addr, pfn);
Russell Kingd7b6b352005-09-08 15:32:23 +010079 return;
80 }
81
82 if (cache_is_vipt_aliasing())
83 flush_pfn_alias(pfn, user_addr);
84}
George G. Davisa188ad22006-09-02 18:43:20 +010085
86void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
87 unsigned long uaddr, void *kaddr,
88 unsigned long len, int write)
89{
90 if (cache_is_vivt()) {
Russell King2f0b1922009-10-25 10:40:02 +000091 vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write);
George G. Davisa188ad22006-09-02 18:43:20 +010092 return;
93 }
94
95 if (cache_is_vipt_aliasing()) {
96 flush_pfn_alias(page_to_pfn(page), uaddr);
97 return;
98 }
99
100 /* VIPT non-aliasing cache */
Rusty Russell56f8ba82009-09-24 09:34:49 -0600101 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) &&
George G. Davisa71ebdf2006-09-21 03:57:04 +0100102 vma->vm_flags & VM_EXEC) {
George G. Davisa188ad22006-09-02 18:43:20 +0100103 unsigned long addr = (unsigned long)kaddr;
104 /* only flushing the kernel mapping on non-aliasing VIPT */
105 __cpuc_coherent_kern_range(addr, addr + len);
106 }
107}
Russell King8d802d22005-05-10 17:31:43 +0100108#else
109#define flush_pfn_alias(pfn,vaddr) do { } while (0)
110#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111
Russell King8830f042005-06-20 09:51:03 +0100112void __flush_dcache_page(struct address_space *mapping, struct page *page)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 /*
115 * Writeback any data associated with the kernel mapping of this
116 * page. This ensures that data in the physical page is mutually
117 * coherent with the kernels mapping.
118 */
Nicolas Pitre13f96d82009-09-01 22:01:27 +0100119#ifdef CONFIG_HIGHMEM
120 /*
121 * kmap_atomic() doesn't set the page virtual address, and
122 * kunmap_atomic() takes care of cache flushing already.
123 */
124 if (page_address(page))
125#endif
126 __cpuc_flush_dcache_page(page_address(page));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127
128 /*
Russell King8830f042005-06-20 09:51:03 +0100129 * If this is a page cache page, and we have an aliasing VIPT cache,
130 * we only need to do one flush - which would be at the relevant
Russell King8d802d22005-05-10 17:31:43 +0100131 * userspace colour, which is congruent with page->index.
132 */
Russell King8830f042005-06-20 09:51:03 +0100133 if (mapping && cache_is_vipt_aliasing())
134 flush_pfn_alias(page_to_pfn(page),
135 page->index << PAGE_CACHE_SHIFT);
136}
137
138static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
139{
140 struct mm_struct *mm = current->active_mm;
141 struct vm_area_struct *mpnt;
142 struct prio_tree_iter iter;
143 pgoff_t pgoff;
Russell King8d802d22005-05-10 17:31:43 +0100144
145 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146 * There are possible user space mappings of this page:
147 * - VIVT cache: we need to also write back and invalidate all user
148 * data in the current VM view associated with this page.
149 * - aliasing VIPT: we only need to find one mapping of this page.
150 */
151 pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
152
153 flush_dcache_mmap_lock(mapping);
154 vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
155 unsigned long offset;
156
157 /*
158 * If this VMA is not in our MM, we can ignore it.
159 */
160 if (mpnt->vm_mm != mm)
161 continue;
162 if (!(mpnt->vm_flags & VM_MAYSHARE))
163 continue;
164 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
165 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 }
167 flush_dcache_mmap_unlock(mapping);
168}
169
170/*
171 * Ensure cache coherency between kernel mapping and userspace mapping
172 * of this page.
173 *
174 * We have three cases to consider:
175 * - VIPT non-aliasing cache: fully coherent so nothing required.
176 * - VIVT: fully aliasing, so we need to handle every alias in our
177 * current VM view.
178 * - VIPT aliasing: need to handle one alias in our current VM view.
179 *
180 * If we need to handle aliasing:
181 * If the page only exists in the page cache and there are no user
182 * space mappings, we can be lazy and remember that we may have dirty
183 * kernel cache lines for later. Otherwise, we assume we have
184 * aliasing mappings.
Russell Kingdf2f5e72005-11-30 16:02:54 +0000185 *
186 * Note that we disable the lazy flush for SMP.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 */
188void flush_dcache_page(struct page *page)
189{
190 struct address_space *mapping = page_mapping(page);
191
Russell Kingdf2f5e72005-11-30 16:02:54 +0000192#ifndef CONFIG_SMP
Nicolas Pitred73cd422008-09-15 16:44:55 -0400193 if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 set_bit(PG_dcache_dirty, &page->flags);
Russell Kingdf2f5e72005-11-30 16:02:54 +0000195 else
196#endif
197 {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 __flush_dcache_page(mapping, page);
Russell King8830f042005-06-20 09:51:03 +0100199 if (mapping && cache_is_vivt())
200 __flush_dcache_aliases(mapping, page);
Catalin Marinas826cbda2008-06-13 10:28:36 +0100201 else if (mapping)
202 __flush_icache_all();
Russell King8830f042005-06-20 09:51:03 +0100203 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204}
205EXPORT_SYMBOL(flush_dcache_page);
Russell King6020dff2006-12-30 23:17:40 +0000206
207/*
208 * Flush an anonymous page so that users of get_user_pages()
209 * can safely access the data. The expected sequence is:
210 *
211 * get_user_pages()
212 * -> flush_anon_page
213 * memcpy() to/from page
214 * if written to page, flush_dcache_page()
215 */
216void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
217{
218 unsigned long pfn;
219
220 /* VIPT non-aliasing caches need do nothing */
221 if (cache_is_vipt_nonaliasing())
222 return;
223
224 /*
225 * Write back and invalidate userspace mapping.
226 */
227 pfn = page_to_pfn(page);
228 if (cache_is_vivt()) {
229 flush_cache_page(vma, vmaddr, pfn);
230 } else {
231 /*
232 * For aliasing VIPT, we can flush an alias of the
233 * userspace address only.
234 */
235 flush_pfn_alias(pfn, vmaddr);
236 }
237
238 /*
239 * Invalidate kernel mapping. No data should be contained
240 * in this mapping of the page. FIXME: this is overkill
241 * since we actually ask for a write-back and invalidate.
242 */
243 __cpuc_flush_dcache_page(page_address(page));
244}