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review.evervolv.com / android_kernel_oneplus_msm8996 / 32d77d114c5f334419e8ccb5e61baa3236f6a586 / . / arch / arm / boot / dts / imx6dl.dtsi
blob: 4b134542c00067eb8f512e70efa8f75a486c2d6e [file] [log] [blame]
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]11#include "imx6qdl.dtsi"
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]12#include "imx6dl-pinfunc.h"
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24
25 cpu@1 {
26 compatible = "arm,cortex-a9";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
31
32 soc {
33 aips1: aips-bus@02000000 {
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]34 iomuxc: iomuxc@020e0000 {
35 compatible = "fsl,imx6dl-iomuxc";
36 reg = <0x020e0000 0x4000>;
37
Huang Shijie32d77d12013-05-09 11:29:00 +0800[diff] [blame^]38 ecspi1 {
39 pinctrl_ecspi1_1: ecspi1grp-1 {
40 fsl,pins = <
41 MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
42 MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
43 MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
44 >;
45 };
46 };
47
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]48 enet {
49 pinctrl_enet_1: enetgrp-1 {
50 fsl,pins = <
51 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
52 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
53 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
54 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
55 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
56 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
57 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
58 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
59 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
60 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
61 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
62 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
63 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
64 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
65 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
66 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
67 >;
68 };
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]69
70 pinctrl_enet_2: enetgrp-2 {
71 fsl,pins = <
72 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
73 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
74 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
75 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
76 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
77 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
78 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
79 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
80 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
81 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
82 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
83 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
84 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
85 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
86 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
87 >;
88 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]89 };
90
Huang Shijiedb372422013-05-07 15:39:19 +0800[diff] [blame]91 gpmi-nand {
92 pinctrl_gpmi_nand_1: gpmi-nand-1 {
93 fsl,pins = <
94 MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
95 MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
96 MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
97 MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
98 MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
99 MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
100 MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
101 MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
102 MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
103 MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
104 MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
105 MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
106 MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
107 MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
108 MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
109 MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
110 MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
111 >;
112 };
113 };
114
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]115 uart1 {
116 pinctrl_uart1_1: uart1grp-1 {
117 fsl,pins = <
118 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
119 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
120 >;
121 };
122 };
123
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]124 uart4 {
125 pinctrl_uart4_1: uart4grp-1 {
126 fsl,pins = <
127 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
128 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
129 >;
130 };
131 };
132
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]133 usbotg {
134 pinctrl_usbotg_2: usbotggrp-2 {
135 fsl,pins = <
136 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
137 >;
138 };
139 };
140
141 usdhc2 {
142 pinctrl_usdhc2_1: usdhc2grp-1 {
143 fsl,pins = <
144 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
145 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
146 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
147 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
148 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
149 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
150 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
151 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
152 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
153 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
154 >;
155 };
156 };
157
158 usdhc3 {
159 pinctrl_usdhc3_1: usdhc3grp-1 {
160 fsl,pins = <
161 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
162 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
163 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
164 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
165 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
166 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
167 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
168 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
169 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
170 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
171 >;
172 };
Fabio Estevam89b82912013-04-03 09:29:16 -0300[diff] [blame]173
174 pinctrl_usdhc3_2: usdhc3grp_2 {
175 fsl,pins = <
176 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
177 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
178 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
179 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
180 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
181 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
182 >;
183 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]184 };
185
186
187 };
188
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]189 pxp: pxp@020f0000 {
190 reg = <0x020f0000 0x4000>;
191 interrupts = <0 98 0x04>;
192 };
193
194 epdc: epdc@020f4000 {
195 reg = <0x020f4000 0x4000>;
196 interrupts = <0 97 0x04>;
197 };
198
199 lcdif: lcdif@020f8000 {
200 reg = <0x020f8000 0x4000>;
201 interrupts = <0 39 0x04>;
202 };
203 };
204
205 aips2: aips-bus@02100000 {
206 i2c4: i2c@021f8000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,imx1-i2c";
210 reg = <0x021f8000 0x4000>;
211 interrupts = <0 35 0x04>;
212 status = "disabled";
213 };
214 };
215 };
216};