Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 1 | /* |
| 2 | * cx18 mailbox functions |
| 3 | * |
| 4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 19 | * 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #include <stdarg.h> |
| 23 | |
| 24 | #include "cx18-driver.h" |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 25 | #include "cx18-io.h" |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 26 | #include "cx18-scb.h" |
| 27 | #include "cx18-irq.h" |
| 28 | #include "cx18-mailbox.h" |
| 29 | |
| 30 | #define API_FAST (1 << 2) /* Short timeout */ |
| 31 | #define API_SLOW (1 << 3) /* Additional 300ms timeout */ |
| 32 | |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 33 | struct cx18_api_info { |
| 34 | u32 cmd; |
| 35 | u8 flags; /* Flags, see above */ |
| 36 | u8 rpu; /* Processing unit */ |
| 37 | const char *name; /* The name of the command */ |
| 38 | }; |
| 39 | |
| 40 | #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x } |
| 41 | |
| 42 | static const struct cx18_api_info api_info[] = { |
| 43 | /* MPEG encoder API */ |
| 44 | API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), |
| 45 | API_ENTRY(CPU, CX18_EPU_DEBUG, 0), |
| 46 | API_ENTRY(CPU, CX18_CREATE_TASK, 0), |
| 47 | API_ENTRY(CPU, CX18_DESTROY_TASK, 0), |
| 48 | API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW), |
| 49 | API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW), |
| 50 | API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0), |
| 51 | API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0), |
| 52 | API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), |
| 53 | API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0), |
| 54 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0), |
| 55 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0), |
| 56 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0), |
| 57 | API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0), |
| 58 | API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0), |
| 59 | API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0), |
| 60 | API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0), |
| 61 | API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0), |
| 62 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0), |
| 63 | API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0), |
| 64 | API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0), |
| 65 | API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW), |
| 66 | API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0), |
| 67 | API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0), |
| 68 | API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0), |
| 69 | API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0), |
| 70 | API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0), |
| 71 | API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0), |
| 72 | API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0), |
| 73 | API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0), |
| 74 | API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0), |
| 75 | API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0), |
| 76 | API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0), |
| 77 | API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0), |
| 78 | API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), |
| 79 | API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), |
Hans Verkuil | 81cb727d | 2008-06-28 12:49:20 -0300 | [diff] [blame] | 80 | API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST), |
Andy Walls | 4e6b610 | 2008-11-01 01:07:36 -0300 | [diff] [blame] | 81 | API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW), |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 82 | API_ENTRY(0, 0, 0), |
| 83 | }; |
| 84 | |
| 85 | static const struct cx18_api_info *find_api_info(u32 cmd) |
| 86 | { |
| 87 | int i; |
| 88 | |
| 89 | for (i = 0; api_info[i].cmd; i++) |
| 90 | if (api_info[i].cmd == cmd) |
| 91 | return &api_info[i]; |
| 92 | return NULL; |
| 93 | } |
| 94 | |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 95 | long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb, int rpu) |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 96 | { |
Al Viro | 990c81c | 2008-05-21 00:32:01 -0300 | [diff] [blame] | 97 | struct cx18_mailbox __iomem *ack_mb; |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 98 | u32 ack_irq; |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 99 | |
| 100 | switch (rpu) { |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 101 | case APU: |
| 102 | ack_irq = IRQ_EPU_TO_APU_ACK; |
| 103 | ack_mb = &cx->scb->apu2epu_mb; |
| 104 | break; |
| 105 | case CPU: |
| 106 | ack_irq = IRQ_EPU_TO_CPU_ACK; |
| 107 | ack_mb = &cx->scb->cpu2epu_mb; |
| 108 | break; |
| 109 | default: |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 110 | CX18_WARN("Unhandled RPU (%d) for command %x ack\n", |
| 111 | rpu, mb->cmd); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 112 | return -EINVAL; |
| 113 | } |
| 114 | |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 115 | cx18_setup_page(cx, SCB_OFFSET); |
| 116 | cx18_write_sync(cx, mb->request, &ack_mb->ack); |
Andy Walls | f056d29 | 2008-10-31 20:49:12 -0300 | [diff] [blame] | 117 | cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 118 | return 0; |
| 119 | } |
| 120 | |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 121 | static void cx18_api_log_ack_delay(struct cx18 *cx, int msecs) |
| 122 | { |
| 123 | if (msecs > CX18_MAX_MB_ACK_DELAY) |
| 124 | msecs = CX18_MAX_MB_ACK_DELAY; |
| 125 | atomic_inc(&cx->mbox_stats.mb_ack_delay[msecs]); |
| 126 | } |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 127 | |
| 128 | static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) |
| 129 | { |
| 130 | const struct cx18_api_info *info = find_api_info(cmd); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 131 | u32 state, irq, req, ack, err; |
Al Viro | 990c81c | 2008-05-21 00:32:01 -0300 | [diff] [blame] | 132 | struct cx18_mailbox __iomem *mb; |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 133 | u32 __iomem *xpu_state; |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 134 | wait_queue_head_t *waitq; |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 135 | struct mutex *mb_lock; |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 136 | long int timeout, ret; |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 137 | int i; |
| 138 | |
| 139 | if (info == NULL) { |
| 140 | CX18_WARN("unknown cmd %x\n", cmd); |
| 141 | return -EINVAL; |
| 142 | } |
| 143 | |
| 144 | if (cmd == CX18_CPU_DE_SET_MDL) |
| 145 | CX18_DEBUG_HI_API("%s\n", info->name); |
| 146 | else |
| 147 | CX18_DEBUG_API("%s\n", info->name); |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 148 | |
| 149 | switch (info->rpu) { |
| 150 | case APU: |
| 151 | waitq = &cx->mb_apu_waitq; |
| 152 | mb_lock = &cx->epu2apu_mb_lock; |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 153 | irq = IRQ_EPU_TO_APU; |
| 154 | mb = &cx->scb->epu2apu_mb; |
| 155 | xpu_state = &cx->scb->apu_state; |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 156 | break; |
| 157 | case CPU: |
| 158 | waitq = &cx->mb_cpu_waitq; |
| 159 | mb_lock = &cx->epu2cpu_mb_lock; |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 160 | irq = IRQ_EPU_TO_CPU; |
| 161 | mb = &cx->scb->epu2cpu_mb; |
| 162 | xpu_state = &cx->scb->cpu_state; |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 163 | break; |
| 164 | default: |
| 165 | CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu); |
| 166 | return -EINVAL; |
| 167 | } |
| 168 | |
| 169 | mutex_lock(mb_lock); |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 170 | cx18_setup_page(cx, SCB_OFFSET); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 171 | |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 172 | /* |
| 173 | * Wait for an in-use mailbox to complete |
| 174 | * |
| 175 | * If the XPU is responding with Ack's, the mailbox shouldn't be in |
| 176 | * a busy state, since we serialize access to it on our end. |
| 177 | * |
| 178 | * If the wait for ack after sending a previous command was interrupted |
| 179 | * by a signal, we may get here and find a busy mailbox. After waiting, |
| 180 | * mark it "not busy" from our end, if the XPU hasn't ack'ed it still. |
| 181 | */ |
| 182 | state = cx18_readl(cx, xpu_state); |
| 183 | req = cx18_readl(cx, &mb->request); |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 184 | timeout = msecs_to_jiffies(20); /* 1 field at 50 Hz vertical refresh */ |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 185 | ret = wait_event_timeout(*waitq, |
| 186 | (ack = cx18_readl(cx, &mb->ack)) == req, |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 187 | timeout); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 188 | if (req != ack) { |
| 189 | /* waited long enough, make the mbox "not busy" from our end */ |
| 190 | cx18_writel(cx, req, &mb->ack); |
| 191 | CX18_ERR("mbox was found stuck busy when setting up for %s; " |
| 192 | "clearing busy and trying to proceed\n", info->name); |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 193 | } else if (ret != timeout) |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 194 | CX18_DEBUG_API("waited %u usecs for busy mbox to be acked\n", |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 195 | jiffies_to_usecs(timeout-ret)); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 196 | |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 197 | /* Build the outgoing mailbox */ |
| 198 | req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1; |
| 199 | |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 200 | cx18_writel(cx, cmd, &mb->cmd); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 201 | for (i = 0; i < args; i++) |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 202 | cx18_writel(cx, data[i], &mb->args[i]); |
| 203 | cx18_writel(cx, 0, &mb->error); |
| 204 | cx18_writel(cx, req, &mb->request); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 205 | cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */ |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 206 | |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 207 | /* |
| 208 | * Notify the XPU and wait for it to send an Ack back |
| 209 | * 21 ms = ~ 0.5 frames at a frame rate of 24 fps |
| 210 | * 42 ms = ~ 1 frame at a frame rate of 24 fps |
| 211 | */ |
| 212 | timeout = msecs_to_jiffies((info->flags & API_FAST) ? 21 : 42); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 213 | |
| 214 | CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n", |
| 215 | irq, info->name); |
Andy Walls | f056d29 | 2008-10-31 20:49:12 -0300 | [diff] [blame] | 216 | cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 217 | |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 218 | ret = wait_event_timeout( |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 219 | *waitq, |
| 220 | cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request), |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 221 | timeout); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 222 | if (ret == 0) { |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 223 | /* Timed out */ |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 224 | mutex_unlock(mb_lock); |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 225 | i = jiffies_to_msecs(timeout); |
| 226 | cx18_api_log_ack_delay(cx, i); |
| 227 | CX18_WARN("sending %s timed out waiting %d msecs for RPU " |
| 228 | "acknowledgement\n", info->name, i); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 229 | return -EINVAL; |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 230 | } else if (ret < 0) { |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 231 | /* Interrupted */ |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 232 | mutex_unlock(mb_lock); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 233 | CX18_WARN("sending %s was interrupted waiting for RPU" |
| 234 | "acknowledgement\n", info->name); |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 235 | return -EINTR; |
Andy Walls | 330c6ec | 2008-11-08 14:19:37 -0300 | [diff] [blame^] | 236 | } |
| 237 | |
| 238 | i = jiffies_to_msecs(timeout-ret); |
| 239 | cx18_api_log_ack_delay(cx, i); |
| 240 | if (ret != timeout) |
| 241 | CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n", |
| 242 | i, info->name); |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 243 | |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 244 | /* Collect data returned by the XPU */ |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 245 | for (i = 0; i < MAX_MB_ARGUMENTS; i++) |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 246 | data[i] = cx18_readl(cx, &mb->args[i]); |
| 247 | err = cx18_readl(cx, &mb->error); |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 248 | mutex_unlock(mb_lock); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 249 | |
| 250 | /* |
| 251 | * Wait for XPU to perform extra actions for the caller in some cases. |
| 252 | * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers |
| 253 | * back in a burst shortly thereafter |
| 254 | */ |
Andy Walls | 72c2d6d | 2008-11-06 01:15:41 -0300 | [diff] [blame] | 255 | if (info->flags & API_SLOW) |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 256 | cx18_msleep_timeout(300, 0); |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 257 | |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 258 | if (err) |
| 259 | CX18_DEBUG_API("mailbox error %08x for command %s\n", err, |
| 260 | info->name); |
| 261 | return err ? -EIO : 0; |
| 262 | } |
| 263 | |
| 264 | int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[]) |
| 265 | { |
Andy Walls | ac50441 | 2008-11-07 23:57:46 -0300 | [diff] [blame] | 266 | return cx18_api_call(cx, cmd, args, data); |
Hans Verkuil | 1c1e45d | 2008-04-28 20:24:33 -0300 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | static int cx18_set_filter_param(struct cx18_stream *s) |
| 270 | { |
| 271 | struct cx18 *cx = s->cx; |
| 272 | u32 mode; |
| 273 | int ret; |
| 274 | |
| 275 | mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0); |
| 276 | ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, |
| 277 | s->handle, 1, mode, cx->spatial_strength); |
| 278 | mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0); |
| 279 | ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, |
| 280 | s->handle, 0, mode, cx->temporal_strength); |
| 281 | ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, |
| 282 | s->handle, 2, cx->filter_mode >> 2, 0); |
| 283 | return ret; |
| 284 | } |
| 285 | |
| 286 | int cx18_api_func(void *priv, u32 cmd, int in, int out, |
| 287 | u32 data[CX2341X_MBOX_MAX_DATA]) |
| 288 | { |
| 289 | struct cx18 *cx = priv; |
| 290 | struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG]; |
| 291 | |
| 292 | switch (cmd) { |
| 293 | case CX2341X_ENC_SET_OUTPUT_PORT: |
| 294 | return 0; |
| 295 | case CX2341X_ENC_SET_FRAME_RATE: |
| 296 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6, |
| 297 | s->handle, 0, 0, 0, 0, data[0]); |
| 298 | case CX2341X_ENC_SET_FRAME_SIZE: |
| 299 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3, |
| 300 | s->handle, data[1], data[0]); |
| 301 | case CX2341X_ENC_SET_STREAM_TYPE: |
| 302 | return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2, |
| 303 | s->handle, data[0]); |
| 304 | case CX2341X_ENC_SET_ASPECT_RATIO: |
| 305 | return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2, |
| 306 | s->handle, data[0]); |
| 307 | |
| 308 | case CX2341X_ENC_SET_GOP_PROPERTIES: |
| 309 | return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3, |
| 310 | s->handle, data[0], data[1]); |
| 311 | case CX2341X_ENC_SET_GOP_CLOSURE: |
| 312 | return 0; |
| 313 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: |
| 314 | return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2, |
| 315 | s->handle, data[0]); |
| 316 | case CX2341X_ENC_MUTE_AUDIO: |
| 317 | return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, |
| 318 | s->handle, data[0]); |
| 319 | case CX2341X_ENC_SET_BIT_RATE: |
| 320 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5, |
| 321 | s->handle, data[0], data[1], data[2], data[3]); |
| 322 | case CX2341X_ENC_MUTE_VIDEO: |
| 323 | return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, |
| 324 | s->handle, data[0]); |
| 325 | case CX2341X_ENC_SET_FRAME_DROP_RATE: |
| 326 | return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2, |
| 327 | s->handle, data[0]); |
| 328 | case CX2341X_ENC_MISC: |
| 329 | return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4, |
| 330 | s->handle, data[0], data[1], data[2]); |
| 331 | case CX2341X_ENC_SET_DNR_FILTER_MODE: |
| 332 | cx->filter_mode = (data[0] & 3) | (data[1] << 2); |
| 333 | return cx18_set_filter_param(s); |
| 334 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
| 335 | cx->spatial_strength = data[0]; |
| 336 | cx->temporal_strength = data[1]; |
| 337 | return cx18_set_filter_param(s); |
| 338 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: |
| 339 | return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3, |
| 340 | s->handle, data[0], data[1]); |
| 341 | case CX2341X_ENC_SET_CORING_LEVELS: |
| 342 | return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5, |
| 343 | s->handle, data[0], data[1], data[2], data[3]); |
| 344 | } |
| 345 | CX18_WARN("Unknown cmd %x\n", cmd); |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS], |
| 350 | u32 cmd, int args, ...) |
| 351 | { |
| 352 | va_list ap; |
| 353 | int i; |
| 354 | |
| 355 | va_start(ap, args); |
| 356 | for (i = 0; i < args; i++) |
| 357 | data[i] = va_arg(ap, u32); |
| 358 | va_end(ap); |
| 359 | return cx18_api(cx, cmd, args, data); |
| 360 | } |
| 361 | |
| 362 | int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...) |
| 363 | { |
| 364 | u32 data[MAX_MB_ARGUMENTS]; |
| 365 | va_list ap; |
| 366 | int i; |
| 367 | |
| 368 | if (cx == NULL) { |
| 369 | CX18_ERR("cx == NULL (cmd=%x)\n", cmd); |
| 370 | return 0; |
| 371 | } |
| 372 | if (args > MAX_MB_ARGUMENTS) { |
| 373 | CX18_ERR("args too big (cmd=%x)\n", cmd); |
| 374 | args = MAX_MB_ARGUMENTS; |
| 375 | } |
| 376 | va_start(ap, args); |
| 377 | for (i = 0; i < args; i++) |
| 378 | data[i] = va_arg(ap, u32); |
| 379 | va_end(ap); |
| 380 | return cx18_api(cx, cmd, args, data); |
| 381 | } |