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review.evervolv.com / android_kernel_oneplus_msm8996 / 3325f1bcd03a0472aa1839732fb46f3c1f010205 / . / arch / arm / boot / dts / tegra20.dtsi
blob: 673f3869c9cc04579a6dd51bd2425c521c7c4656 [file] [log] [blame]
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame^]1#include <dt-bindings/gpio/tegra-gpio.h>
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]3#include "skeleton.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]4
5/ {
6 compatible = "nvidia,tegra20";
7 interrupt-parent = <&intc>;
8
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]9 aliases {
10 serial0 = &uarta;
11 serial1 = &uartb;
12 serial2 = &uartc;
13 serial3 = &uartd;
14 serial4 = &uarte;
15 };
16
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]17 host1x {
18 compatible = "nvidia,tegra20-host1x", "simple-bus";
19 reg = <0x50000000 0x00024000>;
20 interrupts = <0 65 0x04 /* mpcore syncpt */
21 0 67 0x04>; /* mpcore general */
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]22 clocks = <&tegra_car 28>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 ranges = <0x54000000 0x54000000 0x04000000>;
28
29 mpe {
30 compatible = "nvidia,tegra20-mpe";
31 reg = <0x54040000 0x00040000>;
32 interrupts = <0 68 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]33 clocks = <&tegra_car 60>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]34 };
35
36 vi {
37 compatible = "nvidia,tegra20-vi";
38 reg = <0x54080000 0x00040000>;
39 interrupts = <0 69 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]40 clocks = <&tegra_car 100>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]41 };
42
43 epp {
44 compatible = "nvidia,tegra20-epp";
45 reg = <0x540c0000 0x00040000>;
46 interrupts = <0 70 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]47 clocks = <&tegra_car 19>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]48 };
49
50 isp {
51 compatible = "nvidia,tegra20-isp";
52 reg = <0x54100000 0x00040000>;
53 interrupts = <0 71 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]54 clocks = <&tegra_car 23>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]55 };
56
57 gr2d {
58 compatible = "nvidia,tegra20-gr2d";
59 reg = <0x54140000 0x00040000>;
60 interrupts = <0 72 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]61 clocks = <&tegra_car 21>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]62 };
63
64 gr3d {
65 compatible = "nvidia,tegra20-gr3d";
66 reg = <0x54180000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]67 clocks = <&tegra_car 24>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]68 };
69
70 dc@54200000 {
71 compatible = "nvidia,tegra20-dc";
72 reg = <0x54200000 0x00040000>;
73 interrupts = <0 73 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]74 clocks = <&tegra_car 27>, <&tegra_car 121>;
75 clock-names = "disp1", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]76
77 rgb {
78 status = "disabled";
79 };
80 };
81
82 dc@54240000 {
83 compatible = "nvidia,tegra20-dc";
84 reg = <0x54240000 0x00040000>;
85 interrupts = <0 74 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]86 clocks = <&tegra_car 26>, <&tegra_car 121>;
87 clock-names = "disp2", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]88
89 rgb {
90 status = "disabled";
91 };
92 };
93
94 hdmi {
95 compatible = "nvidia,tegra20-hdmi";
96 reg = <0x54280000 0x00040000>;
97 interrupts = <0 75 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]98 clocks = <&tegra_car 51>, <&tegra_car 117>;
99 clock-names = "hdmi", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]100 status = "disabled";
101 };
102
103 tvo {
104 compatible = "nvidia,tegra20-tvo";
105 reg = <0x542c0000 0x00040000>;
106 interrupts = <0 76 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]107 clocks = <&tegra_car 102>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]108 status = "disabled";
109 };
110
111 dsi {
112 compatible = "nvidia,tegra20-dsi";
113 reg = <0x54300000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]114 clocks = <&tegra_car 48>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]115 status = "disabled";
116 };
117 };
118
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]119 timer@50004600 {
120 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x50040600 0x20>;
122 interrupts = <1 13 0x304>;
Prashant Gaikwaded3ced32013-03-01 11:32:24 -0700[diff] [blame]123 clocks = <&tegra_car 132>;
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]124 };
125
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]126 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]127 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]128 reg = <0x50041000 0x1000
129 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]130 interrupt-controller;
131 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]132 };
133
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]134 cache-controller {
135 compatible = "arm,pl310-cache";
136 reg = <0x50043000 0x1000>;
137 arm,data-latency = <5 5 2>;
138 arm,tag-latency = <4 4 2>;
139 cache-unified;
140 cache-level = <2>;
141 };
142
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]143 timer@60005000 {
144 compatible = "nvidia,tegra20-timer";
145 reg = <0x60005000 0x60>;
146 interrupts = <0 0 0x04
147 0 1 0x04
148 0 41 0x04
149 0 42 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame]150 clocks = <&tegra_car 5>;
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]151 };
152
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame]153 tegra_car: clock {
154 compatible = "nvidia,tegra20-car";
155 reg = <0x60006000 0x1000>;
156 #clock-cells = <1>;
157 };
158
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]159 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]160 compatible = "nvidia,tegra20-apbdma";
161 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]162 interrupts = <0 104 0x04
163 0 105 0x04
164 0 106 0x04
165 0 107 0x04
166 0 108 0x04
167 0 109 0x04
168 0 110 0x04
169 0 111 0x04
170 0 112 0x04
171 0 113 0x04
172 0 114 0x04
173 0 115 0x04
174 0 116 0x04
175 0 117 0x04
176 0 118 0x04
177 0 119 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]178 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]179 };
180
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]181 ahb {
182 compatible = "nvidia,tegra20-ahb";
183 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]184 };
185
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]186 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]187 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]188 reg = <0x6000d000 0x1000>;
189 interrupts = <0 32 0x04
190 0 33 0x04
191 0 34 0x04
192 0 35 0x04
193 0 55 0x04
194 0 87 0x04
195 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]196 #gpio-cells = <2>;
197 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]198 #interrupt-cells = <2>;
199 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]200 };
201
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]202 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]203 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]204 reg = <0x70000014 0x10 /* Tri-state registers */
205 0x70000080 0x20 /* Mux registers */
206 0x700000a0 0x14 /* Pull-up/down registers */
207 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]208 };
209
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]210 das {
211 compatible = "nvidia,tegra20-das";
212 reg = <0x70000c00 0x80>;
213 };
Stephen Warrenfc5c3062013-03-06 11:28:32 -0700[diff] [blame]214
Lucas Stach0698ed12013-01-05 02:18:44 +0100[diff] [blame]215 tegra_ac97: ac97 {
216 compatible = "nvidia,tegra20-ac97";
217 reg = <0x70002000 0x200>;
218 interrupts = <0 81 0x04>;
219 nvidia,dma-request-selector = <&apbdma 12>;
220 clocks = <&tegra_car 3>;
221 status = "disabled";
222 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]223
224 tegra_i2s1: i2s@70002800 {
225 compatible = "nvidia,tegra20-i2s";
226 reg = <0x70002800 0x200>;
227 interrupts = <0 13 0x04>;
228 nvidia,dma-request-selector = <&apbdma 2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]229 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]230 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]231 };
232
233 tegra_i2s2: i2s@70002a00 {
234 compatible = "nvidia,tegra20-i2s";
235 reg = <0x70002a00 0x200>;
236 interrupts = <0 3 0x04>;
237 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]238 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]239 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]240 };
241
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]242 /*
243 * There are two serial driver i.e. 8250 based simple serial
244 * driver and APB DMA based serial driver for higher baudrate
245 * and performace. To enable the 8250 based driver, the compatible
246 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
247 * driver, the comptible is "nvidia,tegra20-hsuart".
248 */
249 uarta: serial@70006000 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]250 compatible = "nvidia,tegra20-uart";
251 reg = <0x70006000 0x40>;
252 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]253 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]254 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]255 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]256 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]257 };
258
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]259 uartb: serial@70006040 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]260 compatible = "nvidia,tegra20-uart";
261 reg = <0x70006040 0x40>;
262 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]263 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]264 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]265 clocks = <&tegra_car 96>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]266 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]267 };
268
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]269 uartc: serial@70006200 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]270 compatible = "nvidia,tegra20-uart";
271 reg = <0x70006200 0x100>;
272 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]273 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]274 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]275 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]276 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]277 };
278
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]279 uartd: serial@70006300 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]280 compatible = "nvidia,tegra20-uart";
281 reg = <0x70006300 0x100>;
282 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]283 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]284 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]285 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]286 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]287 };
288
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]289 uarte: serial@70006400 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]290 compatible = "nvidia,tegra20-uart";
291 reg = <0x70006400 0x100>;
292 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]293 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]294 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]295 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]296 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]297 };
298
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]299 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]300 compatible = "nvidia,tegra20-pwm";
301 reg = <0x7000a000 0x100>;
302 #pwm-cells = <2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]303 clocks = <&tegra_car 17>;
Andrew Chewb69cd982013-03-12 16:40:51 -0700[diff] [blame]304 status = "disabled";
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]305 };
306
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]307 rtc {
308 compatible = "nvidia,tegra20-rtc";
309 reg = <0x7000e000 0x100>;
310 interrupts = <0 2 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame]311 clocks = <&tegra_car 4>;
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]312 };
313
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]314 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]315 compatible = "nvidia,tegra20-i2c";
316 reg = <0x7000c000 0x100>;
317 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]318 #address-cells = <1>;
319 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]320 clocks = <&tegra_car 12>, <&tegra_car 124>;
321 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]322 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]323 };
324
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]325 spi@7000c380 {
326 compatible = "nvidia,tegra20-sflash";
327 reg = <0x7000c380 0x80>;
328 interrupts = <0 39 0x04>;
329 nvidia,dma-request-selector = <&apbdma 11>;
330 #address-cells = <1>;
331 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]332 clocks = <&tegra_car 43>;
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]333 status = "disabled";
334 };
335
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]336 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]337 compatible = "nvidia,tegra20-i2c";
338 reg = <0x7000c400 0x100>;
339 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]340 #address-cells = <1>;
341 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]342 clocks = <&tegra_car 54>, <&tegra_car 124>;
343 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]344 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]345 };
346
347 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]348 compatible = "nvidia,tegra20-i2c";
349 reg = <0x7000c500 0x100>;
350 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]351 #address-cells = <1>;
352 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]353 clocks = <&tegra_car 67>, <&tegra_car 124>;
354 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]355 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]356 };
357
358 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]359 compatible = "nvidia,tegra20-i2c-dvc";
360 reg = <0x7000d000 0x200>;
361 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]362 #address-cells = <1>;
363 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]364 clocks = <&tegra_car 47>, <&tegra_car 124>;
365 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]366 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]367 };
368
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]369 spi@7000d400 {
370 compatible = "nvidia,tegra20-slink";
371 reg = <0x7000d400 0x200>;
372 interrupts = <0 59 0x04>;
373 nvidia,dma-request-selector = <&apbdma 15>;
374 #address-cells = <1>;
375 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]376 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]377 status = "disabled";
378 };
379
380 spi@7000d600 {
381 compatible = "nvidia,tegra20-slink";
382 reg = <0x7000d600 0x200>;
383 interrupts = <0 82 0x04>;
384 nvidia,dma-request-selector = <&apbdma 16>;
385 #address-cells = <1>;
386 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]387 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]388 status = "disabled";
389 };
390
391 spi@7000d800 {
392 compatible = "nvidia,tegra20-slink";
Laxman Dewangan57471c82013-03-22 12:35:06 -0600[diff] [blame]393 reg = <0x7000d800 0x200>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]394 interrupts = <0 83 0x04>;
395 nvidia,dma-request-selector = <&apbdma 17>;
396 #address-cells = <1>;
397 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]398 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]399 status = "disabled";
400 };
401
402 spi@7000da00 {
403 compatible = "nvidia,tegra20-slink";
404 reg = <0x7000da00 0x200>;
405 interrupts = <0 93 0x04>;
406 nvidia,dma-request-selector = <&apbdma 18>;
407 #address-cells = <1>;
408 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]409 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]410 status = "disabled";
411 };
412
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]413 kbc {
414 compatible = "nvidia,tegra20-kbc";
415 reg = <0x7000e200 0x100>;
416 interrupts = <0 85 0x04>;
417 clocks = <&tegra_car 36>;
418 status = "disabled";
419 };
420
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]421 pmc {
422 compatible = "nvidia,tegra20-pmc";
423 reg = <0x7000e400 0x400>;
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]424 clocks = <&tegra_car 110>, <&clk32k_in>;
425 clock-names = "pclk", "clk32k_in";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]426 };
427
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]428 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]429 compatible = "nvidia,tegra20-mc";
430 reg = <0x7000f000 0x024
431 0x7000f03c 0x3c4>;
432 interrupts = <0 77 0x04>;
433 };
434
Hiroshi Doyu109269e2013-01-29 10:30:30 +0200[diff] [blame]435 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]436 compatible = "nvidia,tegra20-gart";
437 reg = <0x7000f024 0x00000018 /* controller registers */
438 0x58000000 0x02000000>; /* GART aperture */
439 };
440
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]441 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]442 compatible = "nvidia,tegra20-emc";
443 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]444 #address-cells = <1>;
445 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]446 };
447
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]448 usb@c5000000 {
449 compatible = "nvidia,tegra20-ehci", "usb-ehci";
450 reg = <0xc5000000 0x4000>;
451 interrupts = <0 20 0x04>;
452 phy_type = "utmi";
453 nvidia,has-legacy-mode;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]454 clocks = <&tegra_car 22>;
Venu Byravarasub4e07472012-12-13 20:59:07 +0000[diff] [blame]455 nvidia,needs-double-reset;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]456 nvidia,phy = <&phy1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]457 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]458 };
459
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]460 phy1: usb-phy@c5000000 {
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]461 compatible = "nvidia,tegra20-usb-phy";
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]462 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]463 phy_type = "utmi";
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]464 clocks = <&tegra_car 22>,
465 <&tegra_car 127>,
466 <&tegra_car 106>,
467 <&tegra_car 22>;
468 clock-names = "reg", "pll_u", "timer", "utmi-pads";
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]469 nvidia,has-legacy-mode;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]470 hssync_start_delay = <9>;
471 idle_wait_delay = <17>;
472 elastic_limit = <16>;
473 term_range_adj = <6>;
474 xcvr_setup = <9>;
475 xcvr_lsfslew = <1>;
476 xcvr_lsrslew = <1>;
477 status = "disabled";
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]478 };
479
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]480 usb@c5004000 {
481 compatible = "nvidia,tegra20-ehci", "usb-ehci";
482 reg = <0xc5004000 0x4000>;
483 interrupts = <0 21 0x04>;
484 phy_type = "ulpi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]485 clocks = <&tegra_car 58>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]486 nvidia,phy = <&phy2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]487 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]488 };
489
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]490 phy2: usb-phy@c5004000 {
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]491 compatible = "nvidia,tegra20-usb-phy";
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]492 reg = <0xc5004000 0x4000>;
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]493 phy_type = "ulpi";
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]494 clocks = <&tegra_car 58>,
495 <&tegra_car 127>,
496 <&tegra_car 93>;
497 clock-names = "reg", "pll_u", "ulpi-link";
498 status = "disabled";
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]499 };
500
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]501 usb@c5008000 {
502 compatible = "nvidia,tegra20-ehci", "usb-ehci";
503 reg = <0xc5008000 0x4000>;
504 interrupts = <0 97 0x04>;
505 phy_type = "utmi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]506 clocks = <&tegra_car 59>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]507 nvidia,phy = <&phy3>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]508 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]509 };
510
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]511 phy3: usb-phy@c5008000 {
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]512 compatible = "nvidia,tegra20-usb-phy";
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]513 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]514 phy_type = "utmi";
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530[diff] [blame]515 clocks = <&tegra_car 59>,
516 <&tegra_car 127>,
517 <&tegra_car 106>,
518 <&tegra_car 22>;
519 clock-names = "reg", "pll_u", "timer", "utmi-pads";
520 hssync_start_delay = <9>;
521 idle_wait_delay = <17>;
522 elastic_limit = <16>;
523 term_range_adj = <6>;
524 xcvr_setup = <9>;
525 xcvr_lsfslew = <2>;
526 xcvr_lsrslew = <2>;
527 status = "disabled";
Stephen Warren5d324412013-03-06 11:28:33 -0700[diff] [blame]528 };
529
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]530 sdhci@c8000000 {
531 compatible = "nvidia,tegra20-sdhci";
532 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]533 interrupts = <0 14 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]534 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]535 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]536 };
537
538 sdhci@c8000200 {
539 compatible = "nvidia,tegra20-sdhci";
540 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]541 interrupts = <0 15 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]542 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]543 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]544 };
545
546 sdhci@c8000400 {
547 compatible = "nvidia,tegra20-sdhci";
548 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]549 interrupts = <0 19 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]550 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]551 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]552 };
553
554 sdhci@c8000600 {
555 compatible = "nvidia,tegra20-sdhci";
556 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]557 interrupts = <0 31 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]558 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]559 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]560 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]561
Hiroshi Doyu4dd2bd32013-01-11 15:26:55 +0200[diff] [blame]562 cpus {
563 #address-cells = <1>;
564 #size-cells = <0>;
565
566 cpu@0 {
567 device_type = "cpu";
568 compatible = "arm,cortex-a9";
569 reg = <0>;
570 };
571
572 cpu@1 {
573 device_type = "cpu";
574 compatible = "arm,cortex-a9";
575 reg = <1>;
576 };
577 };
578
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]579 pmu {
580 compatible = "arm,cortex-a9-pmu";
581 interrupts = <0 56 0x04
582 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]583 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]584};