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review.evervolv.com / android_kernel_oneplus_msm8996 / 3325f1bcd03a0472aa1839732fb46f3c1f010205 / . / arch / arm / boot / dts / tegra30.dtsi
blob: 1fe8c3abc2f4574ac9af30719e91a84f7a7ad6a5 [file] [log] [blame]
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame^]1#include <dt-bindings/gpio/tegra-gpio.h>
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]3#include "skeleton.dtsi"
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]4
5/ {
6 compatible = "nvidia,tegra30";
7 interrupt-parent = <&intc>;
8
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]9 aliases {
10 serial0 = &uarta;
11 serial1 = &uartb;
12 serial2 = &uartc;
13 serial3 = &uartd;
14 serial4 = &uarte;
15 };
16
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]17 host1x {
18 compatible = "nvidia,tegra30-host1x", "simple-bus";
19 reg = <0x50000000 0x00024000>;
20 interrupts = <0 65 0x04 /* mpcore syncpt */
21 0 67 0x04>; /* mpcore general */
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]22 clocks = <&tegra_car 28>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 ranges = <0x54000000 0x54000000 0x04000000>;
28
29 mpe {
30 compatible = "nvidia,tegra30-mpe";
31 reg = <0x54040000 0x00040000>;
32 interrupts = <0 68 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]33 clocks = <&tegra_car 60>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]34 };
35
36 vi {
37 compatible = "nvidia,tegra30-vi";
38 reg = <0x54080000 0x00040000>;
39 interrupts = <0 69 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]40 clocks = <&tegra_car 164>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]41 };
42
43 epp {
44 compatible = "nvidia,tegra30-epp";
45 reg = <0x540c0000 0x00040000>;
46 interrupts = <0 70 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]47 clocks = <&tegra_car 19>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]48 };
49
50 isp {
51 compatible = "nvidia,tegra30-isp";
52 reg = <0x54100000 0x00040000>;
53 interrupts = <0 71 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]54 clocks = <&tegra_car 23>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]55 };
56
57 gr2d {
58 compatible = "nvidia,tegra30-gr2d";
59 reg = <0x54140000 0x00040000>;
60 interrupts = <0 72 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]61 clocks = <&tegra_car 21>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]62 };
63
64 gr3d {
65 compatible = "nvidia,tegra30-gr3d";
66 reg = <0x54180000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]67 clocks = <&tegra_car 24 &tegra_car 98>;
68 clock-names = "3d", "3d2";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]69 };
70
71 dc@54200000 {
72 compatible = "nvidia,tegra30-dc";
73 reg = <0x54200000 0x00040000>;
74 interrupts = <0 73 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]75 clocks = <&tegra_car 27>, <&tegra_car 179>;
76 clock-names = "disp1", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]77
78 rgb {
79 status = "disabled";
80 };
81 };
82
83 dc@54240000 {
84 compatible = "nvidia,tegra30-dc";
85 reg = <0x54240000 0x00040000>;
86 interrupts = <0 74 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]87 clocks = <&tegra_car 26>, <&tegra_car 179>;
88 clock-names = "disp2", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]89
90 rgb {
91 status = "disabled";
92 };
93 };
94
95 hdmi {
96 compatible = "nvidia,tegra30-hdmi";
97 reg = <0x54280000 0x00040000>;
98 interrupts = <0 75 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]99 clocks = <&tegra_car 51>, <&tegra_car 189>;
100 clock-names = "hdmi", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]101 status = "disabled";
102 };
103
104 tvo {
105 compatible = "nvidia,tegra30-tvo";
106 reg = <0x542c0000 0x00040000>;
107 interrupts = <0 76 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]108 clocks = <&tegra_car 169>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]109 status = "disabled";
110 };
111
112 dsi {
113 compatible = "nvidia,tegra30-dsi";
114 reg = <0x54300000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]115 clocks = <&tegra_car 48>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]116 status = "disabled";
117 };
118 };
119
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]120 timer@50004600 {
121 compatible = "arm,cortex-a9-twd-timer";
122 reg = <0x50040600 0x20>;
123 interrupts = <1 13 0xf04>;
Prashant Gaikwaded3ced32013-03-01 11:32:24 -0700[diff] [blame]124 clocks = <&tegra_car 214>;
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]125 };
126
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]127 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]128 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]129 reg = <0x50041000 0x1000
130 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]131 interrupt-controller;
132 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]133 };
134
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]135 cache-controller {
136 compatible = "arm,pl310-cache";
137 reg = <0x50043000 0x1000>;
138 arm,data-latency = <6 6 2>;
139 arm,tag-latency = <5 5 2>;
140 cache-unified;
141 cache-level = <2>;
142 };
143
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]144 timer@60005000 {
145 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
146 reg = <0x60005000 0x400>;
147 interrupts = <0 0 0x04
148 0 1 0x04
149 0 41 0x04
150 0 42 0x04
151 0 121 0x04
152 0 122 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame]153 clocks = <&tegra_car 5>;
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]154 };
155
Prashant Gaikwad95985662013-01-11 13:16:23 +0530[diff] [blame]156 tegra_car: clock {
157 compatible = "nvidia,tegra30-car";
158 reg = <0x60006000 0x1000>;
159 #clock-cells = <1>;
160 };
161
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]162 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]163 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
164 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]165 interrupts = <0 104 0x04
166 0 105 0x04
167 0 106 0x04
168 0 107 0x04
169 0 108 0x04
170 0 109 0x04
171 0 110 0x04
172 0 111 0x04
173 0 112 0x04
174 0 113 0x04
175 0 114 0x04
176 0 115 0x04
177 0 116 0x04
178 0 117 0x04
179 0 118 0x04
180 0 119 0x04
181 0 128 0x04
182 0 129 0x04
183 0 130 0x04
184 0 131 0x04
185 0 132 0x04
186 0 133 0x04
187 0 134 0x04
188 0 135 0x04
189 0 136 0x04
190 0 137 0x04
191 0 138 0x04
192 0 139 0x04
193 0 140 0x04
194 0 141 0x04
195 0 142 0x04
196 0 143 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]197 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]198 };
199
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]200 ahb: ahb {
201 compatible = "nvidia,tegra30-ahb";
202 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
203 };
204
205 gpio: gpio {
Laxman Dewangan35f210e2012-12-19 20:27:12 +0530[diff] [blame]206 compatible = "nvidia,tegra30-gpio";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]207 reg = <0x6000d000 0x1000>;
208 interrupts = <0 32 0x04
209 0 33 0x04
210 0 34 0x04
211 0 35 0x04
212 0 55 0x04
213 0 87 0x04
214 0 89 0x04
215 0 125 0x04>;
216 #gpio-cells = <2>;
217 gpio-controller;
218 #interrupt-cells = <2>;
219 interrupt-controller;
220 };
221
222 pinmux: pinmux {
223 compatible = "nvidia,tegra30-pinmux";
Pritesh Raithatha322337b2012-10-30 15:37:09 +0530[diff] [blame]224 reg = <0x70000868 0xd4 /* Pad control registers */
225 0x70003000 0x3e4>; /* Mux registers */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]226 };
227
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]228 /*
229 * There are two serial driver i.e. 8250 based simple serial
230 * driver and APB DMA based serial driver for higher baudrate
231 * and performace. To enable the 8250 based driver, the compatible
232 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
233 * the APB DMA based serial driver, the comptible is
234 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
235 */
236 uarta: serial@70006000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]237 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
238 reg = <0x70006000 0x40>;
239 reg-shift = <2>;
240 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]241 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]242 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]243 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]244 };
245
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]246 uartb: serial@70006040 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]247 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
248 reg = <0x70006040 0x40>;
249 reg-shift = <2>;
250 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]251 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]252 clocks = <&tegra_car 160>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]253 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]254 };
255
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]256 uartc: serial@70006200 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]257 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
258 reg = <0x70006200 0x100>;
259 reg-shift = <2>;
260 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]261 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]262 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]263 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]264 };
265
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]266 uartd: serial@70006300 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]267 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
268 reg = <0x70006300 0x100>;
269 reg-shift = <2>;
270 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]271 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]272 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]273 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]274 };
275
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]276 uarte: serial@70006400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]277 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
278 reg = <0x70006400 0x100>;
279 reg-shift = <2>;
280 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]281 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]282 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]283 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]284 };
285
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]286 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]287 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
288 reg = <0x7000a000 0x100>;
289 #pwm-cells = <2>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]290 clocks = <&tegra_car 17>;
Andrew Chewb69cd982013-03-12 16:40:51 -0700[diff] [blame]291 status = "disabled";
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]292 };
293
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]294 rtc {
295 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
296 reg = <0x7000e000 0x100>;
297 interrupts = <0 2 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame]298 clocks = <&tegra_car 4>;
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]299 };
300
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]301 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]302 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]303 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]304 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]305 #address-cells = <1>;
306 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]307 clocks = <&tegra_car 12>, <&tegra_car 182>;
308 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]309 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]310 };
311
312 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]313 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]314 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]315 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]316 #address-cells = <1>;
317 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]318 clocks = <&tegra_car 54>, <&tegra_car 182>;
319 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]320 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]321 };
322
323 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]324 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]325 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]326 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]327 #address-cells = <1>;
328 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]329 clocks = <&tegra_car 67>, <&tegra_car 182>;
330 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]331 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]332 };
333
334 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]335 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
336 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]337 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]338 #address-cells = <1>;
339 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]340 clocks = <&tegra_car 103>, <&tegra_car 182>;
341 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]342 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]343 };
344
345 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]346 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]347 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]348 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]349 #address-cells = <1>;
350 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]351 clocks = <&tegra_car 47>, <&tegra_car 182>;
352 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]353 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]354 };
355
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]356 spi@7000d400 {
357 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
358 reg = <0x7000d400 0x200>;
359 interrupts = <0 59 0x04>;
360 nvidia,dma-request-selector = <&apbdma 15>;
361 #address-cells = <1>;
362 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]363 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]364 status = "disabled";
365 };
366
367 spi@7000d600 {
368 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
369 reg = <0x7000d600 0x200>;
370 interrupts = <0 82 0x04>;
371 nvidia,dma-request-selector = <&apbdma 16>;
372 #address-cells = <1>;
373 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]374 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]375 status = "disabled";
376 };
377
378 spi@7000d800 {
379 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
Laxman Dewangan57471c82013-03-22 12:35:06 -0600[diff] [blame]380 reg = <0x7000d800 0x200>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]381 interrupts = <0 83 0x04>;
382 nvidia,dma-request-selector = <&apbdma 17>;
383 #address-cells = <1>;
384 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]385 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]386 status = "disabled";
387 };
388
389 spi@7000da00 {
390 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
391 reg = <0x7000da00 0x200>;
392 interrupts = <0 93 0x04>;
393 nvidia,dma-request-selector = <&apbdma 18>;
394 #address-cells = <1>;
395 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]396 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]397 status = "disabled";
398 };
399
400 spi@7000dc00 {
401 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
402 reg = <0x7000dc00 0x200>;
403 interrupts = <0 94 0x04>;
404 nvidia,dma-request-selector = <&apbdma 27>;
405 #address-cells = <1>;
406 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]407 clocks = <&tegra_car 104>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]408 status = "disabled";
409 };
410
411 spi@7000de00 {
412 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
413 reg = <0x7000de00 0x200>;
414 interrupts = <0 79 0x04>;
415 nvidia,dma-request-selector = <&apbdma 28>;
416 #address-cells = <1>;
417 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]418 clocks = <&tegra_car 105>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]419 status = "disabled";
420 };
421
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]422 kbc {
423 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
424 reg = <0x7000e200 0x100>;
425 interrupts = <0 85 0x04>;
426 clocks = <&tegra_car 36>;
427 status = "disabled";
428 };
429
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]430 pmc {
Joseph Lo2b84e532013-02-26 16:27:43 +0000[diff] [blame]431 compatible = "nvidia,tegra30-pmc";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]432 reg = <0x7000e400 0x400>;
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]433 clocks = <&tegra_car 218>, <&clk32k_in>;
434 clock-names = "pclk", "clk32k_in";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]435 };
436
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]437 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]438 compatible = "nvidia,tegra30-mc";
439 reg = <0x7000f000 0x010
440 0x7000f03c 0x1b4
441 0x7000f200 0x028
442 0x7000f284 0x17c>;
443 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]444 };
445
Hiroshi Doyu3fbf07d2013-01-29 10:30:29 +0200[diff] [blame]446 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]447 compatible = "nvidia,tegra30-smmu";
448 reg = <0x7000f010 0x02c
449 0x7000f1f0 0x010
450 0x7000f228 0x05c>;
451 nvidia,#asids = <4>; /* # of ASIDs */
452 dma-window = <0 0x40000000>; /* IOVA start & length */
453 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]454 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]455
456 ahub {
457 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]458 reg = <0x70080000 0x200
459 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]460 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]461 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]462 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
463 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
464 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
465 <&tegra_car 110>, <&tegra_car 162>;
466 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
467 "i2s3", "i2s4", "dam0", "dam1", "dam2",
468 "spdif_in";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]469 ranges;
470 #address-cells = <1>;
471 #size-cells = <1>;
472
473 tegra_i2s0: i2s@70080300 {
474 compatible = "nvidia,tegra30-i2s";
475 reg = <0x70080300 0x100>;
476 nvidia,ahub-cif-ids = <4 4>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]477 clocks = <&tegra_car 30>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]478 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]479 };
480
481 tegra_i2s1: i2s@70080400 {
482 compatible = "nvidia,tegra30-i2s";
483 reg = <0x70080400 0x100>;
484 nvidia,ahub-cif-ids = <5 5>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]485 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]486 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]487 };
488
489 tegra_i2s2: i2s@70080500 {
490 compatible = "nvidia,tegra30-i2s";
491 reg = <0x70080500 0x100>;
492 nvidia,ahub-cif-ids = <6 6>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]493 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]494 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]495 };
496
497 tegra_i2s3: i2s@70080600 {
498 compatible = "nvidia,tegra30-i2s";
499 reg = <0x70080600 0x100>;
500 nvidia,ahub-cif-ids = <7 7>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]501 clocks = <&tegra_car 101>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]502 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]503 };
504
505 tegra_i2s4: i2s@70080700 {
506 compatible = "nvidia,tegra30-i2s";
507 reg = <0x70080700 0x100>;
508 nvidia,ahub-cif-ids = <8 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]509 clocks = <&tegra_car 102>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]510 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]511 };
512 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]513
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]514 sdhci@78000000 {
515 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
516 reg = <0x78000000 0x200>;
517 interrupts = <0 14 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]518 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]519 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]520 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]521
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]522 sdhci@78000200 {
523 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
524 reg = <0x78000200 0x200>;
525 interrupts = <0 15 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]526 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]527 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]528 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]529
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]530 sdhci@78000400 {
531 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
532 reg = <0x78000400 0x200>;
533 interrupts = <0 19 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]534 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]535 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]536 };
537
538 sdhci@78000600 {
539 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
540 reg = <0x78000600 0x200>;
541 interrupts = <0 31 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]542 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]543 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]544 };
545
Hiroshi Doyu7d19a342013-01-11 15:11:54 +0200[diff] [blame]546 cpus {
547 #address-cells = <1>;
548 #size-cells = <0>;
549
550 cpu@0 {
551 device_type = "cpu";
552 compatible = "arm,cortex-a9";
553 reg = <0>;
554 };
555
556 cpu@1 {
557 device_type = "cpu";
558 compatible = "arm,cortex-a9";
559 reg = <1>;
560 };
561
562 cpu@2 {
563 device_type = "cpu";
564 compatible = "arm,cortex-a9";
565 reg = <2>;
566 };
567
568 cpu@3 {
569 device_type = "cpu";
570 compatible = "arm,cortex-a9";
571 reg = <3>;
572 };
573 };
574
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]575 pmu {
576 compatible = "arm,cortex-a9-pmu";
577 interrupts = <0 144 0x04
578 0 145 0x04
579 0 146 0x04
580 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]581 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]582};