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review.evervolv.com / android_kernel_oneplus_msm8996 / 33a6675485f27adc182faa856944836e85520fa1 / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 5d7b759f06a80b8502a2f49829b1537f8d54e8c7 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
Adam Baker33a66752013-06-02 22:59:50 +0100[diff] [blame^]7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 cpu@0 {
12 device_type = "cpu";
13 compatible = "marvell,feroceon";
14 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
15 clock-names = "cpu_clk", "ddrclk", "powersave";
16 };
17 };
18
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 };
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]23 intc: interrupt-controller {
24 compatible = "marvell,orion-intc", "marvell,intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 reg = <0xf1020204 0x04>,
28 <0xf1020214 0x04>;
29 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]30
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]31 ocp@f1000000 {
32 compatible = "simple-bus";
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]33 ranges = <0x00000000 0xf1000000 0x4000000
34 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]35 #address-cells = <1>;
36 #size-cells = <1>;
37
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]38 core_clk: core-clocks@10030 {
39 compatible = "marvell,kirkwood-core-clock";
40 reg = <0x10030 0x4>;
41 #clock-cells = <1>;
42 };
43
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]44 gpio0: gpio@10100 {
45 compatible = "marvell,orion-gpio";
46 #gpio-cells = <2>;
47 gpio-controller;
48 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]49 ngpios = <32>;
50 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]51 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]52 interrupts = <35>, <36>, <37>, <38>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]53 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]54 };
55
56 gpio1: gpio@10140 {
57 compatible = "marvell,orion-gpio";
58 #gpio-cells = <2>;
59 gpio-controller;
60 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]61 ngpios = <18>;
62 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]63 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]64 interrupts = <39>, <40>, <41>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]65 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]66 };
67
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]68 serial@12000 {
69 compatible = "ns16550a";
70 reg = <0x12000 0x100>;
71 reg-shift = <2>;
72 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]73 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]74 status = "disabled";
75 };
76
77 serial@12100 {
78 compatible = "ns16550a";
79 reg = <0x12100 0x100>;
80 reg-shift = <2>;
81 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]82 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]83 status = "disabled";
84 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]85
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]86 spi@10600 {
87 compatible = "marvell,orion-spi";
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <0>;
91 interrupts = <23>;
92 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]93 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]94 status = "disabled";
95 };
96
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]97 gate_clk: clock-gating-control@2011c {
98 compatible = "marvell,kirkwood-gating-clock";
99 reg = <0x2011c 0x4>;
100 clocks = <&core_clk 0>;
101 #clock-cells = <1>;
102 };
103
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]104 wdt@20300 {
105 compatible = "marvell,orion-wdt";
106 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]107 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]108 status = "okay";
109 };
110
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame]111 xor@60800 {
112 compatible = "marvell,orion-xor";
113 reg = <0x60800 0x100
114 0x60A00 0x100>;
115 status = "okay";
116 clocks = <&gate_clk 8>;
117
118 xor00 {
119 interrupts = <5>;
120 dmacap,memcpy;
121 dmacap,xor;
122 };
123 xor01 {
124 interrupts = <6>;
125 dmacap,memcpy;
126 dmacap,xor;
127 dmacap,memset;
128 };
129 };
130
131 xor@60900 {
132 compatible = "marvell,orion-xor";
133 reg = <0x60900 0x100
134 0xd0B00 0x100>;
135 status = "okay";
136 clocks = <&gate_clk 16>;
137
138 xor00 {
139 interrupts = <7>;
140 dmacap,memcpy;
141 dmacap,xor;
142 };
143 xor01 {
144 interrupts = <8>;
145 dmacap,memcpy;
146 dmacap,xor;
147 dmacap,memset;
148 };
149 };
150
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]151 ehci@50000 {
152 compatible = "marvell,orion-ehci";
153 reg = <0x50000 0x1000>;
154 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100[diff] [blame]155 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]156 status = "okay";
157 };
158
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]159 nand@3000000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 cle = <0>;
163 ale = <1>;
164 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]165 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]166 reg = <0x3000000 0x400>;
167 chip-delay = <25>;
168 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]169 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]170 status = "disabled";
171 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]172
173 i2c@11000 {
174 compatible = "marvell,mv64xxx-i2c";
175 reg = <0x11000 0x20>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 interrupts = <29>;
179 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]180 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]181 status = "disabled";
182 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]183
184 crypto@30000 {
185 compatible = "marvell,orion-crypto";
186 reg = <0x30000 0x10000>,
187 <0xf5000000 0x800>;
188 reg-names = "regs", "sram";
189 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]190 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]191 status = "okay";
192 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]193 };
194};