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Tomi Valkeinen559d6702009-11-03 11:23:50 +02001/*
2 * linux/drivers/video/omap2/dss/dss.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DSS"
24
25#include <linux/kernel.h>
26#include <linux/io.h>
27#include <linux/err.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/seq_file.h>
31#include <linux/clk.h>
32
33#include <plat/display.h>
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +000034#include <plat/clock.h>
Tomi Valkeinen559d6702009-11-03 11:23:50 +020035#include "dss.h"
36
Tomi Valkeinen559d6702009-11-03 11:23:50 +020037#define DSS_SZ_REGS SZ_512
38
39struct dss_reg {
40 u16 idx;
41};
42
43#define DSS_REG(idx) ((const struct dss_reg) { idx })
44
45#define DSS_REVISION DSS_REG(0x0000)
46#define DSS_SYSCONFIG DSS_REG(0x0010)
47#define DSS_SYSSTATUS DSS_REG(0x0014)
48#define DSS_IRQSTATUS DSS_REG(0x0018)
49#define DSS_CONTROL DSS_REG(0x0040)
50#define DSS_SDI_CONTROL DSS_REG(0x0044)
51#define DSS_PLL_CONTROL DSS_REG(0x0048)
52#define DSS_SDI_STATUS DSS_REG(0x005C)
53
54#define REG_GET(idx, start, end) \
55 FLD_GET(dss_read_reg(idx), start, end)
56
57#define REG_FLD_MOD(idx, val, start, end) \
58 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
59
60static struct {
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +000061 struct platform_device *pdev;
Tomi Valkeinen559d6702009-11-03 11:23:50 +020062 void __iomem *base;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +000063 int ctx_id;
Tomi Valkeinen559d6702009-11-03 11:23:50 +020064
65 struct clk *dpll4_m4_ck;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +000066 struct clk *dss_ick;
Archit Tanejac7642f62011-01-31 16:27:45 +000067 struct clk *dss_fck;
68 struct clk *dss_sys_clk;
69 struct clk *dss_tv_fck;
70 struct clk *dss_video_fck;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +000071 unsigned num_clks_enabled;
Tomi Valkeinen559d6702009-11-03 11:23:50 +020072
73 unsigned long cache_req_pck;
74 unsigned long cache_prate;
75 struct dss_clock_info cache_dss_cinfo;
76 struct dispc_clock_info cache_dispc_cinfo;
77
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +020078 enum dss_clk_source dsi_clk_source;
79 enum dss_clk_source dispc_clk_source;
80
Tomi Valkeinen559d6702009-11-03 11:23:50 +020081 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
Senthilvadivu Guruswamyef631f82011-02-15 23:14:00 -060082 int dss_irq;
Tomi Valkeinen559d6702009-11-03 11:23:50 +020083} dss;
84
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +000085static void dss_clk_enable_all_no_ctx(void);
86static void dss_clk_disable_all_no_ctx(void);
87static void dss_clk_enable_no_ctx(enum dss_clock clks);
88static void dss_clk_disable_no_ctx(enum dss_clock clks);
89
Tomi Valkeinen559d6702009-11-03 11:23:50 +020090static int _omap_dss_wait_reset(void);
91
92static inline void dss_write_reg(const struct dss_reg idx, u32 val)
93{
94 __raw_writel(val, dss.base + idx.idx);
95}
96
97static inline u32 dss_read_reg(const struct dss_reg idx)
98{
99 return __raw_readl(dss.base + idx.idx);
100}
101
102#define SR(reg) \
103 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
104#define RR(reg) \
105 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
106
107void dss_save_context(void)
108{
109 if (cpu_is_omap24xx())
110 return;
111
112 SR(SYSCONFIG);
113 SR(CONTROL);
114
115#ifdef CONFIG_OMAP2_DSS_SDI
116 SR(SDI_CONTROL);
117 SR(PLL_CONTROL);
118#endif
119}
120
121void dss_restore_context(void)
122{
123 if (_omap_dss_wait_reset())
124 DSSERR("DSS not coming out of reset after sleep\n");
125
126 RR(SYSCONFIG);
127 RR(CONTROL);
128
129#ifdef CONFIG_OMAP2_DSS_SDI
130 RR(SDI_CONTROL);
131 RR(PLL_CONTROL);
132#endif
133}
134
135#undef SR
136#undef RR
137
138void dss_sdi_init(u8 datapairs)
139{
140 u32 l;
141
142 BUG_ON(datapairs > 3 || datapairs < 1);
143
144 l = dss_read_reg(DSS_SDI_CONTROL);
145 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
146 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
147 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
148 dss_write_reg(DSS_SDI_CONTROL, l);
149
150 l = dss_read_reg(DSS_PLL_CONTROL);
151 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
152 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
153 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
154 dss_write_reg(DSS_PLL_CONTROL, l);
155}
156
157int dss_sdi_enable(void)
158{
159 unsigned long timeout;
160
161 dispc_pck_free_enable(1);
162
163 /* Reset SDI PLL */
164 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
165 udelay(1); /* wait 2x PCLK */
166
167 /* Lock SDI PLL */
168 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
169
170 /* Waiting for PLL lock request to complete */
171 timeout = jiffies + msecs_to_jiffies(500);
172 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
173 if (time_after_eq(jiffies, timeout)) {
174 DSSERR("PLL lock request timed out\n");
175 goto err1;
176 }
177 }
178
179 /* Clearing PLL_GO bit */
180 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
181
182 /* Waiting for PLL to lock */
183 timeout = jiffies + msecs_to_jiffies(500);
184 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
185 if (time_after_eq(jiffies, timeout)) {
186 DSSERR("PLL lock timed out\n");
187 goto err1;
188 }
189 }
190
191 dispc_lcd_enable_signal(1);
192
193 /* Waiting for SDI reset to complete */
194 timeout = jiffies + msecs_to_jiffies(500);
195 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
196 if (time_after_eq(jiffies, timeout)) {
197 DSSERR("SDI reset timed out\n");
198 goto err2;
199 }
200 }
201
202 return 0;
203
204 err2:
205 dispc_lcd_enable_signal(0);
206 err1:
207 /* Reset SDI PLL */
208 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
209
210 dispc_pck_free_enable(0);
211
212 return -ETIMEDOUT;
213}
214
215void dss_sdi_disable(void)
216{
217 dispc_lcd_enable_signal(0);
218
219 dispc_pck_free_enable(0);
220
221 /* Reset SDI PLL */
222 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
223}
224
225void dss_dump_clocks(struct seq_file *s)
226{
227 unsigned long dpll4_ck_rate;
228 unsigned long dpll4_m4_ck_rate;
229
Archit Taneja6af9cd12011-01-31 16:27:44 +0000230 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200231
232 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
233 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
234
235 seq_printf(s, "- DSS -\n");
236
237 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
238
Kishore Yac01bb72010-04-25 16:27:19 +0530239 if (cpu_is_omap3630())
240 seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
241 dpll4_ck_rate,
242 dpll4_ck_rate / dpll4_m4_ck_rate,
Archit Taneja6af9cd12011-01-31 16:27:44 +0000243 dss_clk_get_rate(DSS_CLK_FCK));
Kishore Yac01bb72010-04-25 16:27:19 +0530244 else
245 seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200246 dpll4_ck_rate,
247 dpll4_ck_rate / dpll4_m4_ck_rate,
Archit Taneja6af9cd12011-01-31 16:27:44 +0000248 dss_clk_get_rate(DSS_CLK_FCK));
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200249
Archit Taneja6af9cd12011-01-31 16:27:44 +0000250 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200251}
252
253void dss_dump_regs(struct seq_file *s)
254{
255#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
256
Archit Taneja6af9cd12011-01-31 16:27:44 +0000257 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200258
259 DUMPREG(DSS_REVISION);
260 DUMPREG(DSS_SYSCONFIG);
261 DUMPREG(DSS_SYSSTATUS);
262 DUMPREG(DSS_IRQSTATUS);
263 DUMPREG(DSS_CONTROL);
264 DUMPREG(DSS_SDI_CONTROL);
265 DUMPREG(DSS_PLL_CONTROL);
266 DUMPREG(DSS_SDI_STATUS);
267
Archit Taneja6af9cd12011-01-31 16:27:44 +0000268 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200269#undef DUMPREG
270}
271
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200272void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200273{
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200274 int b;
275
276 BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
277 clk_src != DSS_SRC_DSS1_ALWON_FCLK);
278
279 b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
280
Tomi Valkeinene406f902010-06-09 15:28:12 +0300281 if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
282 dsi_wait_dsi1_pll_active();
283
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200284 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
285
286 dss.dispc_clk_source = clk_src;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200287}
288
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200289void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200290{
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200291 int b;
292
293 BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
294 clk_src != DSS_SRC_DSS1_ALWON_FCLK);
295
296 b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
297
Tomi Valkeinene406f902010-06-09 15:28:12 +0300298 if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
299 dsi_wait_dsi2_pll_active();
300
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200301 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
302
303 dss.dsi_clk_source = clk_src;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200304}
305
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200306enum dss_clk_source dss_get_dispc_clk_source(void)
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200307{
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200308 return dss.dispc_clk_source;
309}
310
311enum dss_clk_source dss_get_dsi_clk_source(void)
312{
313 return dss.dsi_clk_source;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200314}
315
316/* calculate clock rates using dividers in cinfo */
317int dss_calc_clock_rates(struct dss_clock_info *cinfo)
318{
319 unsigned long prate;
320
Kishore Yac01bb72010-04-25 16:27:19 +0530321 if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
322 cinfo->fck_div == 0)
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200323 return -EINVAL;
324
325 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
326
327 cinfo->fck = prate / cinfo->fck_div;
328
329 return 0;
330}
331
332int dss_set_clock_div(struct dss_clock_info *cinfo)
333{
334 unsigned long prate;
335 int r;
336
337 if (cpu_is_omap34xx()) {
338 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
339 DSSDBG("dpll4_m4 = %ld\n", prate);
340
341 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
342 if (r)
343 return r;
344 }
345
346 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
347
348 return 0;
349}
350
351int dss_get_clock_div(struct dss_clock_info *cinfo)
352{
Archit Taneja6af9cd12011-01-31 16:27:44 +0000353 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200354
355 if (cpu_is_omap34xx()) {
356 unsigned long prate;
357 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
Kishore Yac01bb72010-04-25 16:27:19 +0530358 if (cpu_is_omap3630())
359 cinfo->fck_div = prate / (cinfo->fck);
360 else
361 cinfo->fck_div = prate / (cinfo->fck / 2);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200362 } else {
363 cinfo->fck_div = 0;
364 }
365
366 return 0;
367}
368
369unsigned long dss_get_dpll4_rate(void)
370{
371 if (cpu_is_omap34xx())
372 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
373 else
374 return 0;
375}
376
377int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
378 struct dss_clock_info *dss_cinfo,
379 struct dispc_clock_info *dispc_cinfo)
380{
381 unsigned long prate;
382 struct dss_clock_info best_dss;
383 struct dispc_clock_info best_dispc;
384
385 unsigned long fck;
386
387 u16 fck_div;
388
389 int match = 0;
390 int min_fck_per_pck;
391
392 prate = dss_get_dpll4_rate();
393
Archit Taneja6af9cd12011-01-31 16:27:44 +0000394 fck = dss_clk_get_rate(DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200395 if (req_pck == dss.cache_req_pck &&
396 ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
397 dss.cache_dss_cinfo.fck == fck)) {
398 DSSDBG("dispc clock info found from cache.\n");
399 *dss_cinfo = dss.cache_dss_cinfo;
400 *dispc_cinfo = dss.cache_dispc_cinfo;
401 return 0;
402 }
403
404 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
405
406 if (min_fck_per_pck &&
407 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
408 DSSERR("Requested pixel clock not possible with the current "
409 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
410 "the constraint off.\n");
411 min_fck_per_pck = 0;
412 }
413
414retry:
415 memset(&best_dss, 0, sizeof(best_dss));
416 memset(&best_dispc, 0, sizeof(best_dispc));
417
418 if (cpu_is_omap24xx()) {
419 struct dispc_clock_info cur_dispc;
420 /* XXX can we change the clock on omap2? */
Archit Taneja6af9cd12011-01-31 16:27:44 +0000421 fck = dss_clk_get_rate(DSS_CLK_FCK);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200422 fck_div = 1;
423
424 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
425 match = 1;
426
427 best_dss.fck = fck;
428 best_dss.fck_div = fck_div;
429
430 best_dispc = cur_dispc;
431
432 goto found;
433 } else if (cpu_is_omap34xx()) {
Kishore Yac01bb72010-04-25 16:27:19 +0530434 for (fck_div = (cpu_is_omap3630() ? 32 : 16);
435 fck_div > 0; --fck_div) {
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200436 struct dispc_clock_info cur_dispc;
437
Kishore Yac01bb72010-04-25 16:27:19 +0530438 if (cpu_is_omap3630())
439 fck = prate / fck_div;
440 else
441 fck = prate / fck_div * 2;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200442
443 if (fck > DISPC_MAX_FCK)
444 continue;
445
446 if (min_fck_per_pck &&
447 fck < req_pck * min_fck_per_pck)
448 continue;
449
450 match = 1;
451
452 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
453
454 if (abs(cur_dispc.pck - req_pck) <
455 abs(best_dispc.pck - req_pck)) {
456
457 best_dss.fck = fck;
458 best_dss.fck_div = fck_div;
459
460 best_dispc = cur_dispc;
461
462 if (cur_dispc.pck == req_pck)
463 goto found;
464 }
465 }
466 } else {
467 BUG();
468 }
469
470found:
471 if (!match) {
472 if (min_fck_per_pck) {
473 DSSERR("Could not find suitable clock settings.\n"
474 "Turning FCK/PCK constraint off and"
475 "trying again.\n");
476 min_fck_per_pck = 0;
477 goto retry;
478 }
479
480 DSSERR("Could not find suitable clock settings.\n");
481
482 return -EINVAL;
483 }
484
485 if (dss_cinfo)
486 *dss_cinfo = best_dss;
487 if (dispc_cinfo)
488 *dispc_cinfo = best_dispc;
489
490 dss.cache_req_pck = req_pck;
491 dss.cache_prate = prate;
492 dss.cache_dss_cinfo = best_dss;
493 dss.cache_dispc_cinfo = best_dispc;
494
495 return 0;
496}
497
498
499
500static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
501{
502 dispc_irq_handler();
503
504 return IRQ_HANDLED;
505}
506
507static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
508{
509 u32 irqstatus;
510
511 irqstatus = dss_read_reg(DSS_IRQSTATUS);
512
513 if (irqstatus & (1<<0)) /* DISPC_IRQ */
514 dispc_irq_handler();
515#ifdef CONFIG_OMAP2_DSS_DSI
516 if (irqstatus & (1<<1)) /* DSI_IRQ */
517 dsi_irq_handler();
518#endif
519
520 return IRQ_HANDLED;
521}
522
523static int _omap_dss_wait_reset(void)
524{
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200525 int t = 0;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200526
527 while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200528 if (++t > 1000) {
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200529 DSSERR("soft reset failed\n");
530 return -ENODEV;
531 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200532 udelay(1);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200533 }
534
535 return 0;
536}
537
538static int _omap_dss_reset(void)
539{
540 /* Soft reset */
541 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
542 return _omap_dss_wait_reset();
543}
544
545void dss_set_venc_output(enum omap_dss_venc_type type)
546{
547 int l = 0;
548
549 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
550 l = 0;
551 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
552 l = 1;
553 else
554 BUG();
555
556 /* venc out selection. 0 = comp, 1 = svideo */
557 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
558}
559
560void dss_set_dac_pwrdn_bgz(bool enable)
561{
562 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
563}
564
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +0000565static int dss_init(bool skip_init)
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200566{
567 int r;
568 u32 rev;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000569 struct resource *dss_mem;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200570
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000571 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
572 if (!dss_mem) {
573 DSSERR("can't get IORESOURCE_MEM DSS\n");
574 r = -EINVAL;
575 goto fail0;
576 }
577 dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200578 if (!dss.base) {
579 DSSERR("can't ioremap DSS\n");
580 r = -ENOMEM;
581 goto fail0;
582 }
583
584 if (!skip_init) {
585 /* disable LCD and DIGIT output. This seems to fix the synclost
586 * problem that we get, if the bootloader starts the DSS and
587 * the kernel resets it */
588 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
589
590 /* We need to wait here a bit, otherwise we sometimes start to
591 * get synclost errors, and after that only power cycle will
592 * restore DSS functionality. I have no idea why this happens.
593 * And we have to wait _before_ resetting the DSS, but after
594 * enabling clocks.
595 */
596 msleep(50);
597
598 _omap_dss_reset();
599 }
600
601 /* autoidle */
602 REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
603
604 /* Select DPLL */
605 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
606
607#ifdef CONFIG_OMAP2_DSS_VENC
608 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
609 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
610 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
611#endif
612
Senthilvadivu Guruswamyef631f82011-02-15 23:14:00 -0600613 dss.dss_irq = platform_get_irq(dss.pdev, 0);
614 if (dss.dss_irq < 0) {
615 DSSERR("omap2 dss: platform_get_irq failed\n");
616 r = -ENODEV;
617 goto fail1;
618 }
619
620 r = request_irq(dss.dss_irq,
621 cpu_is_omap24xx()
622 ? dss_irq_handler_omap2
623 : dss_irq_handler_omap3,
624 0, "OMAP DSS", NULL);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200625
626 if (r < 0) {
627 DSSERR("omap2 dss: request_irq failed\n");
628 goto fail1;
629 }
630
631 if (cpu_is_omap34xx()) {
632 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
633 if (IS_ERR(dss.dpll4_m4_ck)) {
634 DSSERR("Failed to get dpll4_m4_ck\n");
635 r = PTR_ERR(dss.dpll4_m4_ck);
636 goto fail2;
637 }
638 }
639
Tomi Valkeinence619e12010-03-12 12:46:05 +0200640 dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
641 dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
642
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200643 dss_save_context();
644
645 rev = dss_read_reg(DSS_REVISION);
646 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
647 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
648
649 return 0;
650
651fail2:
Senthilvadivu Guruswamyef631f82011-02-15 23:14:00 -0600652 free_irq(dss.dss_irq, NULL);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200653fail1:
654 iounmap(dss.base);
655fail0:
656 return r;
657}
658
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +0000659static void dss_exit(void)
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200660{
661 if (cpu_is_omap34xx())
662 clk_put(dss.dpll4_m4_ck);
663
Senthilvadivu Guruswamyef631f82011-02-15 23:14:00 -0600664 free_irq(dss.dss_irq, NULL);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200665
666 iounmap(dss.base);
667}
668
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000669/* CONTEXT */
670static int dss_get_ctx_id(void)
671{
672 struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
673 int r;
674
675 if (!pdata->board_data->get_last_off_on_transaction_id)
676 return 0;
677 r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
678 if (r < 0) {
679 dev_err(&dss.pdev->dev, "getting transaction ID failed, "
680 "will force context restore\n");
681 r = -1;
682 }
683 return r;
684}
685
686int dss_need_ctx_restore(void)
687{
688 int id = dss_get_ctx_id();
689
690 if (id < 0 || id != dss.ctx_id) {
691 DSSDBG("ctx id %d -> id %d\n",
692 dss.ctx_id, id);
693 dss.ctx_id = id;
694 return 1;
695 } else {
696 return 0;
697 }
698}
699
700static void save_all_ctx(void)
701{
702 DSSDBG("save context\n");
703
Archit Taneja6af9cd12011-01-31 16:27:44 +0000704 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000705
706 dss_save_context();
707 dispc_save_context();
708#ifdef CONFIG_OMAP2_DSS_DSI
709 dsi_save_context();
710#endif
711
Archit Taneja6af9cd12011-01-31 16:27:44 +0000712 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000713}
714
715static void restore_all_ctx(void)
716{
717 DSSDBG("restore context\n");
718
719 dss_clk_enable_all_no_ctx();
720
721 dss_restore_context();
722 dispc_restore_context();
723#ifdef CONFIG_OMAP2_DSS_DSI
724 dsi_restore_context();
725#endif
726
727 dss_clk_disable_all_no_ctx();
728}
729
730static int dss_get_clock(struct clk **clock, const char *clk_name)
731{
732 struct clk *clk;
733
734 clk = clk_get(&dss.pdev->dev, clk_name);
735
736 if (IS_ERR(clk)) {
737 DSSERR("can't get clock %s", clk_name);
738 return PTR_ERR(clk);
739 }
740
741 *clock = clk;
742
743 DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
744
745 return 0;
746}
747
748static int dss_get_clocks(void)
749{
750 int r;
751
752 dss.dss_ick = NULL;
Archit Tanejac7642f62011-01-31 16:27:45 +0000753 dss.dss_fck = NULL;
754 dss.dss_sys_clk = NULL;
755 dss.dss_tv_fck = NULL;
756 dss.dss_video_fck = NULL;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000757
758 r = dss_get_clock(&dss.dss_ick, "ick");
759 if (r)
760 goto err;
761
Archit Tanejac7642f62011-01-31 16:27:45 +0000762 r = dss_get_clock(&dss.dss_fck, "fck");
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000763 if (r)
764 goto err;
765
Archit Tanejac7642f62011-01-31 16:27:45 +0000766 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000767 if (r)
768 goto err;
769
Archit Tanejac7642f62011-01-31 16:27:45 +0000770 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000771 if (r)
772 goto err;
773
Archit Tanejac7642f62011-01-31 16:27:45 +0000774 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000775 if (r)
776 goto err;
777
778 return 0;
779
780err:
781 if (dss.dss_ick)
782 clk_put(dss.dss_ick);
Archit Tanejac7642f62011-01-31 16:27:45 +0000783 if (dss.dss_fck)
784 clk_put(dss.dss_fck);
785 if (dss.dss_sys_clk)
786 clk_put(dss.dss_sys_clk);
787 if (dss.dss_tv_fck)
788 clk_put(dss.dss_tv_fck);
789 if (dss.dss_video_fck)
790 clk_put(dss.dss_video_fck);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000791
792 return r;
793}
794
795static void dss_put_clocks(void)
796{
Archit Tanejac7642f62011-01-31 16:27:45 +0000797 if (dss.dss_video_fck)
798 clk_put(dss.dss_video_fck);
799 clk_put(dss.dss_tv_fck);
800 clk_put(dss.dss_fck);
801 clk_put(dss.dss_sys_clk);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000802 clk_put(dss.dss_ick);
803}
804
805unsigned long dss_clk_get_rate(enum dss_clock clk)
806{
807 switch (clk) {
808 case DSS_CLK_ICK:
809 return clk_get_rate(dss.dss_ick);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000810 case DSS_CLK_FCK:
Archit Tanejac7642f62011-01-31 16:27:45 +0000811 return clk_get_rate(dss.dss_fck);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000812 case DSS_CLK_SYSCK:
Archit Tanejac7642f62011-01-31 16:27:45 +0000813 return clk_get_rate(dss.dss_sys_clk);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000814 case DSS_CLK_TVFCK:
Archit Tanejac7642f62011-01-31 16:27:45 +0000815 return clk_get_rate(dss.dss_tv_fck);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000816 case DSS_CLK_VIDFCK:
Archit Tanejac7642f62011-01-31 16:27:45 +0000817 return clk_get_rate(dss.dss_video_fck);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000818 }
819
820 BUG();
821 return 0;
822}
823
824static unsigned count_clk_bits(enum dss_clock clks)
825{
826 unsigned num_clks = 0;
827
828 if (clks & DSS_CLK_ICK)
829 ++num_clks;
Archit Taneja6af9cd12011-01-31 16:27:44 +0000830 if (clks & DSS_CLK_FCK)
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000831 ++num_clks;
Archit Taneja6af9cd12011-01-31 16:27:44 +0000832 if (clks & DSS_CLK_SYSCK)
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000833 ++num_clks;
Archit Taneja6af9cd12011-01-31 16:27:44 +0000834 if (clks & DSS_CLK_TVFCK)
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000835 ++num_clks;
Archit Taneja6af9cd12011-01-31 16:27:44 +0000836 if (clks & DSS_CLK_VIDFCK)
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000837 ++num_clks;
838
839 return num_clks;
840}
841
842static void dss_clk_enable_no_ctx(enum dss_clock clks)
843{
844 unsigned num_clks = count_clk_bits(clks);
845
846 if (clks & DSS_CLK_ICK)
847 clk_enable(dss.dss_ick);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000848 if (clks & DSS_CLK_FCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000849 clk_enable(dss.dss_fck);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000850 if (clks & DSS_CLK_SYSCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000851 clk_enable(dss.dss_sys_clk);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000852 if (clks & DSS_CLK_TVFCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000853 clk_enable(dss.dss_tv_fck);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000854 if (clks & DSS_CLK_VIDFCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000855 clk_enable(dss.dss_video_fck);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000856
857 dss.num_clks_enabled += num_clks;
858}
859
860void dss_clk_enable(enum dss_clock clks)
861{
862 bool check_ctx = dss.num_clks_enabled == 0;
863
864 dss_clk_enable_no_ctx(clks);
865
866 if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
867 restore_all_ctx();
868}
869
870static void dss_clk_disable_no_ctx(enum dss_clock clks)
871{
872 unsigned num_clks = count_clk_bits(clks);
873
874 if (clks & DSS_CLK_ICK)
875 clk_disable(dss.dss_ick);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000876 if (clks & DSS_CLK_FCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000877 clk_disable(dss.dss_fck);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000878 if (clks & DSS_CLK_SYSCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000879 clk_disable(dss.dss_sys_clk);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000880 if (clks & DSS_CLK_TVFCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000881 clk_disable(dss.dss_tv_fck);
Archit Taneja6af9cd12011-01-31 16:27:44 +0000882 if (clks & DSS_CLK_VIDFCK)
Archit Tanejac7642f62011-01-31 16:27:45 +0000883 clk_disable(dss.dss_video_fck);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000884
885 dss.num_clks_enabled -= num_clks;
886}
887
888void dss_clk_disable(enum dss_clock clks)
889{
890 if (cpu_is_omap34xx()) {
891 unsigned num_clks = count_clk_bits(clks);
892
893 BUG_ON(dss.num_clks_enabled < num_clks);
894
895 if (dss.num_clks_enabled == num_clks)
896 save_all_ctx();
897 }
898
899 dss_clk_disable_no_ctx(clks);
900}
901
902static void dss_clk_enable_all_no_ctx(void)
903{
904 enum dss_clock clks;
905
Archit Taneja6af9cd12011-01-31 16:27:44 +0000906 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000907 if (cpu_is_omap34xx())
Archit Taneja6af9cd12011-01-31 16:27:44 +0000908 clks |= DSS_CLK_VIDFCK;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000909 dss_clk_enable_no_ctx(clks);
910}
911
912static void dss_clk_disable_all_no_ctx(void)
913{
914 enum dss_clock clks;
915
Archit Taneja6af9cd12011-01-31 16:27:44 +0000916 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000917 if (cpu_is_omap34xx())
Archit Taneja6af9cd12011-01-31 16:27:44 +0000918 clks |= DSS_CLK_VIDFCK;
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000919 dss_clk_disable_no_ctx(clks);
920}
921
922#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
923/* CLOCKS */
924static void core_dump_clocks(struct seq_file *s)
925{
926 int i;
927 struct clk *clocks[5] = {
928 dss.dss_ick,
Archit Tanejac7642f62011-01-31 16:27:45 +0000929 dss.dss_fck,
930 dss.dss_sys_clk,
931 dss.dss_tv_fck,
932 dss.dss_video_fck
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000933 };
934
935 seq_printf(s, "- CORE -\n");
936
937 seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
938
939 for (i = 0; i < 5; i++) {
940 if (!clocks[i])
941 continue;
942 seq_printf(s, "%-15s\t%lu\t%d\n",
943 clocks[i]->name,
944 clk_get_rate(clocks[i]),
945 clocks[i]->usecount);
946 }
947}
948#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
949
950/* DEBUGFS */
951#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
952void dss_debug_dump_clocks(struct seq_file *s)
953{
954 core_dump_clocks(s);
955 dss_dump_clocks(s);
956 dispc_dump_clocks(s);
957#ifdef CONFIG_OMAP2_DSS_DSI
958 dsi_dump_clocks(s);
959#endif
960}
961#endif
962
963
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +0000964/* DSS HW IP initialisation */
965static int omap_dsshw_probe(struct platform_device *pdev)
966{
967 int r;
968 int skip_init = 0;
969
970 dss.pdev = pdev;
971
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000972 r = dss_get_clocks();
973 if (r)
974 goto err_clocks;
975
976 dss_clk_enable_all_no_ctx();
977
978 dss.ctx_id = dss_get_ctx_id();
979 DSSDBG("initial ctx id %u\n", dss.ctx_id);
980
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +0000981#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
982 /* DISPC_CONTROL */
983 if (omap_readl(0x48050440) & 1) /* LCD enabled? */
984 skip_init = 1;
985#endif
986
987 r = dss_init(skip_init);
988 if (r) {
989 DSSERR("Failed to initialize DSS\n");
990 goto err_dss;
991 }
992
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000993 dss_clk_disable_all_no_ctx();
994 return 0;
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +0000995
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000996err_dss:
997 dss_clk_disable_all_no_ctx();
998 dss_put_clocks();
999err_clocks:
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +00001000 return r;
1001}
1002
1003static int omap_dsshw_remove(struct platform_device *pdev)
1004{
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +00001005
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +00001006 dss_exit();
1007
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +00001008 /*
1009 * As part of hwmod changes, DSS is not the only controller of dss
1010 * clocks; hwmod framework itself will also enable clocks during hwmod
1011 * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
1012 * need to disable clocks if their usecounts > 1.
1013 */
1014 WARN_ON(dss.num_clks_enabled > 0);
1015
1016 dss_put_clocks();
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +00001017 return 0;
1018}
1019
1020static struct platform_driver omap_dsshw_driver = {
1021 .probe = omap_dsshw_probe,
1022 .remove = omap_dsshw_remove,
1023 .driver = {
1024 .name = "omapdss_dss",
1025 .owner = THIS_MODULE,
1026 },
1027};
1028
1029int dss_init_platform_driver(void)
1030{
1031 return platform_driver_register(&omap_dsshw_driver);
1032}
1033
1034void dss_uninit_platform_driver(void)
1035{
1036 return platform_driver_unregister(&omap_dsshw_driver);
1037}