blob: 54826b805b91ae3ddbcf3b9e9af8e3ee9f68227a [file] [log] [blame]
Erik Gillingc5f80062010-01-21 16:53:02 -08001/*
2 * arch/arm/mach-tegra/board-harmony.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/io.h>
Colin Cross4de3a8f2010-04-05 13:16:42 -070022#include <linux/clk.h>
23#include <linux/delay.h>
Erik Gillingc5f80062010-01-21 16:53:02 -080024
25#include <asm/hardware/cache-l2x0.h>
26
27#include <mach/iomap.h>
Colin Cross4de3a8f2010-04-05 13:16:42 -070028#include <mach/dma.h>
Colin Cross699fe142010-08-23 18:37:25 -070029#include <mach/system.h>
Erik Gillingc5f80062010-01-21 16:53:02 -080030
31#include "board.h"
Colin Crossd8611962010-01-28 16:40:29 -080032#include "clock.h"
Colin Cross73625e32010-06-23 15:49:17 -070033#include "fuse.h"
Colin Crossd8611962010-01-28 16:40:29 -080034
Colin Cross699fe142010-08-23 18:37:25 -070035void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
36
37void tegra_assert_system_reset(char mode, const char *cmd)
38{
39 void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
40 u32 reg;
41
Simon Glass375b19c2011-02-17 08:13:57 -080042 /* use *_related to avoid spinlock since caches are off */
43 reg = readl_relaxed(reset);
Colin Cross699fe142010-08-23 18:37:25 -070044 reg |= 0x04;
Simon Glass375b19c2011-02-17 08:13:57 -080045 writel_relaxed(reg, reset);
Colin Cross699fe142010-08-23 18:37:25 -070046}
47
Colin Crossd8611962010-01-28 16:40:29 -080048static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
49 /* name parent rate enabled */
50 { "clk_m", NULL, 0, true },
51 { "pll_p", "clk_m", 216000000, true },
52 { "pll_p_out1", "pll_p", 28800000, true },
53 { "pll_p_out2", "pll_p", 48000000, true },
54 { "pll_p_out3", "pll_p", 72000000, true },
55 { "pll_p_out4", "pll_p", 108000000, true },
Colin Cross8486bdd2010-06-24 18:57:00 -070056 { "sclk", "pll_p_out4", 108000000, true },
57 { "hclk", "sclk", 108000000, true },
Colin Crossd8611962010-01-28 16:40:29 -080058 { "pclk", "hclk", 54000000, true },
59 { NULL, NULL, 0, 0},
60};
Erik Gillingc5f80062010-01-21 16:53:02 -080061
62void __init tegra_init_cache(void)
63{
64#ifdef CONFIG_CACHE_L2X0
65 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
66
Colin Cross535371c2011-01-22 00:36:14 -080067 writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
68 writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
Erik Gillingc5f80062010-01-21 16:53:02 -080069
70 l2x0_init(p, 0x6C080001, 0x8200c3fe);
71#endif
Colin Cross4de3a8f2010-04-05 13:16:42 -070072
Erik Gillingc5f80062010-01-21 16:53:02 -080073}
74
75void __init tegra_common_init(void)
76{
Colin Cross73625e32010-06-23 15:49:17 -070077 tegra_init_fuse();
Colin Crossd8611962010-01-28 16:40:29 -080078 tegra_init_clock();
79 tegra_clk_init_from_table(common_clk_init_table);
Erik Gillingc5f80062010-01-21 16:53:02 -080080 tegra_init_cache();
Colin Cross4de3a8f2010-04-05 13:16:42 -070081#ifdef CONFIG_TEGRA_SYSTEM_DMA
82 tegra_dma_init();
83#endif
Erik Gillingc5f80062010-01-21 16:53:02 -080084}