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review.evervolv.com / android_kernel_oneplus_msm8996 / 380e04ac2cd96a4c36ad164fce556427dcd2ea0f / . / arch / arm / boot / dts / tegra20.dtsi
blob: 63c25cefaad7442344c377bc2a37c06fc2e22792 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]94 cache-controller@50043000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x50043000 0x1000>;
97 arm,data-latency = <5 5 2>;
98 arm,tag-latency = <4 4 2>;
99 cache-unified;
100 cache-level = <2>;
101 };
102
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]103 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]104 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]105 reg = <0x50041000 0x1000
106 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]107 interrupt-controller;
108 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]109 };
110
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]111 timer@60005000 {
112 compatible = "nvidia,tegra20-timer";
113 reg = <0x60005000 0x60>;
114 interrupts = <0 0 0x04
115 0 1 0x04
116 0 41 0x04
117 0 42 0x04>;
118 };
119
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]120 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]121 compatible = "nvidia,tegra20-apbdma";
122 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]123 interrupts = <0 104 0x04
124 0 105 0x04
125 0 106 0x04
126 0 107 0x04
127 0 108 0x04
128 0 109 0x04
129 0 110 0x04
130 0 111 0x04
131 0 112 0x04
132 0 113 0x04
133 0 114 0x04
134 0 115 0x04
135 0 116 0x04
136 0 117 0x04
137 0 118 0x04
138 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]139 };
140
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]141 ahb {
142 compatible = "nvidia,tegra20-ahb";
143 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]144 };
145
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]146 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]147 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]148 reg = <0x6000d000 0x1000>;
149 interrupts = <0 32 0x04
150 0 33 0x04
151 0 34 0x04
152 0 35 0x04
153 0 55 0x04
154 0 87 0x04
155 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]156 #gpio-cells = <2>;
157 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]158 #interrupt-cells = <2>;
159 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]160 };
161
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]162 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]163 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]164 reg = <0x70000014 0x10 /* Tri-state registers */
165 0x70000080 0x20 /* Mux registers */
166 0x700000a0 0x14 /* Pull-up/down registers */
167 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]168 };
169
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]170 das {
171 compatible = "nvidia,tegra20-das";
172 reg = <0x70000c00 0x80>;
173 };
174
175 tegra_i2s1: i2s@70002800 {
176 compatible = "nvidia,tegra20-i2s";
177 reg = <0x70002800 0x200>;
178 interrupts = <0 13 0x04>;
179 nvidia,dma-request-selector = <&apbdma 2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]180 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]181 };
182
183 tegra_i2s2: i2s@70002a00 {
184 compatible = "nvidia,tegra20-i2s";
185 reg = <0x70002a00 0x200>;
186 interrupts = <0 3 0x04>;
187 nvidia,dma-request-selector = <&apbdma 1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]188 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]189 };
190
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]191 serial@70006000 {
192 compatible = "nvidia,tegra20-uart";
193 reg = <0x70006000 0x40>;
194 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]195 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]196 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]197 };
198
199 serial@70006040 {
200 compatible = "nvidia,tegra20-uart";
201 reg = <0x70006040 0x40>;
202 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]203 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]204 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]205 };
206
207 serial@70006200 {
208 compatible = "nvidia,tegra20-uart";
209 reg = <0x70006200 0x100>;
210 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]211 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]212 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]213 };
214
215 serial@70006300 {
216 compatible = "nvidia,tegra20-uart";
217 reg = <0x70006300 0x100>;
218 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]219 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]220 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]221 };
222
223 serial@70006400 {
224 compatible = "nvidia,tegra20-uart";
225 reg = <0x70006400 0x100>;
226 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]227 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]228 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]229 };
230
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]231 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]232 compatible = "nvidia,tegra20-pwm";
233 reg = <0x7000a000 0x100>;
234 #pwm-cells = <2>;
235 };
236
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame^]237 rtc {
238 compatible = "nvidia,tegra20-rtc";
239 reg = <0x7000e000 0x100>;
240 interrupts = <0 2 0x04>;
241 };
242
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]243 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]244 compatible = "nvidia,tegra20-i2c";
245 reg = <0x7000c000 0x100>;
246 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]247 #address-cells = <1>;
248 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]249 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]250 };
251
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]252 spi@7000c380 {
253 compatible = "nvidia,tegra20-sflash";
254 reg = <0x7000c380 0x80>;
255 interrupts = <0 39 0x04>;
256 nvidia,dma-request-selector = <&apbdma 11>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 status = "disabled";
260 };
261
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]262 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]263 compatible = "nvidia,tegra20-i2c";
264 reg = <0x7000c400 0x100>;
265 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]266 #address-cells = <1>;
267 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]268 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]269 };
270
271 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]272 compatible = "nvidia,tegra20-i2c";
273 reg = <0x7000c500 0x100>;
274 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]275 #address-cells = <1>;
276 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]277 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]278 };
279
280 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]281 compatible = "nvidia,tegra20-i2c-dvc";
282 reg = <0x7000d000 0x200>;
283 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]284 #address-cells = <1>;
285 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]286 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]287 };
288
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]289 spi@7000d400 {
290 compatible = "nvidia,tegra20-slink";
291 reg = <0x7000d400 0x200>;
292 interrupts = <0 59 0x04>;
293 nvidia,dma-request-selector = <&apbdma 15>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 status = "disabled";
297 };
298
299 spi@7000d600 {
300 compatible = "nvidia,tegra20-slink";
301 reg = <0x7000d600 0x200>;
302 interrupts = <0 82 0x04>;
303 nvidia,dma-request-selector = <&apbdma 16>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 status = "disabled";
307 };
308
309 spi@7000d800 {
310 compatible = "nvidia,tegra20-slink";
311 reg = <0x7000d480 0x200>;
312 interrupts = <0 83 0x04>;
313 nvidia,dma-request-selector = <&apbdma 17>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318
319 spi@7000da00 {
320 compatible = "nvidia,tegra20-slink";
321 reg = <0x7000da00 0x200>;
322 interrupts = <0 93 0x04>;
323 nvidia,dma-request-selector = <&apbdma 18>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
328
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]329 pmc {
330 compatible = "nvidia,tegra20-pmc";
331 reg = <0x7000e400 0x400>;
332 };
333
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]334 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]335 compatible = "nvidia,tegra20-mc";
336 reg = <0x7000f000 0x024
337 0x7000f03c 0x3c4>;
338 interrupts = <0 77 0x04>;
339 };
340
341 gart {
342 compatible = "nvidia,tegra20-gart";
343 reg = <0x7000f024 0x00000018 /* controller registers */
344 0x58000000 0x02000000>; /* GART aperture */
345 };
346
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]347 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]348 compatible = "nvidia,tegra20-emc";
349 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]350 #address-cells = <1>;
351 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]352 };
353
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]354 usb@c5000000 {
355 compatible = "nvidia,tegra20-ehci", "usb-ehci";
356 reg = <0xc5000000 0x4000>;
357 interrupts = <0 20 0x04>;
358 phy_type = "utmi";
359 nvidia,has-legacy-mode;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]360 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]361 };
362
363 usb@c5004000 {
364 compatible = "nvidia,tegra20-ehci", "usb-ehci";
365 reg = <0xc5004000 0x4000>;
366 interrupts = <0 21 0x04>;
367 phy_type = "ulpi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]368 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]369 };
370
371 usb@c5008000 {
372 compatible = "nvidia,tegra20-ehci", "usb-ehci";
373 reg = <0xc5008000 0x4000>;
374 interrupts = <0 97 0x04>;
375 phy_type = "utmi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]376 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]377 };
378
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]379 sdhci@c8000000 {
380 compatible = "nvidia,tegra20-sdhci";
381 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]382 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]383 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]384 };
385
386 sdhci@c8000200 {
387 compatible = "nvidia,tegra20-sdhci";
388 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]389 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]390 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]391 };
392
393 sdhci@c8000400 {
394 compatible = "nvidia,tegra20-sdhci";
395 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]396 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]397 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]398 };
399
400 sdhci@c8000600 {
401 compatible = "nvidia,tegra20-sdhci";
402 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]403 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]404 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]405 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]406
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]407 pmu {
408 compatible = "arm,cortex-a9-pmu";
409 interrupts = <0 56 0x04
410 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]411 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]412};