Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 380e04ac2cd96a4c36ad164fce556427dcd2ea0f / . / arch / arm / boot / dts / tegra30.dtsi
blob: f7af06621cc8920a6db47c7462d16d92bc38ae91 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]94 cache-controller@50043000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x50043000 0x1000>;
97 arm,data-latency = <6 6 2>;
98 arm,tag-latency = <5 5 2>;
99 cache-unified;
100 cache-level = <2>;
101 };
102
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]103 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]104 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]105 reg = <0x50041000 0x1000
106 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]107 interrupt-controller;
108 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]109 };
110
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]111 timer@60005000 {
112 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
113 reg = <0x60005000 0x400>;
114 interrupts = <0 0 0x04
115 0 1 0x04
116 0 41 0x04
117 0 42 0x04
118 0 121 0x04
119 0 122 0x04>;
120 };
121
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]122 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]123 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
124 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]125 interrupts = <0 104 0x04
126 0 105 0x04
127 0 106 0x04
128 0 107 0x04
129 0 108 0x04
130 0 109 0x04
131 0 110 0x04
132 0 111 0x04
133 0 112 0x04
134 0 113 0x04
135 0 114 0x04
136 0 115 0x04
137 0 116 0x04
138 0 117 0x04
139 0 118 0x04
140 0 119 0x04
141 0 128 0x04
142 0 129 0x04
143 0 130 0x04
144 0 131 0x04
145 0 132 0x04
146 0 133 0x04
147 0 134 0x04
148 0 135 0x04
149 0 136 0x04
150 0 137 0x04
151 0 138 0x04
152 0 139 0x04
153 0 140 0x04
154 0 141 0x04
155 0 142 0x04
156 0 143 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]157 };
158
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]159 ahb: ahb {
160 compatible = "nvidia,tegra30-ahb";
161 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
162 };
163
164 gpio: gpio {
165 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
166 reg = <0x6000d000 0x1000>;
167 interrupts = <0 32 0x04
168 0 33 0x04
169 0 34 0x04
170 0 35 0x04
171 0 55 0x04
172 0 87 0x04
173 0 89 0x04
174 0 125 0x04>;
175 #gpio-cells = <2>;
176 gpio-controller;
177 #interrupt-cells = <2>;
178 interrupt-controller;
179 };
180
181 pinmux: pinmux {
182 compatible = "nvidia,tegra30-pinmux";
183 reg = <0x70000868 0xd0 /* Pad control registers */
184 0x70003000 0x3e0>; /* Mux registers */
185 };
186
187 serial@70006000 {
188 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
189 reg = <0x70006000 0x40>;
190 reg-shift = <2>;
191 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]192 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]193 };
194
195 serial@70006040 {
196 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
197 reg = <0x70006040 0x40>;
198 reg-shift = <2>;
199 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]200 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]201 };
202
203 serial@70006200 {
204 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
205 reg = <0x70006200 0x100>;
206 reg-shift = <2>;
207 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]208 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]209 };
210
211 serial@70006300 {
212 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
213 reg = <0x70006300 0x100>;
214 reg-shift = <2>;
215 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]216 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]217 };
218
219 serial@70006400 {
220 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
221 reg = <0x70006400 0x100>;
222 reg-shift = <2>;
223 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]224 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]225 };
226
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]227 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]228 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
229 reg = <0x7000a000 0x100>;
230 #pwm-cells = <2>;
231 };
232
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame^]233 rtc {
234 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
235 reg = <0x7000e000 0x100>;
236 interrupts = <0 2 0x04>;
237 };
238
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]239 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]240 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]241 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]242 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]243 #address-cells = <1>;
244 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]245 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]246 };
247
248 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]249 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]250 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]251 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]252 #address-cells = <1>;
253 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]254 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]255 };
256
257 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]258 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]259 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]260 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]261 #address-cells = <1>;
262 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]263 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]264 };
265
266 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]267 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
268 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]269 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]270 #address-cells = <1>;
271 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]272 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]273 };
274
275 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]276 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]277 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]278 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]279 #address-cells = <1>;
280 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]281 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]282 };
283
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]284 spi@7000d400 {
285 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
286 reg = <0x7000d400 0x200>;
287 interrupts = <0 59 0x04>;
288 nvidia,dma-request-selector = <&apbdma 15>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 status = "disabled";
292 };
293
294 spi@7000d600 {
295 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
296 reg = <0x7000d600 0x200>;
297 interrupts = <0 82 0x04>;
298 nvidia,dma-request-selector = <&apbdma 16>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
303
304 spi@7000d800 {
305 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
306 reg = <0x7000d480 0x200>;
307 interrupts = <0 83 0x04>;
308 nvidia,dma-request-selector = <&apbdma 17>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
314 spi@7000da00 {
315 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
316 reg = <0x7000da00 0x200>;
317 interrupts = <0 93 0x04>;
318 nvidia,dma-request-selector = <&apbdma 18>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 status = "disabled";
322 };
323
324 spi@7000dc00 {
325 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
326 reg = <0x7000dc00 0x200>;
327 interrupts = <0 94 0x04>;
328 nvidia,dma-request-selector = <&apbdma 27>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 status = "disabled";
332 };
333
334 spi@7000de00 {
335 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
336 reg = <0x7000de00 0x200>;
337 interrupts = <0 79 0x04>;
338 nvidia,dma-request-selector = <&apbdma 28>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]344 pmc {
345 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
346 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]347 };
348
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]349 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]350 compatible = "nvidia,tegra30-mc";
351 reg = <0x7000f000 0x010
352 0x7000f03c 0x1b4
353 0x7000f200 0x028
354 0x7000f284 0x17c>;
355 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]356 };
357
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]358 smmu {
359 compatible = "nvidia,tegra30-smmu";
360 reg = <0x7000f010 0x02c
361 0x7000f1f0 0x010
362 0x7000f228 0x05c>;
363 nvidia,#asids = <4>; /* # of ASIDs */
364 dma-window = <0 0x40000000>; /* IOVA start & length */
365 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]366 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]367
368 ahub {
369 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]370 reg = <0x70080000 0x200
371 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]372 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]373 nvidia,dma-request-selector = <&apbdma 1>;
374
375 ranges;
376 #address-cells = <1>;
377 #size-cells = <1>;
378
379 tegra_i2s0: i2s@70080300 {
380 compatible = "nvidia,tegra30-i2s";
381 reg = <0x70080300 0x100>;
382 nvidia,ahub-cif-ids = <4 4>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]383 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]384 };
385
386 tegra_i2s1: i2s@70080400 {
387 compatible = "nvidia,tegra30-i2s";
388 reg = <0x70080400 0x100>;
389 nvidia,ahub-cif-ids = <5 5>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]390 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]391 };
392
393 tegra_i2s2: i2s@70080500 {
394 compatible = "nvidia,tegra30-i2s";
395 reg = <0x70080500 0x100>;
396 nvidia,ahub-cif-ids = <6 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]397 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]398 };
399
400 tegra_i2s3: i2s@70080600 {
401 compatible = "nvidia,tegra30-i2s";
402 reg = <0x70080600 0x100>;
403 nvidia,ahub-cif-ids = <7 7>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]404 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]405 };
406
407 tegra_i2s4: i2s@70080700 {
408 compatible = "nvidia,tegra30-i2s";
409 reg = <0x70080700 0x100>;
410 nvidia,ahub-cif-ids = <8 8>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]411 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]412 };
413 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]414
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]415 sdhci@78000000 {
416 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
417 reg = <0x78000000 0x200>;
418 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]419 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]420 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]421
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]422 sdhci@78000200 {
423 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
424 reg = <0x78000200 0x200>;
425 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]426 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]427 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]428
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]429 sdhci@78000400 {
430 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
431 reg = <0x78000400 0x200>;
432 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]433 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]434 };
435
436 sdhci@78000600 {
437 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
438 reg = <0x78000600 0x200>;
439 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]440 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]441 };
442
443 pmu {
444 compatible = "arm,cortex-a9-pmu";
445 interrupts = <0 144 0x04
446 0 145 0x04
447 0 146 0x04
448 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]449 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]450};