Kumar Gala | b053dc5 | 2009-06-19 08:31:05 -0500 | [diff] [blame] | 1 | Specifying GPIO information for devices |
| 2 | ============================================ |
| 3 | |
| 4 | 1) gpios property |
| 5 | ----------------- |
| 6 | |
| 7 | Nodes that makes use of GPIOs should define them using `gpios' property, |
| 8 | format of which is: <&gpio-controller1-phandle gpio1-specifier |
| 9 | &gpio-controller2-phandle gpio2-specifier |
| 10 | 0 /* holes are permitted, means no GPIO 3 */ |
| 11 | &gpio-controller4-phandle gpio4-specifier |
| 12 | ...>; |
| 13 | |
| 14 | Note that gpio-specifier length is controller dependent. |
| 15 | |
| 16 | gpio-specifier may encode: bank, pin position inside the bank, |
| 17 | whether pin is open-drain and whether pin is logically inverted. |
| 18 | |
| 19 | Example of the node using GPIOs: |
| 20 | |
| 21 | node { |
| 22 | gpios = <&qe_pio_e 18 0>; |
| 23 | }; |
| 24 | |
| 25 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, |
| 26 | and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. |
| 27 | |
| 28 | 2) gpio-controller nodes |
| 29 | ------------------------ |
| 30 | |
| 31 | Every GPIO controller node must have #gpio-cells property defined, |
| 32 | this information will be used to translate gpio-specifiers. |
| 33 | |
| 34 | Example of two SOC GPIO banks defined as gpio-controller nodes: |
| 35 | |
| 36 | qe_pio_a: gpio-controller@1400 { |
| 37 | #gpio-cells = <2>; |
| 38 | compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; |
| 39 | reg = <0x1400 0x18>; |
| 40 | gpio-controller; |
| 41 | }; |
| 42 | |
| 43 | qe_pio_e: gpio-controller@1460 { |
| 44 | #gpio-cells = <2>; |
| 45 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; |
| 46 | reg = <0x1460 0x18>; |
| 47 | gpio-controller; |
| 48 | }; |
| 49 | |
| 50 | |