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review.evervolv.com / android_kernel_oneplus_msm8996 / 3c4cfadef6a1665d9cd02a543782d03d3e6740c6 / . / arch / powerpc / kvm / bookehv_interrupts.S
blob: 1685dc43bcf286615b246eb83f163a3a183bb2c3 [file] [log] [blame]
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
16 *
17 * Author: Varun Sethi <varun.sethi@freescale.com>
18 * Author: Scott Wood <scotwood@freescale.com>
19 *
20 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/mmu-44x.h>
27#include <asm/page.h>
28#include <asm/asm-compat.h>
29#include <asm/asm-offsets.h>
30#include <asm/bitsperlong.h>
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]31#include <asm/thread_info.h>
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]32
33#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
34
35#define GET_VCPU(vcpu, thread) \
36 PPC_LL vcpu, THREAD_KVM_VCPU(thread)
37
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]38#define LONGBYTES (BITS_PER_LONG / 8)
39
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]40#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
41
42/* The host stack layout: */
43#define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */
44#define HOST_CALLEE_LR (1 * LONGBYTES)
45#define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */
46/*
47 * r2 is special: it holds 'current', and it made nonvolatile in the
48 * kernel with the -ffixed-r2 gcc option.
49 */
50#define HOST_R2 (3 * LONGBYTES)
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]51#define HOST_CR (4 * LONGBYTES)
52#define HOST_NV_GPRS (5 * LONGBYTES)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]53#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
54#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
55#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
56#define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
57
58#define NEED_EMU 0x00000001 /* emulation -- save nv regs */
59#define NEED_DEAR 0x00000002 /* save faulting DEAR */
60#define NEED_ESR 0x00000004 /* save faulting ESR */
61
62/*
63 * On entry:
64 * r4 = vcpu, r5 = srr0, r6 = srr1
65 * saved in vcpu: cr, ctr, r3-r13
66 */
67.macro kvm_handler_common intno, srr0, flags
Alexander Grafa2723ce2012-02-15 23:06:24 +0000[diff] [blame]68 /* Restore host stack pointer */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]69 PPC_STL r1, VCPU_GPR(R1)(r4)
70 PPC_STL r2, VCPU_GPR(R2)(r4)
Alexander Grafa2723ce2012-02-15 23:06:24 +0000[diff] [blame]71 PPC_LL r1, VCPU_HOST_STACK(r4)
72 PPC_LL r2, HOST_R2(r1)
73
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]74 mfspr r10, SPRN_PID
75 lwz r8, VCPU_HOST_PID(r4)
76 PPC_LL r11, VCPU_SHARED(r4)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]77 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]78 li r14, \intno
79
80 stw r10, VCPU_GUEST_PID(r4)
81 mtspr SPRN_PID, r8
82
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]83#ifdef CONFIG_KVM_EXIT_TIMING
84 /* save exit time */
851: mfspr r7, SPRN_TBRU
86 mfspr r8, SPRN_TBRL
87 mfspr r9, SPRN_TBRU
88 cmpw r9, r7
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]89 stw r8, VCPU_TIMING_EXIT_TBL(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]90 bne- 1b
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]91 stw r9, VCPU_TIMING_EXIT_TBU(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]92#endif
93
94 oris r8, r6, MSR_CE@h
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]95 PPC_STD(r6, VCPU_SHARED_MSR, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]96 ori r8, r8, MSR_ME | MSR_RI
97 PPC_STL r5, VCPU_PC(r4)
98
99 /*
100 * Make sure CE/ME/RI are set (if appropriate for exception type)
101 * whether or not the guest had it set. Since mfmsr/mtmsr are
102 * somewhat expensive, skip in the common case where the guest
103 * had all these bits set (and thus they're still set if
104 * appropriate for the exception type).
105 */
106 cmpw r6, r8
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]107 beq 1f
108 mfmsr r7
109 .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
110 oris r7, r7, MSR_CE@h
111 .endif
112 .if \srr0 != SPRN_MCSRR0
113 ori r7, r7, MSR_ME | MSR_RI
114 .endif
115 mtmsr r7
1161:
117
118 .if \flags & NEED_EMU
119 /*
120 * This assumes you have external PID support.
121 * To support a bookehv CPU without external PID, you'll
122 * need to look up the TLB entry and create a temporary mapping.
123 *
124 * FIXME: we don't currently handle if the lwepx faults. PR-mode
125 * booke doesn't handle it either. Since Linux doesn't use
126 * broadcast tlbivax anymore, the only way this should happen is
127 * if the guest maps its memory execute-but-not-read, or if we
128 * somehow take a TLB miss in the middle of this entry code and
129 * evict the relevant entry. On e500mc, all kernel lowmem is
130 * bolted into TLB1 large page mappings, and we don't use
131 * broadcast invalidates, so we should not take a TLB miss here.
132 *
133 * Later we'll need to deal with faults here. Disallowing guest
134 * mappings that are execute-but-not-read could be an option on
135 * e500mc, but not on chips with an LRAT if it is used.
136 */
137
138 mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]139 PPC_STL r15, VCPU_GPR(R15)(r4)
140 PPC_STL r16, VCPU_GPR(R16)(r4)
141 PPC_STL r17, VCPU_GPR(R17)(r4)
142 PPC_STL r18, VCPU_GPR(R18)(r4)
143 PPC_STL r19, VCPU_GPR(R19)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]144 mr r8, r3
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]145 PPC_STL r20, VCPU_GPR(R20)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]146 rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]147 PPC_STL r21, VCPU_GPR(R21)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]148 rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]149 PPC_STL r22, VCPU_GPR(R22)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]150 rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]151 PPC_STL r23, VCPU_GPR(R23)(r4)
152 PPC_STL r24, VCPU_GPR(R24)(r4)
153 PPC_STL r25, VCPU_GPR(R25)(r4)
154 PPC_STL r26, VCPU_GPR(R26)(r4)
155 PPC_STL r27, VCPU_GPR(R27)(r4)
156 PPC_STL r28, VCPU_GPR(R28)(r4)
157 PPC_STL r29, VCPU_GPR(R29)(r4)
158 PPC_STL r30, VCPU_GPR(R30)(r4)
159 PPC_STL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]160 mtspr SPRN_EPLC, r8
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]161
162 /* disable preemption, so we are sure we hit the fixup handler */
Stuart Yoder9778b692012-07-05 04:41:35 +0000[diff] [blame]163 CURRENT_THREAD_INFO(r8, r1)
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]164 li r7, 1
165 stw r7, TI_PREEMPT(r8)
166
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]167 isync
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]168
169 /*
170 * In case the read goes wrong, we catch it and write an invalid value
171 * in LAST_INST instead.
172 */
1731: lwepx r9, 0, r5
1742:
175.section .fixup, "ax"
1763: li r9, KVM_INST_FETCH_FAILED
177 b 2b
178.previous
179.section __ex_table,"a"
180 PPC_LONG_ALIGN
181 PPC_LONG 1b,3b
182.previous
183
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]184 mtspr SPRN_EPLC, r3
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]185 li r7, 0
186 stw r7, TI_PREEMPT(r8)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]187 stw r9, VCPU_LAST_INST(r4)
188 .endif
189
190 .if \flags & NEED_ESR
191 mfspr r8, SPRN_ESR
192 PPC_STL r8, VCPU_FAULT_ESR(r4)
193 .endif
194
195 .if \flags & NEED_DEAR
196 mfspr r9, SPRN_DEAR
197 PPC_STL r9, VCPU_FAULT_DEAR(r4)
198 .endif
199
200 b kvmppc_resume_host
201.endm
202
203/*
204 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
205 */
206.macro kvm_handler intno srr0, srr1, flags
207_GLOBAL(kvmppc_handler_\intno\()_\srr1)
208 GET_VCPU(r11, r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]209 PPC_STL r3, VCPU_GPR(R3)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]210 mfspr r3, SPRN_SPRG_RSCRATCH0
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]211 PPC_STL r4, VCPU_GPR(R4)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]212 PPC_LL r4, THREAD_NORMSAVE(0)(r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]213 PPC_STL r5, VCPU_GPR(R5)(r11)
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]214 stw r13, VCPU_CR(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]215 mfspr r5, \srr0
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]216 PPC_STL r3, VCPU_GPR(R10)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]217 PPC_LL r3, THREAD_NORMSAVE(2)(r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]218 PPC_STL r6, VCPU_GPR(R6)(r11)
219 PPC_STL r4, VCPU_GPR(R11)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]220 mfspr r6, \srr1
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]221 PPC_STL r7, VCPU_GPR(R7)(r11)
222 PPC_STL r8, VCPU_GPR(R8)(r11)
223 PPC_STL r9, VCPU_GPR(R9)(r11)
224 PPC_STL r3, VCPU_GPR(R13)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]225 mfctr r7
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]226 PPC_STL r12, VCPU_GPR(R12)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]227 PPC_STL r7, VCPU_CTR(r11)
228 mr r4, r11
229 kvm_handler_common \intno, \srr0, \flags
230.endm
231
232.macro kvm_lvl_handler intno scratch srr0, srr1, flags
233_GLOBAL(kvmppc_handler_\intno\()_\srr1)
234 mfspr r10, SPRN_SPRG_THREAD
235 GET_VCPU(r11, r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]236 PPC_STL r3, VCPU_GPR(R3)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]237 mfspr r3, \scratch
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]238 PPC_STL r4, VCPU_GPR(R4)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]239 PPC_LL r4, GPR9(r8)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]240 PPC_STL r5, VCPU_GPR(R5)(r11)
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]241 stw r9, VCPU_CR(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]242 mfspr r5, \srr0
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]243 PPC_STL r3, VCPU_GPR(R8)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]244 PPC_LL r3, GPR10(r8)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]245 PPC_STL r6, VCPU_GPR(R6)(r11)
246 PPC_STL r4, VCPU_GPR(R9)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]247 mfspr r6, \srr1
248 PPC_LL r4, GPR11(r8)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]249 PPC_STL r7, VCPU_GPR(R7)(r11)
250 PPC_STL r3, VCPU_GPR(R10)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]251 mfctr r7
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]252 PPC_STL r12, VCPU_GPR(R12)(r11)
253 PPC_STL r13, VCPU_GPR(R13)(r11)
254 PPC_STL r4, VCPU_GPR(R11)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]255 PPC_STL r7, VCPU_CTR(r11)
256 mr r4, r11
257 kvm_handler_common \intno, \srr0, \flags
258.endm
259
260kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
261 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
262kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
263 SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
264kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
265 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
266kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
267kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
268kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
269 SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
270kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
271kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
272kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
273kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
274kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
275kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
276kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
277 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
278kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
279 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
280kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
281kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
282kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
283kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
284kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
285kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
286kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
287 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
288kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
289kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
290kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
291kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
292 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
293kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
294 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
295kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
296 SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
297
298
299/* Registers:
300 * SPRG_SCRATCH0: guest r10
301 * r4: vcpu pointer
302 * r11: vcpu->arch.shared
303 * r14: KVM exit number
304 */
305_GLOBAL(kvmppc_resume_host)
306 /* Save remaining volatile guest register state to vcpu. */
307 mfspr r3, SPRN_VRSAVE
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]308 PPC_STL r0, VCPU_GPR(R0)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]309 mflr r5
310 mfspr r6, SPRN_SPRG4
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]311 PPC_STL r5, VCPU_LR(r4)
312 mfspr r7, SPRN_SPRG5
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]313 stw r3, VCPU_VRSAVE(r4)
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]314 PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]315 mfspr r8, SPRN_SPRG6
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]316 PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]317 mfspr r9, SPRN_SPRG7
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]318 PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]319 mfxer r3
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]320 PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]321
322 /* save guest MAS registers and restore host mas4 & mas6 */
323 mfspr r5, SPRN_MAS0
324 PPC_STL r3, VCPU_XER(r4)
325 mfspr r6, SPRN_MAS1
326 stw r5, VCPU_SHARED_MAS0(r11)
327 mfspr r7, SPRN_MAS2
328 stw r6, VCPU_SHARED_MAS1(r11)
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]329 PPC_STD(r7, VCPU_SHARED_MAS2, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]330 mfspr r5, SPRN_MAS3
331 mfspr r6, SPRN_MAS4
332 stw r5, VCPU_SHARED_MAS7_3+4(r11)
333 mfspr r7, SPRN_MAS6
334 stw r6, VCPU_SHARED_MAS4(r11)
335 mfspr r5, SPRN_MAS7
336 lwz r6, VCPU_HOST_MAS4(r4)
337 stw r7, VCPU_SHARED_MAS6(r11)
338 lwz r8, VCPU_HOST_MAS6(r4)
339 mtspr SPRN_MAS4, r6
340 stw r5, VCPU_SHARED_MAS7_3+0(r11)
341 mtspr SPRN_MAS6, r8
Alexander Grafe9ba39c2012-02-16 14:53:04 +0000[diff] [blame]342 /* Enable MAS register updates via exception */
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]343 mfspr r3, SPRN_EPCR
344 rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
345 mtspr SPRN_EPCR, r3
346 isync
347
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]348 /* Switch to kernel stack and jump to handler. */
349 PPC_LL r3, HOST_RUN(r1)
350 mr r5, r14 /* intno */
351 mr r14, r4 /* Save vcpu pointer. */
352 bl kvmppc_handle_exit
353
354 /* Restore vcpu pointer and the nonvolatiles we used. */
355 mr r4, r14
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]356 PPC_LL r14, VCPU_GPR(R14)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]357
358 andi. r5, r3, RESUME_FLAG_NV
359 beq skip_nv_load
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]360 PPC_LL r15, VCPU_GPR(R15)(r4)
361 PPC_LL r16, VCPU_GPR(R16)(r4)
362 PPC_LL r17, VCPU_GPR(R17)(r4)
363 PPC_LL r18, VCPU_GPR(R18)(r4)
364 PPC_LL r19, VCPU_GPR(R19)(r4)
365 PPC_LL r20, VCPU_GPR(R20)(r4)
366 PPC_LL r21, VCPU_GPR(R21)(r4)
367 PPC_LL r22, VCPU_GPR(R22)(r4)
368 PPC_LL r23, VCPU_GPR(R23)(r4)
369 PPC_LL r24, VCPU_GPR(R24)(r4)
370 PPC_LL r25, VCPU_GPR(R25)(r4)
371 PPC_LL r26, VCPU_GPR(R26)(r4)
372 PPC_LL r27, VCPU_GPR(R27)(r4)
373 PPC_LL r28, VCPU_GPR(R28)(r4)
374 PPC_LL r29, VCPU_GPR(R29)(r4)
375 PPC_LL r30, VCPU_GPR(R30)(r4)
376 PPC_LL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]377skip_nv_load:
378 /* Should we return to the guest? */
379 andi. r5, r3, RESUME_FLAG_HOST
380 beq lightweight_exit
381
382 srawi r3, r3, 2 /* Shift -ERR back down. */
383
384heavyweight_exit:
385 /* Not returning to guest. */
386 PPC_LL r5, HOST_STACK_LR(r1)
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]387 lwz r6, HOST_CR(r1)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]388
389 /*
390 * We already saved guest volatile register state; now save the
391 * non-volatiles.
392 */
393
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]394 PPC_STL r15, VCPU_GPR(R15)(r4)
395 PPC_STL r16, VCPU_GPR(R16)(r4)
396 PPC_STL r17, VCPU_GPR(R17)(r4)
397 PPC_STL r18, VCPU_GPR(R18)(r4)
398 PPC_STL r19, VCPU_GPR(R19)(r4)
399 PPC_STL r20, VCPU_GPR(R20)(r4)
400 PPC_STL r21, VCPU_GPR(R21)(r4)
401 PPC_STL r22, VCPU_GPR(R22)(r4)
402 PPC_STL r23, VCPU_GPR(R23)(r4)
403 PPC_STL r24, VCPU_GPR(R24)(r4)
404 PPC_STL r25, VCPU_GPR(R25)(r4)
405 PPC_STL r26, VCPU_GPR(R26)(r4)
406 PPC_STL r27, VCPU_GPR(R27)(r4)
407 PPC_STL r28, VCPU_GPR(R28)(r4)
408 PPC_STL r29, VCPU_GPR(R29)(r4)
409 PPC_STL r30, VCPU_GPR(R30)(r4)
410 PPC_STL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]411
412 /* Load host non-volatile register state from host stack. */
413 PPC_LL r14, HOST_NV_GPR(r14)(r1)
414 PPC_LL r15, HOST_NV_GPR(r15)(r1)
415 PPC_LL r16, HOST_NV_GPR(r16)(r1)
416 PPC_LL r17, HOST_NV_GPR(r17)(r1)
417 PPC_LL r18, HOST_NV_GPR(r18)(r1)
418 PPC_LL r19, HOST_NV_GPR(r19)(r1)
419 PPC_LL r20, HOST_NV_GPR(r20)(r1)
420 PPC_LL r21, HOST_NV_GPR(r21)(r1)
421 PPC_LL r22, HOST_NV_GPR(r22)(r1)
422 PPC_LL r23, HOST_NV_GPR(r23)(r1)
423 PPC_LL r24, HOST_NV_GPR(r24)(r1)
424 PPC_LL r25, HOST_NV_GPR(r25)(r1)
425 PPC_LL r26, HOST_NV_GPR(r26)(r1)
426 PPC_LL r27, HOST_NV_GPR(r27)(r1)
427 PPC_LL r28, HOST_NV_GPR(r28)(r1)
428 PPC_LL r29, HOST_NV_GPR(r29)(r1)
429 PPC_LL r30, HOST_NV_GPR(r30)(r1)
430 PPC_LL r31, HOST_NV_GPR(r31)(r1)
431
432 /* Return to kvm_vcpu_run(). */
433 mtlr r5
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]434 mtcr r6
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]435 addi r1, r1, HOST_STACK_SIZE
436 /* r3 still contains the return code from kvmppc_handle_exit(). */
437 blr
438
439/* Registers:
440 * r3: kvm_run pointer
441 * r4: vcpu pointer
442 */
443_GLOBAL(__kvmppc_vcpu_run)
444 stwu r1, -HOST_STACK_SIZE(r1)
445 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
446
447 /* Save host state to stack. */
448 PPC_STL r3, HOST_RUN(r1)
449 mflr r3
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]450 mfcr r5
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]451 PPC_STL r3, HOST_STACK_LR(r1)
452
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]453 stw r5, HOST_CR(r1)
454
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]455 /* Save host non-volatile register state to stack. */
456 PPC_STL r14, HOST_NV_GPR(r14)(r1)
457 PPC_STL r15, HOST_NV_GPR(r15)(r1)
458 PPC_STL r16, HOST_NV_GPR(r16)(r1)
459 PPC_STL r17, HOST_NV_GPR(r17)(r1)
460 PPC_STL r18, HOST_NV_GPR(r18)(r1)
461 PPC_STL r19, HOST_NV_GPR(r19)(r1)
462 PPC_STL r20, HOST_NV_GPR(r20)(r1)
463 PPC_STL r21, HOST_NV_GPR(r21)(r1)
464 PPC_STL r22, HOST_NV_GPR(r22)(r1)
465 PPC_STL r23, HOST_NV_GPR(r23)(r1)
466 PPC_STL r24, HOST_NV_GPR(r24)(r1)
467 PPC_STL r25, HOST_NV_GPR(r25)(r1)
468 PPC_STL r26, HOST_NV_GPR(r26)(r1)
469 PPC_STL r27, HOST_NV_GPR(r27)(r1)
470 PPC_STL r28, HOST_NV_GPR(r28)(r1)
471 PPC_STL r29, HOST_NV_GPR(r29)(r1)
472 PPC_STL r30, HOST_NV_GPR(r30)(r1)
473 PPC_STL r31, HOST_NV_GPR(r31)(r1)
474
475 /* Load guest non-volatiles. */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]476 PPC_LL r14, VCPU_GPR(R14)(r4)
477 PPC_LL r15, VCPU_GPR(R15)(r4)
478 PPC_LL r16, VCPU_GPR(R16)(r4)
479 PPC_LL r17, VCPU_GPR(R17)(r4)
480 PPC_LL r18, VCPU_GPR(R18)(r4)
481 PPC_LL r19, VCPU_GPR(R19)(r4)
482 PPC_LL r20, VCPU_GPR(R20)(r4)
483 PPC_LL r21, VCPU_GPR(R21)(r4)
484 PPC_LL r22, VCPU_GPR(R22)(r4)
485 PPC_LL r23, VCPU_GPR(R23)(r4)
486 PPC_LL r24, VCPU_GPR(R24)(r4)
487 PPC_LL r25, VCPU_GPR(R25)(r4)
488 PPC_LL r26, VCPU_GPR(R26)(r4)
489 PPC_LL r27, VCPU_GPR(R27)(r4)
490 PPC_LL r28, VCPU_GPR(R28)(r4)
491 PPC_LL r29, VCPU_GPR(R29)(r4)
492 PPC_LL r30, VCPU_GPR(R30)(r4)
493 PPC_LL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]494
495
496lightweight_exit:
497 PPC_STL r2, HOST_R2(r1)
498
499 mfspr r3, SPRN_PID
500 stw r3, VCPU_HOST_PID(r4)
501 lwz r3, VCPU_GUEST_PID(r4)
502 mtspr SPRN_PID, r3
503
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]504 PPC_LL r11, VCPU_SHARED(r4)
Alexander Grafe9ba39c2012-02-16 14:53:04 +0000[diff] [blame]505 /* Disable MAS register updates via exception */
506 mfspr r3, SPRN_EPCR
507 oris r3, r3, SPRN_EPCR_DMIUH@h
508 mtspr SPRN_EPCR, r3
509 isync
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]510 /* Save host mas4 and mas6 and load guest MAS registers */
511 mfspr r3, SPRN_MAS4
512 stw r3, VCPU_HOST_MAS4(r4)
513 mfspr r3, SPRN_MAS6
514 stw r3, VCPU_HOST_MAS6(r4)
515 lwz r3, VCPU_SHARED_MAS0(r11)
516 lwz r5, VCPU_SHARED_MAS1(r11)
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]517 PPC_LD(r6, VCPU_SHARED_MAS2, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]518 lwz r7, VCPU_SHARED_MAS7_3+4(r11)
519 lwz r8, VCPU_SHARED_MAS4(r11)
520 mtspr SPRN_MAS0, r3
521 mtspr SPRN_MAS1, r5
522 mtspr SPRN_MAS2, r6
523 mtspr SPRN_MAS3, r7
524 mtspr SPRN_MAS4, r8
525 lwz r3, VCPU_SHARED_MAS6(r11)
526 lwz r5, VCPU_SHARED_MAS7_3+0(r11)
527 mtspr SPRN_MAS6, r3
528 mtspr SPRN_MAS7, r5
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]529
530 /*
531 * Host interrupt handlers may have clobbered these guest-readable
532 * SPRGs, so we need to reload them here with the guest's values.
533 */
534 lwz r3, VCPU_VRSAVE(r4)
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]535 PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]536 mtspr SPRN_VRSAVE, r3
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]537 PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]538 mtspr SPRN_SPRG4W, r5
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]539 PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]540 mtspr SPRN_SPRG5W, r6
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]541 PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]542 mtspr SPRN_SPRG6W, r7
543 mtspr SPRN_SPRG7W, r8
544
545 /* Load some guest volatiles. */
546 PPC_LL r3, VCPU_LR(r4)
547 PPC_LL r5, VCPU_XER(r4)
548 PPC_LL r6, VCPU_CTR(r4)
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]549 lwz r7, VCPU_CR(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]550 PPC_LL r8, VCPU_PC(r4)
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]551 PPC_LD(r9, VCPU_SHARED_MSR, r11)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]552 PPC_LL r0, VCPU_GPR(R0)(r4)
553 PPC_LL r1, VCPU_GPR(R1)(r4)
554 PPC_LL r2, VCPU_GPR(R2)(r4)
555 PPC_LL r10, VCPU_GPR(R10)(r4)
556 PPC_LL r11, VCPU_GPR(R11)(r4)
557 PPC_LL r12, VCPU_GPR(R12)(r4)
558 PPC_LL r13, VCPU_GPR(R13)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]559 mtlr r3
560 mtxer r5
561 mtctr r6
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]562 mtsrr0 r8
563 mtsrr1 r9
564
565#ifdef CONFIG_KVM_EXIT_TIMING
566 /* save enter time */
5671:
568 mfspr r6, SPRN_TBRU
Bharat Bhushanc0fe7b02012-03-05 01:34:08 +0000[diff] [blame]569 mfspr r9, SPRN_TBRL
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]570 mfspr r8, SPRN_TBRU
571 cmpw r8, r6
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]572 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]573 bne 1b
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]574 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]575#endif
576
Bharat Bhushanc0fe7b02012-03-05 01:34:08 +0000[diff] [blame]577 /*
578 * Don't execute any instruction which can change CR after
579 * below instruction.
580 */
581 mtcr r7
582
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]583 /* Finish loading guest volatiles and jump to guest. */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]584 PPC_LL r5, VCPU_GPR(R5)(r4)
585 PPC_LL r6, VCPU_GPR(R6)(r4)
586 PPC_LL r7, VCPU_GPR(R7)(r4)
587 PPC_LL r8, VCPU_GPR(R8)(r4)
588 PPC_LL r9, VCPU_GPR(R9)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]589
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]590 PPC_LL r3, VCPU_GPR(R3)(r4)
591 PPC_LL r4, VCPU_GPR(R4)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]592 rfi