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Mark Browne1a3c742011-05-06 09:45:13 +09001/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * Copyright 2011 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/serial_core.h>
17#include <linux/platform_device.h>
18#include <linux/fb.h>
19#include <linux/io.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/regulator/machine.h>
Mark Brownae24c262011-06-22 13:08:13 +090024#include <linux/regulator/fixed.h>
Mark Browne1a3c742011-05-06 09:45:13 +090025#include <linux/pwm_backlight.h>
26#include <linux/dm9000.h>
27#include <linux/gpio_keys.h>
28#include <linux/basic_mmio_gpio.h>
29#include <linux/spi/spi.h>
30
31#include <linux/i2c/pca953x.h>
32
33#include <video/platform_lcd.h>
34
35#include <linux/mfd/wm831x/core.h>
36#include <linux/mfd/wm831x/pdata.h>
Mark Brownae24c262011-06-22 13:08:13 +090037#include <linux/mfd/wm831x/irq.h>
Mark Browne1a3c742011-05-06 09:45:13 +090038#include <linux/mfd/wm831x/gpio.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach-types.h>
42
43#include <mach/hardware.h>
44#include <mach/map.h>
45
Mark Browne1a3c742011-05-06 09:45:13 +090046#include <mach/regs-sys.h>
47#include <mach/regs-gpio.h>
48#include <mach/regs-modem.h>
49
Mark Browne1a3c742011-05-06 09:45:13 +090050#include <mach/regs-gpio-memport.h>
51
Kukjin Kim3cd7b622011-09-10 10:09:21 +090052#include <plat/s3c6410.h>
Mark Browne1a3c742011-05-06 09:45:13 +090053#include <plat/regs-serial.h>
54#include <plat/regs-fb-v4.h>
55#include <plat/fb.h>
56#include <plat/sdhci.h>
57#include <plat/gpio-cfg.h>
58#include <plat/s3c64xx-spi.h>
59
60#include <plat/keypad.h>
61#include <plat/clock.h>
62#include <plat/devs.h>
63#include <plat/cpu.h>
64#include <plat/adc.h>
65#include <plat/iic.h>
66#include <plat/pm.h>
67
Mark Browna9ba6152011-06-24 12:10:44 +010068#include <sound/wm8996.h>
Mark Brownae24c262011-06-22 13:08:13 +090069#include <sound/wm8962.h>
70#include <sound/wm9081.h>
Mark Browne1a3c742011-05-06 09:45:13 +090071
Mark Brownae24c262011-06-22 13:08:13 +090072#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
73#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
74
75#define PCA935X_GPIO_BASE GPIO_BOARD_START
76#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
77#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
Mark Browne1a3c742011-05-06 09:45:13 +090078
79/* serial port setup */
80
81#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
82#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
83#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
84
85static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
86 [0] = {
Mark Brownae24c262011-06-22 13:08:13 +090087 .hwport = 0,
88 .flags = 0,
89 .ucon = UCON,
90 .ulcon = ULCON,
91 .ufcon = UFCON,
Mark Browne1a3c742011-05-06 09:45:13 +090092 },
93 [1] = {
Mark Brownae24c262011-06-22 13:08:13 +090094 .hwport = 1,
95 .flags = 0,
96 .ucon = UCON,
97 .ulcon = ULCON,
98 .ufcon = UFCON,
Mark Browne1a3c742011-05-06 09:45:13 +090099 },
100 [2] = {
Mark Brownae24c262011-06-22 13:08:13 +0900101 .hwport = 2,
102 .flags = 0,
103 .ucon = UCON,
104 .ulcon = ULCON,
105 .ufcon = UFCON,
Mark Browne1a3c742011-05-06 09:45:13 +0900106 },
107 [3] = {
Mark Brownae24c262011-06-22 13:08:13 +0900108 .hwport = 3,
109 .flags = 0,
110 .ucon = UCON,
111 .ulcon = ULCON,
112 .ufcon = UFCON,
Mark Browne1a3c742011-05-06 09:45:13 +0900113 },
114};
115
116static struct platform_pwm_backlight_data crag6410_backlight_data = {
117 .pwm_id = 0,
118 .max_brightness = 1000,
119 .dft_brightness = 600,
120 .pwm_period_ns = 100000, /* about 1kHz */
121};
122
123static struct platform_device crag6410_backlight_device = {
124 .name = "pwm-backlight",
125 .id = -1,
126 .dev = {
127 .parent = &s3c_device_timer[0].dev,
128 .platform_data = &crag6410_backlight_data,
129 },
130};
131
132static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
133{
134 pr_debug("%s: setting power %d\n", __func__, power);
135
136 if (power) {
137 gpio_set_value(S3C64XX_GPB(0), 1);
138 msleep(1);
139 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
140 } else {
141 gpio_direction_output(S3C64XX_GPF(14), 0);
142 gpio_set_value(S3C64XX_GPB(0), 0);
143 }
144}
145
146static struct platform_device crag6410_lcd_powerdev = {
147 .name = "platform-lcd",
148 .id = -1,
149 .dev.parent = &s3c_device_fb.dev,
150 .dev.platform_data = &(struct plat_lcd_data) {
151 .set_power = crag6410_lcd_power_set,
152 },
153};
154
155/* 640x480 URT */
156static struct s3c_fb_pd_win crag6410_fb_win0 = {
157 /* this is to ensure we use win0 */
158 .win_mode = {
159 .left_margin = 150,
160 .right_margin = 80,
161 .upper_margin = 40,
162 .lower_margin = 5,
163 .hsync_len = 40,
164 .vsync_len = 5,
165 .xres = 640,
166 .yres = 480,
167 },
168 .max_bpp = 32,
169 .default_bpp = 16,
170 .virtual_y = 480 * 2,
171 .virtual_x = 640,
172};
173
174/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
175static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
176 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
177 .win[0] = &crag6410_fb_win0,
178 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
179 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
180};
181
182/* 2x6 keypad */
183
184static uint32_t crag6410_keymap[] __initdata = {
185 /* KEY(row, col, keycode) */
186 KEY(0, 0, KEY_VOLUMEUP),
187 KEY(0, 1, KEY_HOME),
188 KEY(0, 2, KEY_VOLUMEDOWN),
189 KEY(0, 3, KEY_HELP),
190 KEY(0, 4, KEY_MENU),
191 KEY(0, 5, KEY_MEDIA),
192 KEY(1, 0, 232),
193 KEY(1, 1, KEY_DOWN),
194 KEY(1, 2, KEY_LEFT),
195 KEY(1, 3, KEY_UP),
196 KEY(1, 4, KEY_RIGHT),
197 KEY(1, 5, KEY_CAMERA),
198};
199
200static struct matrix_keymap_data crag6410_keymap_data __initdata = {
201 .keymap = crag6410_keymap,
202 .keymap_size = ARRAY_SIZE(crag6410_keymap),
203};
204
205static struct samsung_keypad_platdata crag6410_keypad_data __initdata = {
206 .keymap_data = &crag6410_keymap_data,
207 .rows = 2,
208 .cols = 6,
209};
210
211static struct gpio_keys_button crag6410_gpio_keys[] = {
212 [0] = {
213 .code = KEY_SUSPEND,
214 .gpio = S3C64XX_GPL(10), /* EINT 18 */
Mark Brownae24c262011-06-22 13:08:13 +0900215 .type = EV_KEY,
Mark Browne1a3c742011-05-06 09:45:13 +0900216 .wakeup = 1,
217 .active_low = 1,
218 },
Mark Brownae24c262011-06-22 13:08:13 +0900219 [1] = {
220 .code = SW_FRONT_PROXIMITY,
221 .gpio = S3C64XX_GPN(11), /* EINT 11 */
222 .type = EV_SW,
223 },
Mark Browne1a3c742011-05-06 09:45:13 +0900224};
225
226static struct gpio_keys_platform_data crag6410_gpio_keydata = {
227 .buttons = crag6410_gpio_keys,
228 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
229};
230
231static struct platform_device crag6410_gpio_keydev = {
232 .name = "gpio-keys",
233 .id = 0,
234 .dev.platform_data = &crag6410_gpio_keydata,
235};
236
237static struct resource crag6410_dm9k_resource[] = {
238 [0] = {
239 .start = S3C64XX_PA_XM0CSN5,
240 .end = S3C64XX_PA_XM0CSN5 + 1,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = S3C64XX_PA_XM0CSN5 + (1 << 8),
245 .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [2] = {
249 .start = S3C_EINT(17),
250 .end = S3C_EINT(17),
251 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
252 },
253};
254
255static struct dm9000_plat_data mini6410_dm9k_pdata = {
256 .flags = DM9000_PLATF_16BITONLY,
257};
258
259static struct platform_device crag6410_dm9k_device = {
260 .name = "dm9000",
261 .id = -1,
262 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
263 .resource = crag6410_dm9k_resource,
264 .dev.platform_data = &mini6410_dm9k_pdata,
265};
266
267static struct resource crag6410_mmgpio_resource[] = {
268 [0] = {
269 .start = S3C64XX_PA_XM0CSN4 + 1,
270 .end = S3C64XX_PA_XM0CSN4 + 1,
271 .flags = IORESOURCE_MEM,
272 },
273};
274
275static struct platform_device crag6410_mmgpio = {
276 .name = "basic-mmio-gpio",
277 .id = -1,
278 .resource = crag6410_mmgpio_resource,
279 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
280 .dev.platform_data = &(struct bgpio_pdata) {
281 .base = -1,
282 },
283};
284
Mark Brownae24c262011-06-22 13:08:13 +0900285static struct platform_device speyside_device = {
286 .name = "speyside",
287 .id = -1,
288};
289
290static struct platform_device speyside_wm8962_device = {
291 .name = "speyside-wm8962",
292 .id = -1,
293};
294
295static struct regulator_consumer_supply wallvdd_consumers[] = {
296 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
297 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
298};
299
300static struct regulator_init_data wallvdd_data = {
301 .constraints = {
302 .always_on = 1,
303 },
304 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
305 .consumer_supplies = wallvdd_consumers,
306};
307
308static struct fixed_voltage_config wallvdd_pdata = {
309 .supply_name = "WALLVDD",
310 .microvolts = 5000000,
311 .init_data = &wallvdd_data,
312 .gpio = -EINVAL,
313};
314
315static struct platform_device wallvdd_device = {
316 .name = "reg-fixed-voltage",
317 .id = -1,
318 .dev = {
319 .platform_data = &wallvdd_pdata,
320 },
321};
322
Mark Browne1a3c742011-05-06 09:45:13 +0900323static struct platform_device *crag6410_devices[] __initdata = {
324 &s3c_device_hsmmc0,
325 &s3c_device_hsmmc1,
326 &s3c_device_hsmmc2,
327 &s3c_device_i2c0,
328 &s3c_device_i2c1,
329 &s3c_device_fb,
330 &s3c_device_ohci,
331 &s3c_device_usb_hsotg,
Mark Browne1a3c742011-05-06 09:45:13 +0900332 &s3c_device_timer[0],
333 &s3c64xx_device_iis0,
334 &s3c64xx_device_iis1,
335 &samsung_asoc_dma,
336 &samsung_device_keypad,
337 &crag6410_gpio_keydev,
338 &crag6410_dm9k_device,
339 &s3c64xx_device_spi0,
340 &crag6410_mmgpio,
341 &crag6410_lcd_powerdev,
342 &crag6410_backlight_device,
Mark Brownae24c262011-06-22 13:08:13 +0900343 &speyside_device,
344 &speyside_wm8962_device,
345 &wallvdd_device,
Mark Browne1a3c742011-05-06 09:45:13 +0900346};
347
348static struct pca953x_platform_data crag6410_pca_data = {
349 .gpio_base = PCA935X_GPIO_BASE,
350 .irq_base = 0,
351};
352
353static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
354 REGULATOR_SUPPLY("vddarm", NULL),
355};
356
357static struct regulator_init_data vddarm __initdata = {
358 .constraints = {
359 .name = "VDDARM",
360 .min_uV = 1000000,
361 .max_uV = 1300000,
362 .always_on = 1,
363 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
364 },
365 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
366 .consumer_supplies = vddarm_consumers,
Mark Brown35127292011-06-22 13:08:17 +0900367 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900368};
369
370static struct regulator_init_data vddint __initdata = {
371 .constraints = {
372 .name = "VDDINT",
373 .min_uV = 1000000,
374 .max_uV = 1200000,
375 .always_on = 1,
376 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
377 },
378};
379
380static struct regulator_init_data vddmem __initdata = {
381 .constraints = {
382 .name = "VDDMEM",
383 .always_on = 1,
384 },
385};
386
387static struct regulator_init_data vddsys __initdata = {
388 .constraints = {
389 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
390 .always_on = 1,
391 },
392};
393
394static struct regulator_consumer_supply vddmmc_consumers[] __initdata = {
395 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
396 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
397 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
398};
399
400static struct regulator_init_data vddmmc __initdata = {
401 .constraints = {
402 .name = "VDDMMC,UH",
403 .always_on = 1,
404 },
405 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
406 .consumer_supplies = vddmmc_consumers,
Mark Brown35127292011-06-22 13:08:17 +0900407 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900408};
409
410static struct regulator_init_data vddotgi __initdata = {
411 .constraints = {
412 .name = "VDDOTGi",
413 .always_on = 1,
414 },
Mark Brown35127292011-06-22 13:08:17 +0900415 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900416};
417
418static struct regulator_init_data vddotg __initdata = {
419 .constraints = {
420 .name = "VDDOTG",
421 .always_on = 1,
422 },
Mark Brown35127292011-06-22 13:08:17 +0900423 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900424};
425
426static struct regulator_init_data vddhi __initdata = {
427 .constraints = {
428 .name = "VDDHI",
429 .always_on = 1,
430 },
Mark Brown35127292011-06-22 13:08:17 +0900431 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900432};
433
434static struct regulator_init_data vddadc __initdata = {
435 .constraints = {
436 .name = "VDDADC,VDDDAC",
437 .always_on = 1,
438 },
Mark Brown35127292011-06-22 13:08:17 +0900439 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900440};
441
442static struct regulator_init_data vddmem0 __initdata = {
443 .constraints = {
444 .name = "VDDMEM0",
445 .always_on = 1,
446 },
Mark Brown35127292011-06-22 13:08:17 +0900447 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900448};
449
450static struct regulator_init_data vddpll __initdata = {
451 .constraints = {
452 .name = "VDDPLL",
453 .always_on = 1,
454 },
Mark Brown35127292011-06-22 13:08:17 +0900455 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900456};
457
458static struct regulator_init_data vddlcd __initdata = {
459 .constraints = {
460 .name = "VDDLCD",
461 .always_on = 1,
462 },
Mark Brown35127292011-06-22 13:08:17 +0900463 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900464};
465
466static struct regulator_init_data vddalive __initdata = {
467 .constraints = {
468 .name = "VDDALIVE",
469 .always_on = 1,
470 },
Mark Brown35127292011-06-22 13:08:17 +0900471 .supply_regulator = "WALLVDD",
Mark Browne1a3c742011-05-06 09:45:13 +0900472};
473
Mark Brown89e1c3d2011-07-21 01:26:24 +0900474static struct wm831x_backup_pdata banff_backup_pdata __initdata = {
475 .charger_enable = 1,
476 .vlim = 2500, /* mV */
477 .ilim = 200, /* uA */
478};
479
Mark Browne1a3c742011-05-06 09:45:13 +0900480static struct wm831x_status_pdata banff_red_led __initdata = {
481 .name = "banff:red:",
482 .default_src = WM831X_STATUS_MANUAL,
483};
484
485static struct wm831x_status_pdata banff_green_led __initdata = {
486 .name = "banff:green:",
487 .default_src = WM831X_STATUS_MANUAL,
488};
489
490static struct wm831x_touch_pdata touch_pdata __initdata = {
491 .data_irq = S3C_EINT(26),
Mark Brownae24c262011-06-22 13:08:13 +0900492 .pd_irq = S3C_EINT(27),
Mark Browne1a3c742011-05-06 09:45:13 +0900493};
494
Mark Browne1a3c742011-05-06 09:45:13 +0900495static struct wm831x_pdata crag_pmic_pdata __initdata = {
Mark Brownae24c262011-06-22 13:08:13 +0900496 .wm831x_num = 1,
Mark Browne1a3c742011-05-06 09:45:13 +0900497 .irq_base = BANFF_PMIC_IRQ_BASE,
498 .gpio_base = GPIO_BOARD_START + 8,
499
Mark Brown89e1c3d2011-07-21 01:26:24 +0900500 .backup = &banff_backup_pdata,
501
Mark Brownae24c262011-06-22 13:08:13 +0900502 .gpio_defaults = {
503 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
504 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
505 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
506 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
507 },
508
Mark Browne1a3c742011-05-06 09:45:13 +0900509 .dcdc = {
510 &vddarm, /* DCDC1 */
511 &vddint, /* DCDC2 */
512 &vddmem, /* DCDC3 */
513 },
514
515 .ldo = {
516 &vddsys, /* LDO1 */
517 &vddmmc, /* LDO2 */
518 NULL, /* LDO3 */
519 &vddotgi, /* LDO4 */
520 &vddotg, /* LDO5 */
521 &vddhi, /* LDO6 */
522 &vddadc, /* LDO7 */
523 &vddmem0, /* LDO8 */
524 &vddpll, /* LDO9 */
525 &vddlcd, /* LDO10 */
526 &vddalive, /* LDO11 */
527 },
528
529 .status = {
530 &banff_green_led,
531 &banff_red_led,
532 },
533
534 .touch = &touch_pdata,
535};
536
537static struct i2c_board_info i2c_devs0[] __initdata = {
538 { I2C_BOARD_INFO("24c08", 0x50), },
539 { I2C_BOARD_INFO("tca6408", 0x20),
540 .platform_data = &crag6410_pca_data,
541 },
542 { I2C_BOARD_INFO("wm8312", 0x34),
543 .platform_data = &crag_pmic_pdata,
544 .irq = S3C_EINT(23),
545 },
546};
547
548static struct s3c2410_platform_i2c i2c0_pdata = {
549 .frequency = 400000,
550};
551
Mark Brownae24c262011-06-22 13:08:13 +0900552static struct regulator_init_data pvdd_1v2 __initdata = {
553 .constraints = {
554 .name = "PVDD_1V2",
555 .always_on = 1,
556 },
557};
558
559static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
560 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
561 REGULATOR_SUPPLY("DBVDD", "1-001a"),
562 REGULATOR_SUPPLY("CPVDD", "1-001a"),
563 REGULATOR_SUPPLY("AVDD2", "1-001a"),
564 REGULATOR_SUPPLY("DCVDD", "1-001a"),
565 REGULATOR_SUPPLY("AVDD", "1-001a"),
566};
567
568static struct regulator_init_data pvdd_1v8 __initdata = {
569 .constraints = {
570 .name = "PVDD_1V8",
571 .always_on = 1,
572 },
573
574 .consumer_supplies = pvdd_1v8_consumers,
575 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
576};
577
578static struct regulator_consumer_supply pvdd_3v3_consumers[] __initdata = {
579 REGULATOR_SUPPLY("MICVDD", "1-001a"),
580 REGULATOR_SUPPLY("AVDD1", "1-001a"),
581};
582
583static struct regulator_init_data pvdd_3v3 __initdata = {
584 .constraints = {
585 .name = "PVDD_3V3",
586 .always_on = 1,
587 },
588
589 .consumer_supplies = pvdd_3v3_consumers,
590 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
591};
592
593static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
594 .wm831x_num = 2,
595 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
596 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
597
598 .gpio_defaults = {
599 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
600 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
601 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
602 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
603 },
604
605 .dcdc = {
606 &pvdd_1v2, /* DCDC1 */
607 &pvdd_1v8, /* DCDC2 */
608 &pvdd_3v3, /* DCDC3 */
609 },
610
611 .disable_touch = true,
612};
613
Mark Browna9ba6152011-06-24 12:10:44 +0100614static struct wm8996_retune_mobile_config wm8996_retune[] = {
Mark Brownae24c262011-06-22 13:08:13 +0900615 {
616 .name = "Sub LPF",
617 .rate = 48000,
618 .regs = {
619 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
620 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
621 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
622 },
623 },
624 {
625 .name = "Sub HPF",
626 .rate = 48000,
627 .regs = {
628 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
629 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
630 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
631 },
632 },
633};
634
Mark Browna9ba6152011-06-24 12:10:44 +0100635static struct wm8996_pdata wm8996_pdata __initdata = {
Mark Brownae24c262011-06-22 13:08:13 +0900636 .ldo_ena = S3C64XX_GPN(7),
637 .gpio_base = CODEC_GPIO_BASE,
638 .micdet_def = 1,
Mark Browna9ba6152011-06-24 12:10:44 +0100639 .inl_mode = WM8996_DIFFERRENTIAL_1,
640 .inr_mode = WM8996_DIFFERRENTIAL_1,
Mark Brownae24c262011-06-22 13:08:13 +0900641
Mark Brown1a26d732011-06-22 13:08:59 +0900642 .irq_flags = IRQF_TRIGGER_RISING,
Mark Brownae24c262011-06-22 13:08:13 +0900643
644 .gpio_default = {
645 0x8001, /* GPIO1 == ADCLRCLK1 */
646 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
647 0x0141, /* GPIO3 == HP_SEL */
648 0x0002, /* GPIO4 == IRQ */
649 0x020e, /* GPIO5 == CLKOUT */
650 },
651
Mark Browna9ba6152011-06-24 12:10:44 +0100652 .retune_mobile_cfgs = wm8996_retune,
653 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
Mark Brownae24c262011-06-22 13:08:13 +0900654};
655
656static struct wm8962_pdata wm8962_pdata __initdata = {
657 .gpio_init = {
658 0,
659 WM8962_GPIO_FN_OPCLK,
660 WM8962_GPIO_FN_DMICCLK,
661 0,
662 0x8000 | WM8962_GPIO_FN_DMICDAT,
663 WM8962_GPIO_FN_IRQ, /* Open drain mode */
664 },
665 .irq_active_low = true,
666};
667
668static struct wm9081_pdata wm9081_pdata __initdata = {
669 .irq_high = false,
670 .irq_cmos = false,
671};
672
Mark Browne1a3c742011-05-06 09:45:13 +0900673static struct i2c_board_info i2c_devs1[] __initdata = {
674 { I2C_BOARD_INFO("wm8311", 0x34),
Mark Brownae24c262011-06-22 13:08:13 +0900675 .irq = S3C_EINT(0),
676 .platform_data = &glenfarclas_pmic_pdata },
677
678 { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
Mark Browna9ba6152011-06-24 12:10:44 +0100679 { I2C_BOARD_INFO("wm8996", 0x1a),
680 .platform_data = &wm8996_pdata,
Mark Brownae24c262011-06-22 13:08:13 +0900681 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
682 },
683 { I2C_BOARD_INFO("wm9081", 0x6c),
684 .platform_data = &wm9081_pdata, },
685 { I2C_BOARD_INFO("wm8962", 0x1a),
686 .platform_data = &wm8962_pdata,
687 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
Mark Browne1a3c742011-05-06 09:45:13 +0900688 },
689};
690
691static void __init crag6410_map_io(void)
692{
693 s3c64xx_init_io(NULL, 0);
694 s3c24xx_init_clocks(12000000);
695 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
696
697 /* LCD type and Bypass set by bootloader */
698}
699
700static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
701 .max_width = 4,
702 .cd_type = S3C_SDHCI_CD_PERMANENT,
703};
704
705static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
706 .max_width = 4,
707 .cd_type = S3C_SDHCI_CD_GPIO,
708 .ext_cd_gpio = S3C64XX_GPF(11),
709};
710
711static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
712{
713 /* Set all the necessary GPG pins to special-function 2 */
714 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
715
716 /* force card-detected for prototype 0 */
717 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
718}
719
720static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
721 .max_width = 4,
722 .cd_type = S3C_SDHCI_CD_INTERNAL,
723 .cfg_gpio = crag6410_cfg_sdhci0,
724};
725
726static void __init crag6410_machine_init(void)
727{
728 /* Open drain IRQs need pullups */
729 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
730 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
731
732 gpio_request(S3C64XX_GPB(0), "LCD power");
733 gpio_direction_output(S3C64XX_GPB(0), 0);
734
735 gpio_request(S3C64XX_GPF(14), "LCD PWM");
736 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
737
738 gpio_request(S3C64XX_GPB(1), "SD power");
739 gpio_direction_output(S3C64XX_GPB(1), 0);
740
741 gpio_request(S3C64XX_GPF(10), "nRESETSEL");
742 gpio_direction_output(S3C64XX_GPF(10), 1);
743
744 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
745 s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
746 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
747
748 s3c_i2c0_set_platdata(&i2c0_pdata);
749 s3c_i2c1_set_platdata(NULL);
750 s3c_fb_set_platdata(&crag6410_lcd_pdata);
751
752 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
753 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
754
755 samsung_keypad_set_platdata(&crag6410_keypad_data);
756
757 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
758
Mark Brownae24c262011-06-22 13:08:13 +0900759 regulator_has_full_constraints();
760
Mark Browne1a3c742011-05-06 09:45:13 +0900761 s3c_pm_init();
762}
763
764MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
765 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
766 .boot_params = S3C64XX_PA_SDRAM + 0x100,
767 .init_irq = s3c6410_init_irq,
768 .map_io = crag6410_map_io,
769 .init_machine = crag6410_machine_init,
770 .timer = &s3c24xx_timer,
771MACHINE_END