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review.evervolv.com / android_kernel_oneplus_msm8996 / 3fbf07d80b40f73c304624179381f9038bd03b74 / . / arch / arm / boot / dts / tegra30.dtsi
blob: 572a45bab93be3c2e150a315cd57f9813bd367e0 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra30-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra30-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra30-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]38 clocks = <&tegra_car 164>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra30-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra30-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra30-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra30-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]65 clocks = <&tegra_car 24 &tegra_car 98>;
66 clock-names = "3d", "3d2";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]67 };
68
69 dc@54200000 {
70 compatible = "nvidia,tegra30-dc";
71 reg = <0x54200000 0x00040000>;
72 interrupts = <0 73 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]73 clocks = <&tegra_car 27>, <&tegra_car 179>;
74 clock-names = "disp1", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]75
76 rgb {
77 status = "disabled";
78 };
79 };
80
81 dc@54240000 {
82 compatible = "nvidia,tegra30-dc";
83 reg = <0x54240000 0x00040000>;
84 interrupts = <0 74 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]85 clocks = <&tegra_car 26>, <&tegra_car 179>;
86 clock-names = "disp2", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]87
88 rgb {
89 status = "disabled";
90 };
91 };
92
93 hdmi {
94 compatible = "nvidia,tegra30-hdmi";
95 reg = <0x54280000 0x00040000>;
96 interrupts = <0 75 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]97 clocks = <&tegra_car 51>, <&tegra_car 189>;
98 clock-names = "hdmi", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]99 status = "disabled";
100 };
101
102 tvo {
103 compatible = "nvidia,tegra30-tvo";
104 reg = <0x542c0000 0x00040000>;
105 interrupts = <0 76 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]106 clocks = <&tegra_car 169>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]107 status = "disabled";
108 };
109
110 dsi {
111 compatible = "nvidia,tegra30-dsi";
112 reg = <0x54300000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]113 clocks = <&tegra_car 48>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]114 status = "disabled";
115 };
116 };
117
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]118 timer@50004600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x50040600 0x20>;
121 interrupts = <1 13 0xf04>;
122 };
123
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]124 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]125 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]126 reg = <0x50041000 0x1000
127 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]128 interrupt-controller;
129 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]130 };
131
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]132 cache-controller {
133 compatible = "arm,pl310-cache";
134 reg = <0x50043000 0x1000>;
135 arm,data-latency = <6 6 2>;
136 arm,tag-latency = <5 5 2>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]141 timer@60005000 {
142 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
143 reg = <0x60005000 0x400>;
144 interrupts = <0 0 0x04
145 0 1 0x04
146 0 41 0x04
147 0 42 0x04
148 0 121 0x04
149 0 122 0x04>;
150 };
151
Prashant Gaikwad95985662013-01-11 13:16:23 +0530[diff] [blame]152 tegra_car: clock {
153 compatible = "nvidia,tegra30-car";
154 reg = <0x60006000 0x1000>;
155 #clock-cells = <1>;
156 };
157
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]158 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]159 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
160 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]161 interrupts = <0 104 0x04
162 0 105 0x04
163 0 106 0x04
164 0 107 0x04
165 0 108 0x04
166 0 109 0x04
167 0 110 0x04
168 0 111 0x04
169 0 112 0x04
170 0 113 0x04
171 0 114 0x04
172 0 115 0x04
173 0 116 0x04
174 0 117 0x04
175 0 118 0x04
176 0 119 0x04
177 0 128 0x04
178 0 129 0x04
179 0 130 0x04
180 0 131 0x04
181 0 132 0x04
182 0 133 0x04
183 0 134 0x04
184 0 135 0x04
185 0 136 0x04
186 0 137 0x04
187 0 138 0x04
188 0 139 0x04
189 0 140 0x04
190 0 141 0x04
191 0 142 0x04
192 0 143 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]193 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]194 };
195
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]196 ahb: ahb {
197 compatible = "nvidia,tegra30-ahb";
198 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
199 };
200
201 gpio: gpio {
Laxman Dewangan35f210e2012-12-19 20:27:12 +0530[diff] [blame]202 compatible = "nvidia,tegra30-gpio";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]203 reg = <0x6000d000 0x1000>;
204 interrupts = <0 32 0x04
205 0 33 0x04
206 0 34 0x04
207 0 35 0x04
208 0 55 0x04
209 0 87 0x04
210 0 89 0x04
211 0 125 0x04>;
212 #gpio-cells = <2>;
213 gpio-controller;
214 #interrupt-cells = <2>;
215 interrupt-controller;
216 };
217
218 pinmux: pinmux {
219 compatible = "nvidia,tegra30-pinmux";
Pritesh Raithatha322337b2012-10-30 15:37:09 +0530[diff] [blame]220 reg = <0x70000868 0xd4 /* Pad control registers */
221 0x70003000 0x3e4>; /* Mux registers */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]222 };
223
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]224 /*
225 * There are two serial driver i.e. 8250 based simple serial
226 * driver and APB DMA based serial driver for higher baudrate
227 * and performace. To enable the 8250 based driver, the compatible
228 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
229 * the APB DMA based serial driver, the comptible is
230 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
231 */
232 uarta: serial@70006000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]233 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
234 reg = <0x70006000 0x40>;
235 reg-shift = <2>;
236 interrupts = <0 36 0x04>;
Stephen Warrenabf80c22013-01-23 09:43:49 -0700[diff] [blame]237 clock-frequency = <408000000>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]238 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]239 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]240 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]241 };
242
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]243 uartb: serial@70006040 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]244 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
245 reg = <0x70006040 0x40>;
246 reg-shift = <2>;
Stephen Warrenabf80c22013-01-23 09:43:49 -0700[diff] [blame]247 clock-frequency = <408000000>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]248 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]249 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]250 clocks = <&tegra_car 160>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]251 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]252 };
253
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]254 uartc: serial@70006200 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]255 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
256 reg = <0x70006200 0x100>;
257 reg-shift = <2>;
Stephen Warrenabf80c22013-01-23 09:43:49 -0700[diff] [blame]258 clock-frequency = <408000000>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]259 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]260 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]261 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]262 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]263 };
264
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]265 uartd: serial@70006300 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]266 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
267 reg = <0x70006300 0x100>;
268 reg-shift = <2>;
Stephen Warrenabf80c22013-01-23 09:43:49 -0700[diff] [blame]269 clock-frequency = <408000000>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]270 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]271 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]272 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]273 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]274 };
275
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]276 uarte: serial@70006400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]277 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
278 reg = <0x70006400 0x100>;
279 reg-shift = <2>;
Stephen Warrenabf80c22013-01-23 09:43:49 -0700[diff] [blame]280 clock-frequency = <408000000>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]281 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]282 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]283 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]284 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]285 };
286
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]287 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]288 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
289 reg = <0x7000a000 0x100>;
290 #pwm-cells = <2>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]291 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]292 };
293
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]294 rtc {
295 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
296 reg = <0x7000e000 0x100>;
297 interrupts = <0 2 0x04>;
298 };
299
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]300 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]301 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]302 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]303 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]304 #address-cells = <1>;
305 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]306 clocks = <&tegra_car 12>, <&tegra_car 182>;
307 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]308 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]309 };
310
311 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]312 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]313 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]314 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]315 #address-cells = <1>;
316 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]317 clocks = <&tegra_car 54>, <&tegra_car 182>;
318 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]319 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]320 };
321
322 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]323 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]324 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]325 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]326 #address-cells = <1>;
327 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]328 clocks = <&tegra_car 67>, <&tegra_car 182>;
329 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]330 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]331 };
332
333 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]334 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
335 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]336 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]337 #address-cells = <1>;
338 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]339 clocks = <&tegra_car 103>, <&tegra_car 182>;
340 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]341 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]342 };
343
344 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]345 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]346 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]347 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]348 #address-cells = <1>;
349 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]350 clocks = <&tegra_car 47>, <&tegra_car 182>;
351 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]352 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]353 };
354
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]355 spi@7000d400 {
356 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
357 reg = <0x7000d400 0x200>;
358 interrupts = <0 59 0x04>;
359 nvidia,dma-request-selector = <&apbdma 15>;
360 #address-cells = <1>;
361 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]362 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]363 status = "disabled";
364 };
365
366 spi@7000d600 {
367 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
368 reg = <0x7000d600 0x200>;
369 interrupts = <0 82 0x04>;
370 nvidia,dma-request-selector = <&apbdma 16>;
371 #address-cells = <1>;
372 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]373 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]374 status = "disabled";
375 };
376
377 spi@7000d800 {
378 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
379 reg = <0x7000d480 0x200>;
380 interrupts = <0 83 0x04>;
381 nvidia,dma-request-selector = <&apbdma 17>;
382 #address-cells = <1>;
383 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]384 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]385 status = "disabled";
386 };
387
388 spi@7000da00 {
389 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
390 reg = <0x7000da00 0x200>;
391 interrupts = <0 93 0x04>;
392 nvidia,dma-request-selector = <&apbdma 18>;
393 #address-cells = <1>;
394 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]395 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]396 status = "disabled";
397 };
398
399 spi@7000dc00 {
400 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
401 reg = <0x7000dc00 0x200>;
402 interrupts = <0 94 0x04>;
403 nvidia,dma-request-selector = <&apbdma 27>;
404 #address-cells = <1>;
405 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]406 clocks = <&tegra_car 104>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]407 status = "disabled";
408 };
409
410 spi@7000de00 {
411 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
412 reg = <0x7000de00 0x200>;
413 interrupts = <0 79 0x04>;
414 nvidia,dma-request-selector = <&apbdma 28>;
415 #address-cells = <1>;
416 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]417 clocks = <&tegra_car 105>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]418 status = "disabled";
419 };
420
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]421 kbc {
422 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
423 reg = <0x7000e200 0x100>;
424 interrupts = <0 85 0x04>;
425 clocks = <&tegra_car 36>;
426 status = "disabled";
427 };
428
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]429 pmc {
430 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
431 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]432 };
433
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]434 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]435 compatible = "nvidia,tegra30-mc";
436 reg = <0x7000f000 0x010
437 0x7000f03c 0x1b4
438 0x7000f200 0x028
439 0x7000f284 0x17c>;
440 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]441 };
442
Hiroshi Doyu3fbf07d2013-01-29 10:30:29 +0200[diff] [blame^]443 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]444 compatible = "nvidia,tegra30-smmu";
445 reg = <0x7000f010 0x02c
446 0x7000f1f0 0x010
447 0x7000f228 0x05c>;
448 nvidia,#asids = <4>; /* # of ASIDs */
449 dma-window = <0 0x40000000>; /* IOVA start & length */
450 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]451 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]452
453 ahub {
454 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]455 reg = <0x70080000 0x200
456 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]457 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]458 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]459 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
460 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
461 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
462 <&tegra_car 110>, <&tegra_car 162>;
463 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
464 "i2s3", "i2s4", "dam0", "dam1", "dam2",
465 "spdif_in";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]466 ranges;
467 #address-cells = <1>;
468 #size-cells = <1>;
469
470 tegra_i2s0: i2s@70080300 {
471 compatible = "nvidia,tegra30-i2s";
472 reg = <0x70080300 0x100>;
473 nvidia,ahub-cif-ids = <4 4>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]474 clocks = <&tegra_car 30>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]475 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]476 };
477
478 tegra_i2s1: i2s@70080400 {
479 compatible = "nvidia,tegra30-i2s";
480 reg = <0x70080400 0x100>;
481 nvidia,ahub-cif-ids = <5 5>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]482 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]483 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]484 };
485
486 tegra_i2s2: i2s@70080500 {
487 compatible = "nvidia,tegra30-i2s";
488 reg = <0x70080500 0x100>;
489 nvidia,ahub-cif-ids = <6 6>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]490 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]491 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]492 };
493
494 tegra_i2s3: i2s@70080600 {
495 compatible = "nvidia,tegra30-i2s";
496 reg = <0x70080600 0x100>;
497 nvidia,ahub-cif-ids = <7 7>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]498 clocks = <&tegra_car 101>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]499 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]500 };
501
502 tegra_i2s4: i2s@70080700 {
503 compatible = "nvidia,tegra30-i2s";
504 reg = <0x70080700 0x100>;
505 nvidia,ahub-cif-ids = <8 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]506 clocks = <&tegra_car 102>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]507 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]508 };
509 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]510
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]511 sdhci@78000000 {
512 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
513 reg = <0x78000000 0x200>;
514 interrupts = <0 14 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]515 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]516 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]517 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]518
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]519 sdhci@78000200 {
520 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
521 reg = <0x78000200 0x200>;
522 interrupts = <0 15 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]523 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]524 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]525 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]526
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]527 sdhci@78000400 {
528 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
529 reg = <0x78000400 0x200>;
530 interrupts = <0 19 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]531 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]532 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]533 };
534
535 sdhci@78000600 {
536 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
537 reg = <0x78000600 0x200>;
538 interrupts = <0 31 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]539 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]540 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]541 };
542
Hiroshi Doyu7d19a342013-01-11 15:11:54 +0200[diff] [blame]543 cpus {
544 #address-cells = <1>;
545 #size-cells = <0>;
546
547 cpu@0 {
548 device_type = "cpu";
549 compatible = "arm,cortex-a9";
550 reg = <0>;
551 };
552
553 cpu@1 {
554 device_type = "cpu";
555 compatible = "arm,cortex-a9";
556 reg = <1>;
557 };
558
559 cpu@2 {
560 device_type = "cpu";
561 compatible = "arm,cortex-a9";
562 reg = <2>;
563 };
564
565 cpu@3 {
566 device_type = "cpu";
567 compatible = "arm,cortex-a9";
568 reg = <3>;
569 };
570 };
571
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]572 pmu {
573 compatible = "arm,cortex-a9-pmu";
574 interrupts = <0 144 0x04
575 0 145 0x04
576 0 146 0x04
577 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]578 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]579};