blob: f6c61d10fd2781f055a249b30443359e05614a62 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060067 dta {
68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
69 nvidia,function = "vi";
70 };
71 dtf {
72 nvidia,pins = "dtf";
73 nvidia,function = "i2c3";
74 };
75 gmc {
76 nvidia,pins = "gmc";
77 nvidia,function = "uartd";
78 };
79 gmd {
80 nvidia,pins = "gmd";
81 nvidia,function = "sflash";
82 };
83 gpu {
84 nvidia,pins = "gpu";
85 nvidia,function = "pwm";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
Mark Zhangcf633462012-10-25 14:52:30 +080096 nvidia,pins = "hdint";
Stephen Warrenecc295b2012-03-15 16:27:36 -060097 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uartb";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
114 "lsdi", "lvp0";
115 nvidia,function = "rsvd4";
116 };
117 ld0 {
118 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
119 "ld5", "ld6", "ld7", "ld8", "ld9",
120 "ld10", "ld11", "ld12", "ld13", "ld14",
121 "ld15", "ld16", "ld17", "ldi", "lhp0",
122 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
123 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
124 "lspi", "lvp1", "lvs";
125 nvidia,function = "displaya";
126 };
Mark Zhangcf633462012-10-25 14:52:30 +0800127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600131 pmc {
132 nvidia,pins = "pmc";
133 nvidia,function = "pwr_on";
134 };
135 rm {
136 nvidia,pins = "rm";
137 nvidia,function = "i2c1";
138 };
139 sdb {
140 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
141 nvidia,function = "sdio3";
142 };
143 sdio1 {
144 nvidia,pins = "sdio1";
145 nvidia,function = "sdio1";
146 };
147 slxd {
148 nvidia,pins = "slxd";
149 nvidia,function = "spdif";
150 };
151 spid {
152 nvidia,pins = "spid", "spie", "spif";
153 nvidia,function = "spi1";
154 };
155 spig {
156 nvidia,pins = "spig", "spih";
157 nvidia,function = "spi2_alt";
158 };
159 uaa {
160 nvidia,pins = "uaa", "uab", "uda";
161 nvidia,function = "ulpi";
162 };
163 uad {
164 nvidia,pins = "uad";
165 nvidia,function = "irda";
166 };
167 uca {
168 nvidia,pins = "uca", "ucb";
169 nvidia,function = "uartc";
170 };
171 conf_ata {
172 nvidia,pins = "ata", "atb", "atc", "atd",
173 "cdev1", "cdev2", "dap1", "dap2",
174 "dap4", "ddc", "dtf", "gma", "gmc",
175 "gme", "gpu", "gpu7", "i2cp", "irrx",
176 "irtx", "pta", "rm", "sdc", "sdd",
177 "slxc", "slxd", "slxk", "spdi", "spdo",
178 "uac", "uad", "uca", "ucb", "uda";
179 nvidia,pull = <0>;
180 nvidia,tristate = <0>;
181 };
182 conf_ate {
183 nvidia,pins = "ate", "csus", "dap3", "gmd",
184 "gpv", "owc", "spia", "spib", "spic",
185 "spid", "spie", "spig";
186 nvidia,pull = <0>;
187 nvidia,tristate = <1>;
188 };
189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
192 nvidia,pull = <0>;
193 };
194 conf_crtp {
195 nvidia,pins = "crtp", "gmb", "slxa", "spih";
196 nvidia,pull = <2>;
197 nvidia,tristate = <1>;
198 };
199 conf_dta {
200 nvidia,pins = "dta", "dtb", "dtc", "dtd";
201 nvidia,pull = <1>;
202 nvidia,tristate = <0>;
203 };
204 conf_dte {
205 nvidia,pins = "dte", "spif";
206 nvidia,pull = <1>;
207 nvidia,tristate = <1>;
208 };
209 conf_hdint {
210 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
211 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
212 nvidia,tristate = <1>;
213 };
214 conf_kbca {
215 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
216 "kbce", "kbcf", "sdio1", "uaa", "uab";
217 nvidia,pull = <2>;
218 nvidia,tristate = <0>;
219 };
220 conf_lc {
221 nvidia,pins = "lc", "ls";
222 nvidia,pull = <2>;
223 };
224 conf_ld0 {
225 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
226 "ld5", "ld6", "ld7", "ld8", "ld9",
227 "ld10", "ld11", "ld12", "ld13", "ld14",
228 "ld15", "ld16", "ld17", "ldi", "lhp0",
229 "lhp1", "lhp2", "lhs", "lm0", "lpp",
230 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
231 "lvp1", "lvs", "pmc", "sdb";
232 nvidia,tristate = <0>;
233 };
234 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22";
237 nvidia,pull = <1>;
238 };
Wei Nic7294292012-09-21 16:54:58 +0800239 drive_sdio1 {
240 nvidia,pins = "drive_sdio1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <3>;
244 nvidia,pull-down-strength = <31>;
245 nvidia,pull-up-strength = <31>;
246 nvidia,slew-rate-rising = <3>;
247 nvidia,slew-rate-falling = <3>;
248 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600249 };
Mark Zhangcf633462012-10-25 14:52:30 +0800250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
282 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600283 };
284
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600285 i2s@70002800 {
286 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600287 };
288
289 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600290 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600291 clock-frequency = <216000000>;
292 };
293
Stephen Warren88950f32011-11-21 14:44:09 -0700294 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600295 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700296 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700297
298 wm8903: wm8903@1a {
299 compatible = "wlf,wm8903";
300 reg = <0x1a>;
301 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600302 interrupts = <187 0x04>;
Stephen Warren797acf72012-01-11 16:09:57 -0700303
304 gpio-controller;
305 #gpio-cells = <2>;
306
307 micdet-cfg = <0>;
308 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600309 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700310 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530311
312 /* ALS and proximity sensor */
313 isl29018@44 {
314 compatible = "isil,isl29018";
315 reg = <0x44>;
316 interrupt-parent = <&gpio>;
317 interrupts = <202 0x04>; /*gpio PZ2 */
318 };
Stephen Warren88950f32011-11-21 14:44:09 -0700319 };
320
321 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600322 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700323 clock-frequency = <400000>;
324 };
325
Mark Zhangcf633462012-10-25 14:52:30 +0800326 i2cmux {
327 compatible = "i2c-mux-pinctrl";
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 i2c-parent = <&{/i2c@7000c400}>;
332
333 pinctrl-names = "ddc", "pta", "idle";
334 pinctrl-0 = <&state_i2cmux_ddc>;
335 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>;
337
338 i2c@0 {
339 reg = <0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 };
343
344 i2c@1 {
345 reg = <1>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349 };
350
Stephen Warren88950f32011-11-21 14:44:09 -0700351 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600352 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700353 clock-frequency = <400000>;
354 };
355
356 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600357 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700358 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600359
360 pmic: tps6586x@34 {
361 compatible = "ti,tps6586x";
362 reg = <0x34>;
363 interrupts = <0 86 0x4>;
364
Stephen Warren44b12ef2012-09-11 11:42:26 -0600365 ti,system-power-controller;
366
Stephen Warren017a0102012-06-20 16:53:41 -0600367 #gpio-cells = <2>;
368 gpio-controller;
369
370 sys-supply = <&vdd_5v0_reg>;
371 vin-sm0-supply = <&sys_reg>;
372 vin-sm1-supply = <&sys_reg>;
373 vin-sm2-supply = <&sys_reg>;
374 vinldo01-supply = <&sm2_reg>;
375 vinldo23-supply = <&sm2_reg>;
376 vinldo4-supply = <&sm2_reg>;
377 vinldo678-supply = <&sm2_reg>;
378 vinldo9-supply = <&sm2_reg>;
379
380 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600381 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600382 regulator-name = "vdd_sys";
383 regulator-always-on;
384 };
385
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600386 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600387 regulator-name = "vdd_sm0,vdd_core";
388 regulator-min-microvolt = <1200000>;
389 regulator-max-microvolt = <1200000>;
390 regulator-always-on;
391 };
392
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600393 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600394 regulator-name = "vdd_sm1,vdd_cpu";
395 regulator-min-microvolt = <1000000>;
396 regulator-max-microvolt = <1000000>;
397 regulator-always-on;
398 };
399
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600400 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600401 regulator-name = "vdd_sm2,vin_ldo*";
402 regulator-min-microvolt = <3700000>;
403 regulator-max-microvolt = <3700000>;
404 regulator-always-on;
405 };
406
407 /* LDO0 is not connected to anything */
408
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600409 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600410 regulator-name = "vdd_ldo1,avdd_pll*";
411 regulator-min-microvolt = <1100000>;
412 regulator-max-microvolt = <1100000>;
413 regulator-always-on;
414 };
415
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600416 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600417 regulator-name = "vdd_ldo2,vdd_rtc";
418 regulator-min-microvolt = <1200000>;
419 regulator-max-microvolt = <1200000>;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600423 regulator-name = "vdd_ldo3,avdd_usb*";
424 regulator-min-microvolt = <3300000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-always-on;
427 };
428
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600429 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600430 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
431 regulator-min-microvolt = <1800000>;
432 regulator-max-microvolt = <1800000>;
433 regulator-always-on;
434 };
435
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600436 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600437 regulator-name = "vdd_ldo5,vcore_mmc";
438 regulator-min-microvolt = <2850000>;
439 regulator-max-microvolt = <2850000>;
440 regulator-always-on;
441 };
442
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600443 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600444 regulator-name = "vdd_ldo6,avdd_vdac";
445 regulator-min-microvolt = <1800000>;
446 regulator-max-microvolt = <1800000>;
447 };
448
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600449 ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600450 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
451 regulator-min-microvolt = <3300000>;
452 regulator-max-microvolt = <3300000>;
453 };
454
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600455 ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600456 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 };
460
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600461 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600462 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
463 regulator-min-microvolt = <2850000>;
464 regulator-max-microvolt = <2850000>;
465 regulator-always-on;
466 };
467
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600468 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600469 regulator-name = "vdd_rtc_out,vdd_cell";
470 regulator-min-microvolt = <3300000>;
471 regulator-max-microvolt = <3300000>;
472 regulator-always-on;
473 };
474 };
475 };
Thierry Redingee9f7262012-11-09 23:01:21 +0100476
477 temperature-sensor@4c {
478 compatible = "onnn,nct1008";
479 reg = <0x4c>;
480 };
Stephen Warren017a0102012-06-20 16:53:41 -0600481 };
482
483 pmc {
484 nvidia,invert-interrupt;
Stephen Warren88950f32011-11-21 14:44:09 -0700485 };
486
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600487 usb@c5000000 {
488 status = "okay";
489 };
490
Stephen Warrenc04abb32012-05-11 17:03:26 -0600491 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600492 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600493 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
494 };
495
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600496 usb@c5008000 {
497 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600498 };
499
Venu Byravarasu40e8b3a2013-01-24 15:46:46 +0530500 usb-phy@c5004400 {
501 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
502 };
503
Wei Nic7294292012-09-21 16:54:58 +0800504 sdhci@c8000000 {
505 status = "okay";
506 power-gpios = <&gpio 86 0>; /* gpio PK6 */
507 bus-width = <4>;
508 };
509
Stephen Warrenc04abb32012-05-11 17:03:26 -0600510 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600511 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600512 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
513 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
514 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200515 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600516 };
517
518 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600519 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200520 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600521 };
522
Stephen Warren017a0102012-06-20 16:53:41 -0600523 regulators {
524 compatible = "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 vdd_5v0_reg: regulator@0 {
529 compatible = "regulator-fixed";
530 reg = <0>;
531 regulator-name = "vdd_5v0";
532 regulator-min-microvolt = <5000000>;
533 regulator-max-microvolt = <5000000>;
534 regulator-always-on;
535 };
536
537 regulator@1 {
538 compatible = "regulator-fixed";
539 reg = <1>;
540 regulator-name = "vdd_1v5";
541 regulator-min-microvolt = <1500000>;
542 regulator-max-microvolt = <1500000>;
543 gpio = <&pmic 0 0>;
544 };
545
546 regulator@2 {
547 compatible = "regulator-fixed";
548 reg = <2>;
549 regulator-name = "vdd_1v2";
550 regulator-min-microvolt = <1200000>;
551 regulator-max-microvolt = <1200000>;
552 gpio = <&pmic 1 0>;
553 enable-active-high;
554 };
555
556 regulator@3 {
557 compatible = "regulator-fixed";
558 reg = <3>;
559 regulator-name = "vdd_pnl";
560 regulator-min-microvolt = <2800000>;
561 regulator-max-microvolt = <2800000>;
562 gpio = <&gpio 22 0>; /* gpio PC6 */
563 enable-active-high;
564 };
565
566 regulator@4 {
567 compatible = "regulator-fixed";
568 reg = <4>;
569 regulator-name = "vdd_bl";
570 regulator-min-microvolt = <2800000>;
571 regulator-max-microvolt = <2800000>;
572 gpio = <&gpio 176 0>; /* gpio PW0 */
573 enable-active-high;
574 };
575 };
576
Stephen Warren797acf72012-01-11 16:09:57 -0700577 sound {
578 compatible = "nvidia,tegra-audio-wm8903-ventana",
579 "nvidia,tegra-audio-wm8903";
580 nvidia,model = "NVIDIA Tegra Ventana";
581
582 nvidia,audio-routing =
583 "Headphone Jack", "HPOUTR",
584 "Headphone Jack", "HPOUTL",
585 "Int Spk", "ROP",
586 "Int Spk", "RON",
587 "Int Spk", "LOP",
588 "Int Spk", "LON",
589 "Mic Jack", "MICBIAS",
590 "IN1L", "Mic Jack";
591
592 nvidia,i2s-controller = <&tegra_i2s1>;
593 nvidia,audio-codec = <&wm8903>;
594
595 nvidia,spkr-en-gpios = <&wm8903 2 0>;
596 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenc44e4382012-05-11 16:21:10 -0600597 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
Stephen Warren797acf72012-01-11 16:09:57 -0700598 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
599 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300600};