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Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +01001Atmel AT91 device tree bindings.
2================================
3
4PIT Timer required properties:
5- compatible: Should be "atmel,at91sam9260-pit"
6- reg: Should contain registers location and length
7- interrupts: Should contain interrupt for the PIT which is the IRQ line
8 shared across all System Controller members.
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +01009
Joachim Eastwood454c46d2012-10-28 18:31:07 +000010System Timer (ST) required properties:
11- compatible: Should be "atmel,at91rm9200-st"
12- reg: Should contain registers location and length
13- interrupts: Should contain interrupt for the ST which is the IRQ line
14 shared across all System Controller members.
15
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010016TC/TCLIB Timer required properties:
17- compatible: Should be "atmel,<chip>-pit".
18 <chip> can be "at91rm9200" or "at91sam9x5"
19- reg: Should contain registers location and length
20- interrupts: Should contain all interrupts for the TC block
21 Note that you can specify several interrupt cells if the TC
22 block has one interrupt per channel.
23
24Examples:
25
26One interrupt per TC block:
27 tcb0: timer@fff7c000 {
28 compatible = "atmel,at91rm9200-tcb";
29 reg = <0xfff7c000 0x100>;
30 interrupts = <18 4>;
31 };
32
33One interrupt per TC channel in a TC block:
34 tcb1: timer@fffdc000 {
35 compatible = "atmel,at91rm9200-tcb";
36 reg = <0xfffdc000 0x100>;
37 interrupts = <26 4 27 4 28 4>;
38 };
Jean-Christophe PLAGNIOL-VILLARDc8082d32012-03-03 03:16:27 +080039
40RSTC Reset Controller required properties:
41- compatible: Should be "atmel,<chip>-rstc".
42 <chip> can be "at91sam9260" or "at91sam9g45"
43- reg: Should contain registers location and length
44
45Example:
46
47 rstc@fffffd00 {
48 compatible = "atmel,at91sam9260-rstc";
49 reg = <0xfffffd00 0x10>;
50 };
Jean-Christophe PLAGNIOL-VILLARDa7776ec2012-03-02 20:54:37 +080051
52RAMC SDRAM/DDR Controller required properties:
53- compatible: Should be "atmel,at91sam9260-sdramc",
54 "atmel,at91sam9g45-ddramc",
55- reg: Should contain registers location and length
56 For at91sam9263 and at91sam9g45 you must specify 2 entries.
57
58Examples:
59
60 ramc0: ramc@ffffe800 {
61 compatible = "atmel,at91sam9g45-ddramc";
62 reg = <0xffffe800 0x200>;
63 };
64
65 ramc0: ramc@ffffe400 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe400 0x200
68 0xffffe600 0x200>;
69 };
Jean-Christophe PLAGNIOL-VILLARD82015c42012-03-02 21:01:00 +080070
71SHDWC Shutdown Controller
72
73required properties:
74- compatible: Should be "atmel,<chip>-shdwc".
75 <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
76- reg: Should contain registers location and length
77
78optional properties:
79- atmel,wakeup-mode: String, operation mode of the wakeup mode.
80 Supported values are: "none", "high", "low", "any".
81- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
82
83optional at91sam9260 properties:
84- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
85
86optional at91sam9rl properties:
87- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
88- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
89
90optional at91sam9x5 properties:
91- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
92
93Example:
94
95 rstc@fffffd00 {
96 compatible = "atmel,at91sam9260-rstc";
97 reg = <0xfffffd00 0x10>;
98 };