| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1997,1998 Russell King |
| 3 | * Copyright (C) 1999 ARM Limited |
| 4 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 5 | * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| Uwe Kleine-König | 3cdd544 | 2010-01-08 16:02:30 +0100 | [diff] [blame] | 12 | #ifndef __MACH_MX1_H__ |
| 13 | #define __MACH_MX1_H__ |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 14 | |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 15 | /* |
| 16 | * Memory map |
| 17 | */ |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 18 | #define MX1_IO_BASE_ADDR 0x00200000 |
| 19 | #define MX1_IO_SIZE SZ_1M |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 20 | |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 21 | #define MX1_CS0_PHYS 0x10000000 |
| 22 | #define MX1_CS0_SIZE 0x02000000 |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 23 | |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 24 | #define MX1_CS1_PHYS 0x12000000 |
| 25 | #define MX1_CS1_SIZE 0x01000000 |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 26 | |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 27 | #define MX1_CS2_PHYS 0x13000000 |
| 28 | #define MX1_CS2_SIZE 0x01000000 |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 29 | |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 30 | #define MX1_CS3_PHYS 0x14000000 |
| 31 | #define MX1_CS3_SIZE 0x01000000 |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 32 | |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 33 | #define MX1_CS4_PHYS 0x15000000 |
| 34 | #define MX1_CS4_SIZE 0x01000000 |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 35 | |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 36 | #define MX1_CS5_PHYS 0x16000000 |
| 37 | #define MX1_CS5_SIZE 0x01000000 |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 38 | |
| 39 | /* |
| 40 | * Register BASEs, based on OFFSETs |
| 41 | */ |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 42 | #define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) |
| 43 | #define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) |
| 44 | #define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) |
| 45 | #define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) |
| 46 | #define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) |
| 47 | #define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) |
| 48 | #define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) |
| 49 | #define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) |
| 50 | #define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) |
| 51 | #define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) |
| 52 | #define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) |
| 53 | #define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) |
| 54 | #define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) |
| Gwenhael Goavec-Merou | 40b2747 | 2011-02-23 16:58:37 +0000 | [diff] [blame] | 55 | #define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 56 | #define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) |
| 57 | #define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) |
| 58 | #define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) |
| 59 | #define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) |
| 60 | #define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) |
| Gwenhael Goavec-Merou | 40b2747 | 2011-02-23 16:58:37 +0000 | [diff] [blame] | 61 | #define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 62 | #define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) |
| 63 | #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) |
| 64 | #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) |
| 65 | #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) |
| Uwe Kleine-König | d485c7e | 2010-11-11 10:52:33 +0100 | [diff] [blame] | 66 | #define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) |
| 67 | #define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) |
| 68 | #define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) |
| 69 | #define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 70 | #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) |
| 71 | #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) |
| 72 | #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) |
| 73 | #define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) |
| 74 | #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 75 | |
| 76 | /* macro to get at IO space when running virtually */ |
| Uwe Kleine-König | a996314 | 2010-10-25 15:44:25 +0200 | [diff] [blame] | 77 | #define MX1_IO_P2V(x) IMX_IO_P2V(x) |
| Uwe Kleine-König | f5d7a13 | 2010-10-25 11:40:30 +0200 | [diff] [blame] | 78 | #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 79 | |
| 80 | /* fixed interrput numbers */ |
| Shawn Guo | 8842a9e | 2012-06-14 11:16:14 +0800 | [diff] [blame] | 81 | #include <asm/irq.h> |
| 82 | #define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0) |
| 83 | #define MX1_INT_CSI (NR_IRQS_LEGACY + 6) |
| 84 | #define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7) |
| 85 | #define MX1_DSPA_INT (NR_IRQS_LEGACY + 8) |
| 86 | #define MX1_COMP_INT (NR_IRQS_LEGACY + 9) |
| 87 | #define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10) |
| 88 | #define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11) |
| 89 | #define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12) |
| 90 | #define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13) |
| 91 | #define MX1_INT_LCDC (NR_IRQS_LEGACY + 14) |
| 92 | #define MX1_SIM_INT (NR_IRQS_LEGACY + 15) |
| 93 | #define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16) |
| 94 | #define MX1_RTC_INT (NR_IRQS_LEGACY + 17) |
| 95 | #define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18) |
| 96 | #define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19) |
| 97 | #define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20) |
| 98 | #define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21) |
| 99 | #define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22) |
| 100 | #define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23) |
| 101 | #define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24) |
| 102 | #define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25) |
| 103 | #define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26) |
| 104 | #define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27) |
| 105 | #define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28) |
| 106 | #define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29) |
| 107 | #define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30) |
| 108 | #define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31) |
| 109 | #define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32) |
| 110 | #define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33) |
| 111 | #define MX1_PWM_INT (NR_IRQS_LEGACY + 34) |
| 112 | #define MX1_SDHC_INT (NR_IRQS_LEGACY + 35) |
| 113 | #define MX1_INT_I2C (NR_IRQS_LEGACY + 39) |
| 114 | #define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40) |
| 115 | #define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41) |
| 116 | #define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42) |
| 117 | #define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43) |
| 118 | #define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44) |
| 119 | #define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45) |
| 120 | #define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46) |
| 121 | #define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47) |
| 122 | #define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48) |
| 123 | #define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49) |
| 124 | #define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50) |
| 125 | #define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51) |
| 126 | #define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52) |
| 127 | #define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53) |
| 128 | #define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55) |
| 129 | #define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56) |
| 130 | #define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57) |
| 131 | #define MX1_TIM2_INT (NR_IRQS_LEGACY + 58) |
| 132 | #define MX1_TIM1_INT (NR_IRQS_LEGACY + 59) |
| 133 | #define MX1_DMA_ERR (NR_IRQS_LEGACY + 60) |
| 134 | #define MX1_DMA_INT (NR_IRQS_LEGACY + 61) |
| 135 | #define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62) |
| 136 | #define MX1_WDT_INT (NR_IRQS_LEGACY + 63) |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 137 | |
| Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 138 | /* DMA */ |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 139 | #define MX1_DMA_REQ_UART3_T 2 |
| 140 | #define MX1_DMA_REQ_UART3_R 3 |
| 141 | #define MX1_DMA_REQ_SSI2_T 4 |
| 142 | #define MX1_DMA_REQ_SSI2_R 5 |
| 143 | #define MX1_DMA_REQ_CSI_STAT 6 |
| 144 | #define MX1_DMA_REQ_CSI_R 7 |
| 145 | #define MX1_DMA_REQ_MSHC 8 |
| 146 | #define MX1_DMA_REQ_DSPA_DCT_DOUT 9 |
| 147 | #define MX1_DMA_REQ_DSPA_DCT_DIN 10 |
| 148 | #define MX1_DMA_REQ_DSPA_MAC 11 |
| 149 | #define MX1_DMA_REQ_EXT 12 |
| 150 | #define MX1_DMA_REQ_SDHC 13 |
| 151 | #define MX1_DMA_REQ_SPI1_R 14 |
| 152 | #define MX1_DMA_REQ_SPI1_T 15 |
| 153 | #define MX1_DMA_REQ_SSI_T 16 |
| 154 | #define MX1_DMA_REQ_SSI_R 17 |
| 155 | #define MX1_DMA_REQ_ASP_DAC 18 |
| 156 | #define MX1_DMA_REQ_ASP_ADC 19 |
| 157 | #define MX1_DMA_REQ_USP_EP(x) (20 + (x)) |
| 158 | #define MX1_DMA_REQ_SPI2_R 26 |
| 159 | #define MX1_DMA_REQ_SPI2_T 27 |
| 160 | #define MX1_DMA_REQ_UART2_T 28 |
| 161 | #define MX1_DMA_REQ_UART2_R 29 |
| 162 | #define MX1_DMA_REQ_UART1_T 30 |
| 163 | #define MX1_DMA_REQ_UART1_R 31 |
| 164 | |
| 165 | /* |
| 166 | * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS |
| 167 | * to not break drivers/usb/gadget/imx_udc. Should go |
| 168 | * away after this driver uses the new name. |
| 169 | */ |
| Uwe Kleine-König | e083000 | 2010-11-02 10:03:51 +0100 | [diff] [blame] | 170 | #define USBD_INT0 MX1_INT_USBD0 |
| Uwe Kleine-König | 7d58289 | 2010-01-11 11:37:24 +0100 | [diff] [blame] | 171 | |
| Uwe Kleine-König | 3cdd544 | 2010-01-08 16:02:30 +0100 | [diff] [blame] | 172 | #endif /* ifndef __MACH_MX1_H__ */ |