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Chris Zankel5a0015d2005-06-23 22:01:16 -07001/*
2 * linux/arch/xtensa/kernel/irq.c
3 *
4 * Xtensa built-in interrupt controller and some generic functions copied
5 * from i386.
6 *
Chris Zankelfd43fe12006-12-10 02:18:47 -08007 * Copyright (C) 2002 - 2006 Tensilica, Inc.
Chris Zankel5a0015d2005-06-23 22:01:16 -07008 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
9 *
10 *
11 * Chris Zankel <chris@zankel.net>
12 * Kevin Chea
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/seq_file.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/kernel_stat.h>
21
22#include <asm/uaccess.h>
23#include <asm/platform.h>
24
Chris Zankel5a0015d2005-06-23 22:01:16 -070025static unsigned int cached_irq_mask;
26
27atomic_t irq_err_count;
28
29/*
Chris Zankel5a0015d2005-06-23 22:01:16 -070030 * do_IRQ handles all normal device IRQ's (the special
31 * SMP cross-CPU interrupts have their own specific
32 * handlers).
33 */
34
Chris Zankelfd43fe12006-12-10 02:18:47 -080035asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
Chris Zankel5a0015d2005-06-23 22:01:16 -070036{
Chris Zankelfd43fe12006-12-10 02:18:47 -080037 struct pt_regs *old_regs = set_irq_regs(regs);
Chris Zankelfd43fe12006-12-10 02:18:47 -080038
39 if (irq >= NR_IRQS) {
40 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
Harvey Harrison1b532c62008-07-30 12:48:54 -070041 __func__, irq);
Chris Zankelfd43fe12006-12-10 02:18:47 -080042 }
43
Chris Zankel5a0015d2005-06-23 22:01:16 -070044 irq_enter();
45
46#ifdef CONFIG_DEBUG_STACKOVERFLOW
47 /* Debugging check for stack overflow: is there less than 1KB free? */
48 {
49 unsigned long sp;
50
51 __asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp));
52 sp &= THREAD_SIZE - 1;
53
54 if (unlikely(sp < (sizeof(thread_info) + 1024)))
55 printk("Stack overflow in do_IRQ: %ld\n",
56 sp - sizeof(struct thread_info));
57 }
58#endif
Thomas Gleixner495e0c72011-02-06 22:10:52 +010059 generic_handle_irq(irq);
Chris Zankel5a0015d2005-06-23 22:01:16 -070060
61 irq_exit();
Chris Zankelfd43fe12006-12-10 02:18:47 -080062 set_irq_regs(old_regs);
Chris Zankel5a0015d2005-06-23 22:01:16 -070063}
64
Thomas Gleixner47a5d9d2011-03-24 18:28:40 +010065int arch_show_interrupts(struct seq_file *p, int prec)
Chris Zankel5a0015d2005-06-23 22:01:16 -070066{
Thomas Gleixner47a5d9d2011-03-24 18:28:40 +010067 int j;
Chris Zankel5a0015d2005-06-23 22:01:16 -070068
Thomas Gleixner47a5d9d2011-03-24 18:28:40 +010069 seq_printf(p, "%*s: ", prec, "NMI");
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", nmi_count(j));
72 seq_putc(p, '\n');
73 seq_printf(p, "%*s: ", prec, "ERR");
74 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
Chris Zankel5a0015d2005-06-23 22:01:16 -070075 return 0;
76}
Chris Zankel5a0015d2005-06-23 22:01:16 -070077
Thomas Gleixner495e0c72011-02-06 22:10:52 +010078static void xtensa_irq_mask(struct irq_chip *d)
Chris Zankel5a0015d2005-06-23 22:01:16 -070079{
Thomas Gleixner495e0c72011-02-06 22:10:52 +010080 cached_irq_mask &= ~(1 << d->irq);
Chris Zankel5a0015d2005-06-23 22:01:16 -070081 set_sr (cached_irq_mask, INTENABLE);
82}
83
Thomas Gleixner495e0c72011-02-06 22:10:52 +010084static void xtensa_irq_unmask(struct irq_chip *d)
Chris Zankel5a0015d2005-06-23 22:01:16 -070085{
Thomas Gleixner495e0c72011-02-06 22:10:52 +010086 cached_irq_mask |= 1 << d->irq;
Chris Zankel5a0015d2005-06-23 22:01:16 -070087 set_sr (cached_irq_mask, INTENABLE);
88}
89
Thomas Gleixner495e0c72011-02-06 22:10:52 +010090static void xtensa_irq_enable(struct irq_chip *d)
Johannes Weiner4c0d2142009-03-04 16:21:31 +010091{
Thomas Gleixner495e0c72011-02-06 22:10:52 +010092 variant_irq_enable(d->irq);
93 xtensa_irq_unmask(d->irq);
Johannes Weiner4c0d2142009-03-04 16:21:31 +010094}
95
Thomas Gleixner495e0c72011-02-06 22:10:52 +010096static void xtensa_irq_disable(struct irq_chip *d)
Johannes Weiner4c0d2142009-03-04 16:21:31 +010097{
Thomas Gleixner495e0c72011-02-06 22:10:52 +010098 xtensa_irq_mask(d->irq);
99 variant_irq_disable(d->irq);
Johannes Weiner4c0d2142009-03-04 16:21:31 +0100100}
101
Thomas Gleixner495e0c72011-02-06 22:10:52 +0100102static void xtensa_irq_ack(struct irq_chip *d)
Chris Zankel5a0015d2005-06-23 22:01:16 -0700103{
Thomas Gleixner495e0c72011-02-06 22:10:52 +0100104 set_sr(1 << d->irq, INTCLEAR);
Chris Zankel5a0015d2005-06-23 22:01:16 -0700105}
106
Thomas Gleixner495e0c72011-02-06 22:10:52 +0100107static int xtensa_irq_retrigger(struct irq_chip *d)
Chris Zankel5a0015d2005-06-23 22:01:16 -0700108{
Thomas Gleixner495e0c72011-02-06 22:10:52 +0100109 set_sr (1 << d->irq, INTSET);
Chris Zankelfd43fe12006-12-10 02:18:47 -0800110 return 1;
Chris Zankel5a0015d2005-06-23 22:01:16 -0700111}
112
Chris Zankel5a0015d2005-06-23 22:01:16 -0700113
Chris Zankelfd43fe12006-12-10 02:18:47 -0800114static struct irq_chip xtensa_irq_chip = {
115 .name = "xtensa",
Thomas Gleixner495e0c72011-02-06 22:10:52 +0100116 .irq_enable = xtensa_irq_enable,
117 .irq_disable = xtensa_irq_disable,
118 .irq_mask = xtensa_irq_mask,
119 .irq_unmask = xtensa_irq_unmask,
120 .irq_ack = xtensa_irq_ack,
121 .irq_retrigger = xtensa_irq_retrigger,
Chris Zankelfd43fe12006-12-10 02:18:47 -0800122};
Chris Zankel5a0015d2005-06-23 22:01:16 -0700123
124void __init init_IRQ(void)
125{
Chris Zankelfd43fe12006-12-10 02:18:47 -0800126 int index;
Chris Zankel5a0015d2005-06-23 22:01:16 -0700127
Chris Zankelfd43fe12006-12-10 02:18:47 -0800128 for (index = 0; index < XTENSA_NR_IRQS; index++) {
129 int mask = 1 << index;
130
131 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
Thomas Gleixner610e1752011-03-24 14:58:43 +0100132 irq_set_chip_and_handler(index, &xtensa_irq_chip,
Chris Zankelfd43fe12006-12-10 02:18:47 -0800133 handle_simple_irq);
134
135 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
Thomas Gleixner610e1752011-03-24 14:58:43 +0100136 irq_set_chip_and_handler(index, &xtensa_irq_chip,
Chris Zankelfd43fe12006-12-10 02:18:47 -0800137 handle_edge_irq);
138
139 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
Thomas Gleixner610e1752011-03-24 14:58:43 +0100140 irq_set_chip_and_handler(index, &xtensa_irq_chip,
Chris Zankelfd43fe12006-12-10 02:18:47 -0800141 handle_level_irq);
142
143 else if (mask & XCHAL_INTTYPE_MASK_TIMER)
Thomas Gleixner610e1752011-03-24 14:58:43 +0100144 irq_set_chip_and_handler(index, &xtensa_irq_chip,
Chris Zankelfd43fe12006-12-10 02:18:47 -0800145 handle_edge_irq);
146
147 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
148 /* XCHAL_INTTYPE_MASK_NMI */
149
Thomas Gleixner610e1752011-03-24 14:58:43 +0100150 irq_set_chip_and_handler(index, &xtensa_irq_chip,
Chris Zankelfd43fe12006-12-10 02:18:47 -0800151 handle_level_irq);
152 }
Chris Zankel5a0015d2005-06-23 22:01:16 -0700153
154 cached_irq_mask = 0;
Daniel Glöckner1beee212009-05-05 15:03:21 +0000155
156 variant_init_irq();
Chris Zankel5a0015d2005-06-23 22:01:16 -0700157}