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review.evervolv.com / android_kernel_oneplus_msm8996 / 497ae1747b8c52fde4ab7e9987326ca43886b652 / . / arch / arm / boot / dts / imx6q.dtsi
blob: 1d07be2530b5610cbbb35fe65fa6057b5130cb5e [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a9";
49 reg = <2>;
50 next-level-cache = <&L2>;
51 };
52
53 cpu@3 {
54 compatible = "arm,cortex-a9";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 interrupt-controller;
66 reg = <0x00a01000 0x1000>,
67 <0x00a00100 0x100>;
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 ckil {
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
77 };
78
79 ckih1 {
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
95 ranges;
96
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
100 };
101
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]102 gpmi-nand@00112000 {
103 compatible = "fsl,imx6q-gpmi-nand";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
107 reg-names = "gpmi-nand", "bch";
108 interrupts = <0 13 0x04>, <0 15 0x04>;
109 interrupt-names = "gpmi-dma", "bch";
110 fsl,gpmi-dma-channel = <0>;
111 status = "disabled";
112 };
113
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]114 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]115 compatible = "arm,cortex-a9-twd-timer";
116 reg = <0x00a00600 0x20>;
117 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]118 };
119
120 L2: l2-cache@00a02000 {
121 compatible = "arm,pl310-cache";
122 reg = <0x00a02000 0x1000>;
123 interrupts = <0 92 0x04>;
124 cache-unified;
125 cache-level = <2>;
126 };
127
128 aips-bus@02000000 { /* AIPS1 */
129 compatible = "fsl,aips-bus", "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0x02000000 0x100000>;
133 ranges;
134
135 spba-bus@02000000 {
136 compatible = "fsl,spba-bus", "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 reg = <0x02000000 0x40000>;
140 ranges;
141
142 spdif@02004000 {
143 reg = <0x02004000 0x4000>;
144 interrupts = <0 52 0x04>;
145 };
146
147 ecspi@02008000 { /* eCSPI1 */
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
151 reg = <0x02008000 0x4000>;
152 interrupts = <0 31 0x04>;
153 status = "disabled";
154 };
155
156 ecspi@0200c000 { /* eCSPI2 */
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
160 reg = <0x0200c000 0x4000>;
161 interrupts = <0 32 0x04>;
162 status = "disabled";
163 };
164
165 ecspi@02010000 { /* eCSPI3 */
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 0x04>;
171 status = "disabled";
172 };
173
174 ecspi@02014000 { /* eCSPI4 */
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02014000 0x4000>;
179 interrupts = <0 34 0x04>;
180 status = "disabled";
181 };
182
183 ecspi@02018000 { /* eCSPI5 */
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
187 reg = <0x02018000 0x4000>;
188 interrupts = <0 35 0x04>;
189 status = "disabled";
190 };
191
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]192 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]193 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
194 reg = <0x02020000 0x4000>;
195 interrupts = <0 26 0x04>;
196 status = "disabled";
197 };
198
199 esai@02024000 {
200 reg = <0x02024000 0x4000>;
201 interrupts = <0 51 0x04>;
202 };
203
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]204 ssi1: ssi@02028000 {
205 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]206 reg = <0x02028000 0x4000>;
207 interrupts = <0 46 0x04>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]208 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <38 37>;
210 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]211 };
212
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]213 ssi2: ssi@0202c000 {
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]215 reg = <0x0202c000 0x4000>;
216 interrupts = <0 47 0x04>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]217 fsl,fifo-depth = <15>;
218 fsl,ssi-dma-events = <42 41>;
219 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]220 };
221
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]222 ssi3: ssi@02030000 {
223 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]224 reg = <0x02030000 0x4000>;
225 interrupts = <0 48 0x04>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <46 45>;
228 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]229 };
230
231 asrc@02034000 {
232 reg = <0x02034000 0x4000>;
233 interrupts = <0 50 0x04>;
234 };
235
236 spba@0203c000 {
237 reg = <0x0203c000 0x4000>;
238 };
239 };
240
241 vpu@02040000 {
242 reg = <0x02040000 0x3c000>;
243 interrupts = <0 3 0x04 0 12 0x04>;
244 };
245
246 aipstz@0207c000 { /* AIPSTZ1 */
247 reg = <0x0207c000 0x4000>;
248 };
249
250 pwm@02080000 { /* PWM1 */
251 reg = <0x02080000 0x4000>;
252 interrupts = <0 83 0x04>;
253 };
254
255 pwm@02084000 { /* PWM2 */
256 reg = <0x02084000 0x4000>;
257 interrupts = <0 84 0x04>;
258 };
259
260 pwm@02088000 { /* PWM3 */
261 reg = <0x02088000 0x4000>;
262 interrupts = <0 85 0x04>;
263 };
264
265 pwm@0208c000 { /* PWM4 */
266 reg = <0x0208c000 0x4000>;
267 interrupts = <0 86 0x04>;
268 };
269
270 flexcan@02090000 { /* CAN1 */
271 reg = <0x02090000 0x4000>;
272 interrupts = <0 110 0x04>;
273 };
274
275 flexcan@02094000 { /* CAN2 */
276 reg = <0x02094000 0x4000>;
277 interrupts = <0 111 0x04>;
278 };
279
280 gpt@02098000 {
281 compatible = "fsl,imx6q-gpt";
282 reg = <0x02098000 0x4000>;
283 interrupts = <0 55 0x04>;
284 };
285
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]286 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]287 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]288 reg = <0x0209c000 0x4000>;
289 interrupts = <0 66 0x04 0 67 0x04>;
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]293 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]294 };
295
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]296 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]297 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]298 reg = <0x020a0000 0x4000>;
299 interrupts = <0 68 0x04 0 69 0x04>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]303 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]304 };
305
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]306 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 reg = <0x020a4000 0x4000>;
309 interrupts = <0 70 0x04 0 71 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]313 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]314 };
315
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]316 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]318 reg = <0x020a8000 0x4000>;
319 interrupts = <0 72 0x04 0 73 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]323 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]324 };
325
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]326 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]328 reg = <0x020ac000 0x4000>;
329 interrupts = <0 74 0x04 0 75 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]333 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]336 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 reg = <0x020b0000 0x4000>;
339 interrupts = <0 76 0x04 0 77 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]343 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]346 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 reg = <0x020b4000 0x4000>;
349 interrupts = <0 78 0x04 0 79 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]353 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 };
355
356 kpp@020b8000 {
357 reg = <0x020b8000 0x4000>;
358 interrupts = <0 82 0x04>;
359 };
360
361 wdog@020bc000 { /* WDOG1 */
362 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
363 reg = <0x020bc000 0x4000>;
364 interrupts = <0 80 0x04>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]365 };
366
367 wdog@020c0000 { /* WDOG2 */
368 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
369 reg = <0x020c0000 0x4000>;
370 interrupts = <0 81 0x04>;
371 status = "disabled";
372 };
373
374 ccm@020c4000 {
375 compatible = "fsl,imx6q-ccm";
376 reg = <0x020c4000 0x4000>;
377 interrupts = <0 87 0x04 0 88 0x04>;
378 };
379
380 anatop@020c8000 {
381 compatible = "fsl,imx6q-anatop";
382 reg = <0x020c8000 0x1000>;
383 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]384
385 regulator-1p1@110 {
386 compatible = "fsl,anatop-regulator";
387 regulator-name = "vdd1p1";
388 regulator-min-microvolt = <800000>;
389 regulator-max-microvolt = <1375000>;
390 regulator-always-on;
391 anatop-reg-offset = <0x110>;
392 anatop-vol-bit-shift = <8>;
393 anatop-vol-bit-width = <5>;
394 anatop-min-bit-val = <4>;
395 anatop-min-voltage = <800000>;
396 anatop-max-voltage = <1375000>;
397 };
398
399 regulator-3p0@120 {
400 compatible = "fsl,anatop-regulator";
401 regulator-name = "vdd3p0";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <3150000>;
404 regulator-always-on;
405 anatop-reg-offset = <0x120>;
406 anatop-vol-bit-shift = <8>;
407 anatop-vol-bit-width = <5>;
408 anatop-min-bit-val = <0>;
409 anatop-min-voltage = <2625000>;
410 anatop-max-voltage = <3400000>;
411 };
412
413 regulator-2p5@130 {
414 compatible = "fsl,anatop-regulator";
415 regulator-name = "vdd2p5";
416 regulator-min-microvolt = <2000000>;
417 regulator-max-microvolt = <2750000>;
418 regulator-always-on;
419 anatop-reg-offset = <0x130>;
420 anatop-vol-bit-shift = <8>;
421 anatop-vol-bit-width = <5>;
422 anatop-min-bit-val = <0>;
423 anatop-min-voltage = <2000000>;
424 anatop-max-voltage = <2750000>;
425 };
426
427 regulator-vddcore@140 {
428 compatible = "fsl,anatop-regulator";
429 regulator-name = "cpu";
430 regulator-min-microvolt = <725000>;
431 regulator-max-microvolt = <1450000>;
432 regulator-always-on;
433 anatop-reg-offset = <0x140>;
434 anatop-vol-bit-shift = <0>;
435 anatop-vol-bit-width = <5>;
436 anatop-min-bit-val = <1>;
437 anatop-min-voltage = <725000>;
438 anatop-max-voltage = <1450000>;
439 };
440
441 regulator-vddpu@140 {
442 compatible = "fsl,anatop-regulator";
443 regulator-name = "vddpu";
444 regulator-min-microvolt = <725000>;
445 regulator-max-microvolt = <1450000>;
446 regulator-always-on;
447 anatop-reg-offset = <0x140>;
448 anatop-vol-bit-shift = <9>;
449 anatop-vol-bit-width = <5>;
450 anatop-min-bit-val = <1>;
451 anatop-min-voltage = <725000>;
452 anatop-max-voltage = <1450000>;
453 };
454
455 regulator-vddsoc@140 {
456 compatible = "fsl,anatop-regulator";
457 regulator-name = "vddsoc";
458 regulator-min-microvolt = <725000>;
459 regulator-max-microvolt = <1450000>;
460 regulator-always-on;
461 anatop-reg-offset = <0x140>;
462 anatop-vol-bit-shift = <18>;
463 anatop-vol-bit-width = <5>;
464 anatop-min-bit-val = <1>;
465 anatop-min-voltage = <725000>;
466 anatop-max-voltage = <1450000>;
467 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]468 };
469
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]470 usbphy1: usbphy@020c9000 {
471 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]472 reg = <0x020c9000 0x1000>;
473 interrupts = <0 44 0x04>;
474 };
475
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]476 usbphy2: usbphy@020ca000 {
477 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]478 reg = <0x020ca000 0x1000>;
479 interrupts = <0 45 0x04>;
480 };
481
482 snvs@020cc000 {
483 reg = <0x020cc000 0x4000>;
484 interrupts = <0 19 0x04 0 20 0x04>;
485 };
486
487 epit@020d0000 { /* EPIT1 */
488 reg = <0x020d0000 0x4000>;
489 interrupts = <0 56 0x04>;
490 };
491
492 epit@020d4000 { /* EPIT2 */
493 reg = <0x020d4000 0x4000>;
494 interrupts = <0 57 0x04>;
495 };
496
497 src@020d8000 {
498 compatible = "fsl,imx6q-src";
499 reg = <0x020d8000 0x4000>;
500 interrupts = <0 91 0x04 0 96 0x04>;
501 };
502
503 gpc@020dc000 {
504 compatible = "fsl,imx6q-gpc";
505 reg = <0x020dc000 0x4000>;
506 interrupts = <0 89 0x04 0 90 0x04>;
507 };
508
509 iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]510 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]511 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]512
513 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]514 audmux {
515 pinctrl_audmux_1: audmux-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]516 fsl,pins = <
517 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
518 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
519 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
520 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
521 >;
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]522 };
523 };
524
Shawn Guo52ccd492012-08-11 11:17:42 +0800[diff] [blame]525 ecspi1 {
526 pinctrl_ecspi1_1: ecspi1grp-1 {
527 fsl,pins = <
528 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
529 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
530 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
531 >;
532 };
533 };
534
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]535 enet {
536 pinctrl_enet_1: enetgrp-1 {
537 fsl,pins = <
538 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
539 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
540 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
541 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
542 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
543 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
544 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
545 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
546 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
547 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
548 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
549 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
550 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
551 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
552 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
553 >;
554 };
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]555
556 pinctrl_enet_2: enetgrp-2 {
557 fsl,pins = <
558 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
559 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
560 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
561 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
562 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
563 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
564 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
565 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
566 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
567 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
568 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
569 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
570 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
571 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
572 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
573 >;
574 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]575 };
576
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]577 gpmi-nand {
578 pinctrl_gpmi_nand_1: gpmi-nand-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]579 fsl,pins = <
580 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
581 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
582 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
583 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
584 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
585 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
586 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
587 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
588 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
589 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
590 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
591 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
592 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
593 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
594 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
595 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
596 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
597 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
598 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
599 >;
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]600 };
601 };
602
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]603 i2c1 {
604 pinctrl_i2c1_1: i2c1grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]605 fsl,pins = <
606 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
607 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
608 >;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]609 };
610 };
611
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame^]612 uart1 {
613 pinctrl_uart1_1: uart1grp-1 {
614 fsl,pins = <
615 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
616 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
617 >;
618 };
619 };
620
Shawn Guoe30ba892012-08-11 12:33:51 +0800[diff] [blame]621 uart2 {
622 pinctrl_uart2_1: uart2grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]623 fsl,pins = <
624 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
625 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
626 >;
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]627 };
628 };
629
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]630 uart4 {
631 pinctrl_uart4_1: uart4grp-1 {
632 fsl,pins = <
633 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
634 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
635 >;
636 };
637 };
638
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame^]639 usdhc2 {
640 pinctrl_usdhc2_1: usdhc2grp-1 {
641 fsl,pins = <
642 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
643 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
644 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
645 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
646 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
647 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
648 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
649 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
650 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
651 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
652 >;
653 };
654 };
655
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]656 usdhc3 {
657 pinctrl_usdhc3_1: usdhc3grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]658 fsl,pins = <
659 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
660 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
661 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
662 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
663 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
664 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
665 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
666 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
667 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
668 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
669 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]670 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]671
672 pinctrl_usdhc3_2: usdhc3grp-2 {
673 fsl,pins = <
674 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
675 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
676 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
677 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
678 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
679 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
680 >;
681 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]682 };
683
684 usdhc4 {
685 pinctrl_usdhc4_1: usdhc4grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]686 fsl,pins = <
687 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
688 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
689 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
690 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
691 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
692 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
693 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
694 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
695 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
696 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
697 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]698 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]699
700 pinctrl_usdhc4_2: usdhc4grp-2 {
701 fsl,pins = <
702 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
703 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
704 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
705 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
706 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
707 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
708 >;
709 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]710 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]711 };
712
713 dcic@020e4000 { /* DCIC1 */
714 reg = <0x020e4000 0x4000>;
715 interrupts = <0 124 0x04>;
716 };
717
718 dcic@020e8000 { /* DCIC2 */
719 reg = <0x020e8000 0x4000>;
720 interrupts = <0 125 0x04>;
721 };
722
723 sdma@020ec000 {
724 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
725 reg = <0x020ec000 0x4000>;
726 interrupts = <0 2 0x04>;
727 };
728 };
729
730 aips-bus@02100000 { /* AIPS2 */
731 compatible = "fsl,aips-bus", "simple-bus";
732 #address-cells = <1>;
733 #size-cells = <1>;
734 reg = <0x02100000 0x100000>;
735 ranges;
736
737 caam@02100000 {
738 reg = <0x02100000 0x40000>;
739 interrupts = <0 105 0x04 0 106 0x04>;
740 };
741
742 aipstz@0217c000 { /* AIPSTZ2 */
743 reg = <0x0217c000 0x4000>;
744 };
745
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]746 usb@02184000 { /* USB OTG */
747 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
748 reg = <0x02184000 0x200>;
749 interrupts = <0 43 0x04>;
750 fsl,usbphy = <&usbphy1>;
751 status = "disabled";
752 };
753
754 usb@02184200 { /* USB1 */
755 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
756 reg = <0x02184200 0x200>;
757 interrupts = <0 40 0x04>;
758 fsl,usbphy = <&usbphy2>;
759 status = "disabled";
760 };
761
762 usb@02184400 { /* USB2 */
763 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
764 reg = <0x02184400 0x200>;
765 interrupts = <0 41 0x04>;
766 status = "disabled";
767 };
768
769 usb@02184600 { /* USB3 */
770 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
771 reg = <0x02184600 0x200>;
772 interrupts = <0 42 0x04>;
773 status = "disabled";
774 };
775
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]776 ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]777 compatible = "fsl,imx6q-fec";
778 reg = <0x02188000 0x4000>;
779 interrupts = <0 118 0x04 0 119 0x04>;
780 status = "disabled";
781 };
782
783 mlb@0218c000 {
784 reg = <0x0218c000 0x4000>;
785 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
786 };
787
788 usdhc@02190000 { /* uSDHC1 */
789 compatible = "fsl,imx6q-usdhc";
790 reg = <0x02190000 0x4000>;
791 interrupts = <0 22 0x04>;
792 status = "disabled";
793 };
794
795 usdhc@02194000 { /* uSDHC2 */
796 compatible = "fsl,imx6q-usdhc";
797 reg = <0x02194000 0x4000>;
798 interrupts = <0 23 0x04>;
799 status = "disabled";
800 };
801
802 usdhc@02198000 { /* uSDHC3 */
803 compatible = "fsl,imx6q-usdhc";
804 reg = <0x02198000 0x4000>;
805 interrupts = <0 24 0x04>;
806 status = "disabled";
807 };
808
809 usdhc@0219c000 { /* uSDHC4 */
810 compatible = "fsl,imx6q-usdhc";
811 reg = <0x0219c000 0x4000>;
812 interrupts = <0 25 0x04>;
813 status = "disabled";
814 };
815
816 i2c@021a0000 { /* I2C1 */
817 #address-cells = <1>;
818 #size-cells = <0>;
819 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
820 reg = <0x021a0000 0x4000>;
821 interrupts = <0 36 0x04>;
822 status = "disabled";
823 };
824
825 i2c@021a4000 { /* I2C2 */
826 #address-cells = <1>;
827 #size-cells = <0>;
828 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
829 reg = <0x021a4000 0x4000>;
830 interrupts = <0 37 0x04>;
831 status = "disabled";
832 };
833
834 i2c@021a8000 { /* I2C3 */
835 #address-cells = <1>;
836 #size-cells = <0>;
837 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
838 reg = <0x021a8000 0x4000>;
839 interrupts = <0 38 0x04>;
840 status = "disabled";
841 };
842
843 romcp@021ac000 {
844 reg = <0x021ac000 0x4000>;
845 };
846
847 mmdc@021b0000 { /* MMDC0 */
848 compatible = "fsl,imx6q-mmdc";
849 reg = <0x021b0000 0x4000>;
850 };
851
852 mmdc@021b4000 { /* MMDC1 */
853 reg = <0x021b4000 0x4000>;
854 };
855
856 weim@021b8000 {
857 reg = <0x021b8000 0x4000>;
858 interrupts = <0 14 0x04>;
859 };
860
861 ocotp@021bc000 {
862 reg = <0x021bc000 0x4000>;
863 };
864
865 ocotp@021c0000 {
866 reg = <0x021c0000 0x4000>;
867 interrupts = <0 21 0x04>;
868 };
869
870 tzasc@021d0000 { /* TZASC1 */
871 reg = <0x021d0000 0x4000>;
872 interrupts = <0 108 0x04>;
873 };
874
875 tzasc@021d4000 { /* TZASC2 */
876 reg = <0x021d4000 0x4000>;
877 interrupts = <0 109 0x04>;
878 };
879
880 audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]881 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]882 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]883 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]884 };
885
886 mipi@021dc000 { /* MIPI-CSI */
887 reg = <0x021dc000 0x4000>;
888 };
889
890 mipi@021e0000 { /* MIPI-DSI */
891 reg = <0x021e0000 0x4000>;
892 };
893
894 vdoa@021e4000 {
895 reg = <0x021e4000 0x4000>;
896 interrupts = <0 18 0x04>;
897 };
898
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]899 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]900 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
901 reg = <0x021e8000 0x4000>;
902 interrupts = <0 27 0x04>;
903 status = "disabled";
904 };
905
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]906 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]907 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
908 reg = <0x021ec000 0x4000>;
909 interrupts = <0 28 0x04>;
910 status = "disabled";
911 };
912
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]913 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]914 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
915 reg = <0x021f0000 0x4000>;
916 interrupts = <0 29 0x04>;
917 status = "disabled";
918 };
919
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]920 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]921 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
922 reg = <0x021f4000 0x4000>;
923 interrupts = <0 30 0x04>;
924 status = "disabled";
925 };
926 };
927 };
928};