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Michal Simek4f0f2342013-03-20 10:46:01 +01001Cadence TTC - Triple Timer Counter
2
3Required properties:
4- compatible : Should be "cdns,ttc".
5- reg : Specifies base physical address and size of the registers.
6- interrupts : A list of 3 interrupts; one per timer channel.
7- clocks: phandle to the source clock
8
9Example:
10
11ttc0: ttc0@f8001000 {
12 interrupt-parent = <&intc>;
13 interrupts = < 0 10 4 0 11 4 0 12 4 >;
14 compatible = "cdns,ttc";
15 reg = <0xF8001000 0x1000>;
16 clocks = <&cpu_clk 3>;
17};