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review.evervolv.com / android_kernel_oneplus_msm8996 / 515a828f773ba7389d77db90b980565382ece977 / . / drivers / pinctrl / sh-pfc / pfc-r8a73a4.c
blob: 8a5288c99a837a37dc078801fe38d66f6eee3a07 [file] [log] [blame]
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1/*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]20#include <linux/io.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]21#include <linux/kernel.h>
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]22#include <linux/pinctrl/pinconf-generic.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]23#include <mach/irqs.h>
24#include <mach/r8a73a4.h>
25
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]26#include "core.h"
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]27#include "sh_pfc.h"
28
29#define CPU_ALL_PORT(fn, pfx, sfx) \
30 /* Port0 - Port30 */ \
31 PORT_10(fn, pfx, sfx), \
32 PORT_10(fn, pfx##1, sfx), \
33 PORT_10(fn, pfx##2, sfx), \
34 PORT_1(fn, pfx##30, sfx), \
35 /* Port32 - Port40 */ \
36 PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
37 PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
38 PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
39 PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
40 PORT_1(fn, pfx##40, sfx), \
41 /* Port64 - Port85 */ \
42 PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
43 PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
44 PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
45 PORT_10(fn, pfx##7, sfx), \
46 PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
47 PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
48 PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
49 /* Port96 - Port126 */ \
50 PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
51 PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
52 PORT_10(fn, pfx##10, sfx), \
53 PORT_10(fn, pfx##11, sfx), \
54 PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
55 PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
56 PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
57 PORT_1(fn, pfx##126, sfx), \
58 /* Port128 - Port134 */ \
59 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
60 PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
61 PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
62 PORT_1(fn, pfx##134, sfx), \
63 /* Port160 - Port178 */ \
64 PORT_10(fn, pfx##16, sfx), \
65 PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
66 PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
67 PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
68 PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
69 PORT_1(fn, pfx##178, sfx), \
70 /* Port192 - Port222 */ \
71 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
72 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
73 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
74 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
75 PORT_10(fn, pfx##20, sfx), \
76 PORT_10(fn, pfx##21, sfx), \
77 PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
78 PORT_1(fn, pfx##222, sfx), \
79 /* Port224 - Port250 */ \
80 PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
81 PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
82 PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
83 PORT_10(fn, pfx##23, sfx), \
84 PORT_10(fn, pfx##24, sfx), \
85 PORT_1(fn, pfx##250, sfx), \
86 /* Port256 - Port283 */ \
87 PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
88 PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
89 PORT_10(fn, pfx##26, sfx), \
90 PORT_10(fn, pfx##27, sfx), \
91 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
92 PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
93 /* Port288 - Port308 */ \
94 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
95 PORT_10(fn, pfx##29, sfx), \
96 PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
97 PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
98 PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
99 PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
100 PORT_1(fn, pfx##308, sfx), \
101 /* Port320 - Port329 */ \
102 PORT_10(fn, pfx##32, sfx)
103
104
105enum {
106 PINMUX_RESERVED = 0,
107
108 /* PORT0_DATA -> PORT329_DATA */
109 PINMUX_DATA_BEGIN,
110 PORT_ALL(DATA),
111 PINMUX_DATA_END,
112
113 /* PORT0_IN -> PORT329_IN */
114 PINMUX_INPUT_BEGIN,
115 PORT_ALL(IN),
116 PINMUX_INPUT_END,
117
118 /* PORT0_IN_PU -> PORT329_IN_PU */
119 PINMUX_INPUT_PULLUP_BEGIN,
120 PORT_ALL(IN_PU),
121 PINMUX_INPUT_PULLUP_END,
122
123 /* PORT0_IN_PD -> PORT329_IN_PD */
124 PINMUX_INPUT_PULLDOWN_BEGIN,
125 PORT_ALL(IN_PD),
126 PINMUX_INPUT_PULLDOWN_END,
127
128 /* PORT0_OUT -> PORT329_OUT */
129 PINMUX_OUTPUT_BEGIN,
130 PORT_ALL(OUT),
131 PINMUX_OUTPUT_END,
132
133 PINMUX_FUNCTION_BEGIN,
134 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
135 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
136 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
137 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
138 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
139 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
140 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
141 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
142 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
143 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
144
145 MSEL1CR_31_0, MSEL1CR_31_1,
146 MSEL1CR_27_0, MSEL1CR_27_1,
147 MSEL1CR_25_0, MSEL1CR_25_1,
148 MSEL1CR_24_0, MSEL1CR_24_1,
149 MSEL1CR_22_0, MSEL1CR_22_1,
150 MSEL1CR_21_0, MSEL1CR_21_1,
151 MSEL1CR_20_0, MSEL1CR_20_1,
152 MSEL1CR_19_0, MSEL1CR_19_1,
153 MSEL1CR_18_0, MSEL1CR_18_1,
154 MSEL1CR_17_0, MSEL1CR_17_1,
155 MSEL1CR_16_0, MSEL1CR_16_1,
156 MSEL1CR_15_0, MSEL1CR_15_1,
157 MSEL1CR_14_0, MSEL1CR_14_1,
158 MSEL1CR_13_0, MSEL1CR_13_1,
159 MSEL1CR_12_0, MSEL1CR_12_1,
160 MSEL1CR_11_0, MSEL1CR_11_1,
161 MSEL1CR_10_0, MSEL1CR_10_1,
162 MSEL1CR_09_0, MSEL1CR_09_1,
163 MSEL1CR_08_0, MSEL1CR_08_1,
164 MSEL1CR_07_0, MSEL1CR_07_1,
165 MSEL1CR_06_0, MSEL1CR_06_1,
166 MSEL1CR_05_0, MSEL1CR_05_1,
167 MSEL1CR_04_0, MSEL1CR_04_1,
168 MSEL1CR_03_0, MSEL1CR_03_1,
169 MSEL1CR_02_0, MSEL1CR_02_1,
170 MSEL1CR_01_0, MSEL1CR_01_1,
171 MSEL1CR_00_0, MSEL1CR_00_1,
172
173 MSEL3CR_31_0, MSEL3CR_31_1,
174 MSEL3CR_28_0, MSEL3CR_28_1,
175 MSEL3CR_27_0, MSEL3CR_27_1,
176 MSEL3CR_26_0, MSEL3CR_26_1,
177 MSEL3CR_23_0, MSEL3CR_23_1,
178 MSEL3CR_22_0, MSEL3CR_22_1,
179 MSEL3CR_21_0, MSEL3CR_21_1,
180 MSEL3CR_20_0, MSEL3CR_20_1,
181 MSEL3CR_19_0, MSEL3CR_19_1,
182 MSEL3CR_18_0, MSEL3CR_18_1,
183 MSEL3CR_17_0, MSEL3CR_17_1,
184 MSEL3CR_16_0, MSEL3CR_16_1,
185 MSEL3CR_15_0, MSEL3CR_15_1,
186 MSEL3CR_12_0, MSEL3CR_12_1,
187 MSEL3CR_11_0, MSEL3CR_11_1,
188 MSEL3CR_10_0, MSEL3CR_10_1,
189 MSEL3CR_09_0, MSEL3CR_09_1,
190 MSEL3CR_06_0, MSEL3CR_06_1,
191 MSEL3CR_03_0, MSEL3CR_03_1,
192 MSEL3CR_01_0, MSEL3CR_01_1,
193 MSEL3CR_00_0, MSEL3CR_00_1,
194
195 MSEL4CR_30_0, MSEL4CR_30_1,
196 MSEL4CR_29_0, MSEL4CR_29_1,
197 MSEL4CR_28_0, MSEL4CR_28_1,
198 MSEL4CR_27_0, MSEL4CR_27_1,
199 MSEL4CR_26_0, MSEL4CR_26_1,
200 MSEL4CR_25_0, MSEL4CR_25_1,
201 MSEL4CR_24_0, MSEL4CR_24_1,
202 MSEL4CR_23_0, MSEL4CR_23_1,
203 MSEL4CR_22_0, MSEL4CR_22_1,
204 MSEL4CR_21_0, MSEL4CR_21_1,
205 MSEL4CR_20_0, MSEL4CR_20_1,
206 MSEL4CR_19_0, MSEL4CR_19_1,
207 MSEL4CR_18_0, MSEL4CR_18_1,
208 MSEL4CR_17_0, MSEL4CR_17_1,
209 MSEL4CR_16_0, MSEL4CR_16_1,
210 MSEL4CR_15_0, MSEL4CR_15_1,
211 MSEL4CR_14_0, MSEL4CR_14_1,
212 MSEL4CR_13_0, MSEL4CR_13_1,
213 MSEL4CR_12_0, MSEL4CR_12_1,
214 MSEL4CR_11_0, MSEL4CR_11_1,
215 MSEL4CR_10_0, MSEL4CR_10_1,
216 MSEL4CR_09_0, MSEL4CR_09_1,
217 MSEL4CR_07_0, MSEL4CR_07_1,
218 MSEL4CR_04_0, MSEL4CR_04_1,
219 MSEL4CR_01_0, MSEL4CR_01_1,
220
221 MSEL5CR_31_0, MSEL5CR_31_1,
222 MSEL5CR_30_0, MSEL5CR_30_1,
223 MSEL5CR_29_0, MSEL5CR_29_1,
224 MSEL5CR_28_0, MSEL5CR_28_1,
225 MSEL5CR_27_0, MSEL5CR_27_1,
226 MSEL5CR_26_0, MSEL5CR_26_1,
227 MSEL5CR_25_0, MSEL5CR_25_1,
228 MSEL5CR_24_0, MSEL5CR_24_1,
229 MSEL5CR_23_0, MSEL5CR_23_1,
230 MSEL5CR_22_0, MSEL5CR_22_1,
231 MSEL5CR_21_0, MSEL5CR_21_1,
232 MSEL5CR_20_0, MSEL5CR_20_1,
233 MSEL5CR_19_0, MSEL5CR_19_1,
234 MSEL5CR_18_0, MSEL5CR_18_1,
235 MSEL5CR_17_0, MSEL5CR_17_1,
236 MSEL5CR_16_0, MSEL5CR_16_1,
237 MSEL5CR_15_0, MSEL5CR_15_1,
238 MSEL5CR_14_0, MSEL5CR_14_1,
239 MSEL5CR_13_0, MSEL5CR_13_1,
240 MSEL5CR_12_0, MSEL5CR_12_1,
241 MSEL5CR_11_0, MSEL5CR_11_1,
242 MSEL5CR_10_0, MSEL5CR_10_1,
243 MSEL5CR_09_0, MSEL5CR_09_1,
244 MSEL5CR_08_0, MSEL5CR_08_1,
245 MSEL5CR_07_0, MSEL5CR_07_1,
246 MSEL5CR_06_0, MSEL5CR_06_1,
247
248 MSEL8CR_16_0, MSEL8CR_16_1,
249 MSEL8CR_01_0, MSEL8CR_01_1,
250 MSEL8CR_00_0, MSEL8CR_00_1,
251
252 PINMUX_FUNCTION_END,
253
254 PINMUX_MARK_BEGIN,
255
256
257#define F1(a) a##_MARK
258#define F2(a) a##_MARK
259#define F3(a) a##_MARK
260#define F4(a) a##_MARK
261#define F5(a) a##_MARK
262#define F6(a) a##_MARK
263#define F7(a) a##_MARK
264#define IRQ(a) IRQ##a##_MARK
265
266 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
267 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
268 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
269 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
270 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
271 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
272 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
273 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
274 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
275 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
276 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
277 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
278 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
279 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
280 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
281 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
282 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
283 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
284 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
285 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
286 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
287 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
288 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
289 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
290 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
291 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
292 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
293 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
294 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
295 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
296 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
297 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
298
299 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
300 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
301 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
302 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
303 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
304 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
305 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
306 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
307 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
308 F7(CHSCIF0_HSCK), /* Port40 */
309
310 F1(PDM0_DATA), /* Port64 */
311 F1(PDM1_DATA),
312 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
313 IRQ(40),
314 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
315 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
316 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
317 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
318 F7(CHSCIF1_HRTS), /* Port70 */
319 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
320 F7(CHSCIF1_HCTS),
321 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
322 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
323 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
324 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
325 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
326
327 F1(KEYIN0), /* Port96 */
328 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
329 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
330 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
331 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
332 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
333 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
334 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
335 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
336 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
337 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
338 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
339 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
340 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
341 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
342 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
343 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
344 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
345 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
346 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
347 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
348 F5(SIM0_VOLTSEL1), /* Port130 */
349 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
350 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
351 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
352 IRQ(20), /* Port160 */
353 IRQ(21), IRQ(22), IRQ(23),
354 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
355 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
356 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
357 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
358 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
359 F1(A9), F2(MMCD1_6), IRQ(32),
360 F1(A8), F2(MMCD1_5), IRQ(33),
361 F1(A7), F2(MMCD1_4), IRQ(34),
362 F1(A6), F2(MMCD1_3), IRQ(35),
363 F1(A5), F2(MMCD1_2), IRQ(36),
364 F1(A4), F2(MMCD1_1), IRQ(37),
365 F1(A3), F2(MMCD1_0), IRQ(38),
366 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
367 F1(A1),
368 F1(A0), F2(BS),
369 F1(CKO), F2(MMCCLK1),
370 F1(CS0_N), F5(SIM0_GPO1),
371 F1(CS2_N), F5(SIM0_GPO2),
372 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
373 F1(D15), F5(GIO_OUT15),
374 F1(D14), F5(GIO_OUT14),
375 F1(D13), F5(GIO_OUT13),
376 F1(D12), F5(GIO_OUT12), /* Port210 */
377 F1(D11), F5(WGM_TXP2),
378 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
379 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
380 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
381 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
382 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
383 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
384 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
385 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
386 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
387 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
388 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
389 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
390 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
391 F1(WE0_N), F2(RDWR_227),
392 F1(WE1_N), F5(SIM0_GPO0),
393 F1(PWMO), F2(VIO_CKO1_229),
394 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
395 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
396 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
397 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
398 F1(FSIAISLD), F2(PDM3_DATA_235),
399 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
400 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
401 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
402 F1(FSIBISLD), /* Port240 */
403 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
404 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
405 F1(FSIBCK), F3(ISP_SHUTTER0_245),
406 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
407 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
408 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
409 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
410 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
411 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
412 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
413 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
414 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
415 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
416 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
417 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
418 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
419 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
420 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
421 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
422 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
423 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
424 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
425 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
426 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
427 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
428 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
429 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
430 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
431 F4(MSIOF6_SS1), /* Port300 */
432 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
433 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
434 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
435 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
436 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
437 IRQ(55), IRQ(56), IRQ(57),
438 PINMUX_MARK_END,
439};
440
441static const pinmux_enum_t pinmux_data[] = {
442 /* specify valid pin states for each pin in GPIO mode */
443
444 PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1),
445 PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3),
446 PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5),
447 PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7),
448 PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9),
449
450 PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11),
451 PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13),
452 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
453 PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17),
454 PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19),
455
456 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21),
457 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23),
458 PORT_DATA_IO_PU_PD(24), PORT_DATA_IO_PU_PD(25),
459 PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27),
460 PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29),
461
462 PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32),
463 PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34),
464 PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36),
465 PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38),
466 PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40),
467
468 PORT_DATA_IO_PU_PD(64), PORT_DATA_IO_PU_PD(65),
469 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
470 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
471
472 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
473 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
474 PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75),
475 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
476 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
477
478 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
479 PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
480 PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
481
482 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
483 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
484
485 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101),
486 PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103),
487 PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105),
488 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107),
489 PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
490
491 PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
492 PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
493 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115),
494 PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117),
495 PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119),
496
497 PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121),
498 PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123),
499 PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125),
500 PORT_DATA_IO_PU_PD(126),
501 PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129),
502
503 PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
504 PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
505 PORT_DATA_IO_PU_PD(134),
506
507 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161),
508 PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163),
509 PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165),
510 PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167),
511 PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169),
512
513 PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171),
514 PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
515 PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
516 PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
517 PORT_DATA_IO_PU_PD(178),
518
519 PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193),
520 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195),
521 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197),
522 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
523
524 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
525 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
526 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
527 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
528 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209),
529
530 PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211),
531 PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213),
532 PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215),
533 PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217),
534 PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219),
535
536 PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221),
537 PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224),
538 PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226),
539 PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228),
540 PORT_DATA_IO_PU_PD(229),
541
542 PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231),
543 PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233),
544 PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235),
545 PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237),
546 PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
547
548 PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241),
549 PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243),
550 PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245),
551 PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247),
552 PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249),
553
554 PORT_DATA_IO_PU_PD(250),
555 PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257),
556 PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259),
557
558 PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261),
559 PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263),
560 PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265),
561 PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267),
562 PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269),
563
564 PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271),
565 PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273),
566 PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275),
567 PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277),
568 PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279),
569
570 PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281),
571 PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283),
572 PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289),
573
574 PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291),
575 PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293),
576 PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295),
577 PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297),
578 PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299),
579
580 PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301),
581 PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303),
582 PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305),
583 PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307),
584 PORT_DATA_IO_PU_PD(308),
585
586 PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321),
587 PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323),
588 PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325),
589 PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327),
590 PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329),
591
592 /* Port0 */
593 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
594 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
595 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
596 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
597
598 /* Port1 */
599 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
600 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
601 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
602 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
603
604 /* Port2 */
605 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
606 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
607 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
608 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
609
610 /* Port3 */
611 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
612 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
613 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
614 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
615
616 /* Port4 */
617 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
618 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
619 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
620 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
621
622 /* Port5 */
623 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
624 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
625 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
626 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
627
628 /* Port6 */
629 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
630 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
631 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
632 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
633
634 /* Port7 */
635 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
636 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
637 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
638 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
639
640 /* Port8 */
641 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
642 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
643 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
644 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
645
646 /* Port9 */
647 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
648 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
649 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
650 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
651
652 /* Port10 */
653 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
654 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
655 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
656 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
657
658 /* Port11 */
659 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
660 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
661 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
662 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
663
664 /* Port12 */
665 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
666 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
667 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
668 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
669
670 /* Port13 */
671 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
672 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
673 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
674 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
675 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
676
677 /* Port14 */
678 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
679 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
680 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
681 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
682 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
683
684 /* Port15 */
685 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
686 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
687 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
688 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
689
690 /* Port16 */
691 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
692 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
693 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
694
695 /* Port17 */
696 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
697 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
698 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
699
700 /* Port18 */
701 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
702 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
703 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
704
705 /* Port19 */
706 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
707 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
708 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
709
710 /* Port20 */
711 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
712 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
713 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
714
715 /* Port21 */
716 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
717 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
718 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
719
720 /* Port22 */
721 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
722 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
723 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
724
725 /* Port23 */
726 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
727 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
728 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
729
730 /* Port24 */
731 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
732 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
733 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
734 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
735
736 /* Port25 */
737 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
738 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
739 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
740
741 /* Port26 */
742 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
743 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
744 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
745 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
746
747 /* Port27 */
748 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
749 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
750 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
751 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
752
753 /* Port28 */
754 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
755 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
756 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
757
758 /* Port29 */
759 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
760 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
761 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
762
763 /* Port30 */
764 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
765 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
766 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
767
768 /* Port32 */
769 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
770 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
771 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
772
773 /* Port33 */
774 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
775 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
776 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
777
778 /* Port34 */
779 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
780 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
781 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
782
783 /* Port35 */
784 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
785 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
786
787 /* Port36 */
788 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
789 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
790
791 /* Port37 */
792 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
793 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
794
795 /* Port38 */
796 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
797 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
798 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
799 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
800
801 /* Port39 */
802 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
803 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
804 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
805 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
806
807 /* Port40 */
808 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
809 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
810 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
811 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
812
813 /* Port64 */
814 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
815
816 /* Port65 */
817 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
818
819 /* Port66 */
820 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
821 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
822 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
823 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
824 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
825
826 /* Port67 */
827 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
828 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
829 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
830 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
831
832 /* Port68 */
833 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
834 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
835 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
836 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
837
838 /* Port69 */
839 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
840 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
841 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
842 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
843
844 /* Port70 */
845 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
846 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
847 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
848 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
849 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
850
851 /* Port71 */
852 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
853 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
854 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
855 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
856 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
857
858 /* Port72 */
859 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
860 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
861 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
862 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
863
864 /* Port73 */
865 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
866 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
867 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
868 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
869
870 /* Port74 - Port85 */
871 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
872 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
873 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
874 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
875 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
876 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
877 PINMUX_DATA(TXP_MARK, PORT80_FN1),
878 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
879 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
880 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
881 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
882 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
883
884 /* Port96 - Port101 */
885 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
886 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
887 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
888 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
889 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
890 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
891
892 /* Port102 */
893 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
894 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
895
896 /* Port103 */
897 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
898 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
899
900 /* Port104 - Port108 */
901 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
902 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
903 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
904 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
905 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
906
907 /* Port109 */
908 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
909 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
910
911 /* Port110 */
912 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
913 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
914
915 /* Port111 */
916 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
917 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
918 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
919
920 /* Port112 */
921 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
922 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
923 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
924 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
925
926 /* Port113 */
927 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
928 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
929 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
930 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
931
932 /* Port114 */
933 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
934 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
935 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
936 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
937
938 /* Port115 */
939 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
940 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
941 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
942 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
943
944 /* Port116 */
945 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
946 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
947
948 /* Port117 */
949 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
950 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
951
952 /* Port118 */
953 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
954 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
955
956 /* Port119 */
957 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
958 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
959
960 /* Port120 */
961 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
962 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
963 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
964
965 /* Port121 */
966 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
967 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
968
969 /* Port122 */
970 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
971 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
972
973 /* Port123 */
974 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
975 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
976
977 /* Port124 */
978 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
979
980 /* Port125 */
981 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
982 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
983 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
984 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
985
986 /* Port126 */
987 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
988 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
989 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
990
991 /* Port128 */
992 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
993 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
994 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
995 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
996
997 /* Port129 */
998 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
999 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
1000 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
1001
1002 /* Port130 */
1003 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
1004 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
1005 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
1006 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
1007
1008 /* Port131 */
1009 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
1010 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
1011
1012 /* Port132 */
1013 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
1014 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
1015 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
1016
1017 /* Port133 */
1018 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
1019 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
1020 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
1021 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
1022
1023 /* Port134 */
1024 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
1025 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
1026 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
1027
1028 /* Port160 - Port178 */
1029 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
1030 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
1031 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
1032 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
1033 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
1034 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
1035 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
1036 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
1037 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
1038 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
1039 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
1040 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
1041 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
1042 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
1043 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
1044 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
1045 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
1046 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
1047 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
1048
1049 /* Port192 - Port200 FN1 */
1050 PINMUX_DATA(A10_MARK, PORT192_FN1),
1051 PINMUX_DATA(A9_MARK, PORT193_FN1),
1052 PINMUX_DATA(A8_MARK, PORT194_FN1),
1053 PINMUX_DATA(A7_MARK, PORT195_FN1),
1054 PINMUX_DATA(A6_MARK, PORT196_FN1),
1055 PINMUX_DATA(A5_MARK, PORT197_FN1),
1056 PINMUX_DATA(A4_MARK, PORT198_FN1),
1057 PINMUX_DATA(A3_MARK, PORT199_FN1),
1058 PINMUX_DATA(A2_MARK, PORT200_FN1),
1059
1060 /* Port192 - Port200 FN2 */
1061 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
1062 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
1063 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
1064 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
1065 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
1066 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
1067 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
1068 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
1069 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
1070
1071 /* Port192 - Port200 IRQ */
1072 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
1073 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
1074 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
1075 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
1076 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
1077 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
1078 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
1079 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
1080 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
1081
1082 /* Port201 */
1083 PINMUX_DATA(A1_MARK, PORT201_FN1),
1084
1085 /* Port202 */
1086 PINMUX_DATA(A0_MARK, PORT202_FN1),
1087 PINMUX_DATA(BS_MARK, PORT202_FN2),
1088
1089 /* Port203 */
1090 PINMUX_DATA(CKO_MARK, PORT203_FN1),
1091 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
1092
1093 /* Port204 */
1094 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
1095 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
1096
1097 /* Port205 */
1098 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
1099 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
1100
1101 /* Port206 */
1102 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
1103 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
1104 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
1105
1106 /* Port207 - Port212 FN1 */
1107 PINMUX_DATA(D15_MARK, PORT207_FN1),
1108 PINMUX_DATA(D14_MARK, PORT208_FN1),
1109 PINMUX_DATA(D13_MARK, PORT209_FN1),
1110 PINMUX_DATA(D12_MARK, PORT210_FN1),
1111 PINMUX_DATA(D11_MARK, PORT211_FN1),
1112 PINMUX_DATA(D10_MARK, PORT212_FN1),
1113
1114 /* Port207 - Port212 FN5 */
1115 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
1116 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
1117 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
1118 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
1119 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
1120 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
1121
1122 /* Port213 - Port222 FN1 */
1123 PINMUX_DATA(D9_MARK, PORT213_FN1),
1124 PINMUX_DATA(D8_MARK, PORT214_FN1),
1125 PINMUX_DATA(D7_MARK, PORT215_FN1),
1126 PINMUX_DATA(D6_MARK, PORT216_FN1),
1127 PINMUX_DATA(D5_MARK, PORT217_FN1),
1128 PINMUX_DATA(D4_MARK, PORT218_FN1),
1129 PINMUX_DATA(D3_MARK, PORT219_FN1),
1130 PINMUX_DATA(D2_MARK, PORT220_FN1),
1131 PINMUX_DATA(D1_MARK, PORT221_FN1),
1132 PINMUX_DATA(D0_MARK, PORT222_FN1),
1133
1134 /* Port213 - Port222 FN2 */
1135 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
1136 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
1137 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
1138 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
1139 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
1140 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
1141 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
1142 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
1143 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
1144 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
1145
1146 /* Port213 - Port222 FN5 */
1147 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
1148 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
1149 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
1150 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
1151 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
1152 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
1153 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
1154 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1155 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1156 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1157
1158 /* Port224 */
1159 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1160 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1161 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1162
1163 /* Port225 */
1164 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1165
1166 /* Port226 */
1167 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1168 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1169 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1170
1171 /* Port227 */
1172 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1173 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1174
1175 /* Port228 */
1176 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1177 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1178
1179 /* Port229 */
1180 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1181 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1182
1183 /* Port230 */
1184 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1185 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1186
1187 /* Port231 */
1188 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1189 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1190
1191 /* Port232 */
1192 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1193 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1194
1195 /* Port233 */
1196 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1197 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1198
1199 /* Port234 */
1200 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1201 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1202 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1203
1204 /* Port235 */
1205 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1206 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1207
1208 /* Port236 */
1209 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1210 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1211 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1212
1213 /* Port237 */
1214 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1215 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1216
1217 /* Port238 */
1218 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1219 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1220
1221 /* Port239 */
1222 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1223 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1224
1225 /* Port240 */
1226 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1227
1228 /* Port241 */
1229 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1230 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1231
1232 /* Port242 */
1233 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1234 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1235
1236 /* Port243 */
1237 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1238 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1239
1240 /* Port244 */
1241 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1242 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1243
1244 /* Port245 */
1245 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1246 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1247
1248 /* Port246 - Port250 FN1 */
1249 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1250 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1251 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1252 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1253 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1254
1255 /* Port256 - Port258 */
1256 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1257 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1258 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1259
1260 /* Port259 */
1261 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1262 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1263
1264 /* Port260 */
1265 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1266
1267 /* Port261 */
1268 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1269 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1270
1271 /* Port262 */
1272 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1273
1274 /* Port263 - Port266 FN1 */
1275 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1276 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1277 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1278 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1279
1280 /* Port263 - Port266 FN4 */
1281 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1282 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1283 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1284 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1285
1286 /* Port267 */
1287 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1288
1289 /* Port268 */
1290 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1291 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1292
1293 /* Port269 */
1294 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1295 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1296
1297 /* Port270 - Port273 FN1 */
1298 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1299 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1300 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1301 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1302
1303 /* Port270 - Port273 FN3 */
1304 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1305 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1306 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1307 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1308
1309 /* Port274 */
1310 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1311 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1312
1313 /* Port275 - Port280 */
1314 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1315 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1316 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1317 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1318 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1319 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1320
1321 /* Port281 */
1322 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1323 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1324
1325 /* Port282 */
1326 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1327 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1328
1329 /* Port283 */
1330 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1331
1332 /* Port289 */
1333 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1334 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1335
1336 /* Port290 */
1337 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1338 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1339 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1340
1341 /* Port291 - Port294 FN1 */
1342 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1343 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1344 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1345 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1346
1347 /* Port291 - Port294 FN3 */
1348 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1349 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1350 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1351 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1352
1353 /* Port295 */
1354 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1355 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1356 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1357 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1358
1359 /* Port296 */
1360 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1361 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1362 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1363
1364 /* Port297 - Port300 FN1 */
1365 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1366 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1367 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1368 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1369
1370 /* Port297 - Port300 FN2 */
1371 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1372 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1373 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1374 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1375
1376 /* Port297 - Port300 FN3 */
1377 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1378 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1379 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1380 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1381
1382 /* Port297 - Port300 FN4 */
1383 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1384 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1385 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1386 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1387
1388 /* Port301 */
1389 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1390 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1391
1392 /* Port302 - Port306 FN1 */
1393 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1394 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1395 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1396 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1397 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1398
1399 /* Port302 - Port306 FN3 */
1400 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1401 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1402 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1403 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1404 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1405
1406 /* Port307 */
1407 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1408
1409 /* Port308 */
1410 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1411 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1412
1413 /* Port320 - Port329 */
1414 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1415 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1416 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1417 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1418 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1419 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1420 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1421 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1422 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1423 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1424};
1425
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1426#define R8A73A4_PIN(pin, cfgs) \
1427 { \
1428 .name = __stringify(PORT##pin), \
1429 .enum_id = PORT##pin##_DATA, \
1430 .configs = cfgs, \
1431 }
1432
1433#define __O (SH_PFC_PIN_CFG_OUTPUT)
1434#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1435#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1436
1437#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1438#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1439
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1440static struct sh_pfc_pin pinmux_pins[] = {
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1441 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1442 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1443 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1444 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1445 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1446 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1447 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1448 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1449 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1450 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1451 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1452 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1453 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1454 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1455 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1456 R8A73A4_PIN_IO_PU_PD(30),
1457 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1458 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1459 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1460 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1461 R8A73A4_PIN_IO_PU_PD(40),
1462 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1463 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1464 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1465 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1466 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1467 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1468 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1469 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1470 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1471 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1472 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1473 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1474 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1475 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1476 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1477 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1478 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1479 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1480 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1481 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1482 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1483 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1484 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1485 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1486 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1487 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1488 R8A73A4_PIN_IO_PU_PD(126),
1489 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1490 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1491 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1492 R8A73A4_PIN_IO_PU_PD(134),
1493 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1494 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1495 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1496 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1497 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1498 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1499 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1500 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1501 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1502 R8A73A4_PIN_IO_PU_PD(178),
1503 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1504 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1505 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1506 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1507 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1508 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1509 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1510 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1511 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1512 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1513 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1514 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1515 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1516 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1517 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1518 R8A73A4_PIN_IO_PU_PD(222),
1519 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1520 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1521 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1522 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1523 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1524 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1525 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1526 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1527 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1528 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1529 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1530 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1531 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1532 R8A73A4_PIN_IO_PU_PD(250),
1533 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1534 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1535 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1536 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1537 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1538 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1539 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1540 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1541 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1542 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1543 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1544 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1545 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1546 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1547 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1548 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1549 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1550 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1551 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1552 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1553 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1554 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1555 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1556 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1557 R8A73A4_PIN_IO_PU_PD(308),
1558 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1559 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1560 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1561 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1562 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1563};
1564
Magnus Dammf365bfc2013-03-26 22:49:59 +0900[diff] [blame]1565static const struct pinmux_range pinmux_ranges[] = {
1566 {.begin = 0, .end = 30,},
1567 {.begin = 32, .end = 40,},
1568 {.begin = 64, .end = 85,},
1569 {.begin = 96, .end = 126,},
1570 {.begin = 128, .end = 134,},
1571 {.begin = 160, .end = 178,},
1572 {.begin = 192, .end = 222,},
1573 {.begin = 224, .end = 250,},
1574 {.begin = 256, .end = 283,},
1575 {.begin = 288, .end = 308,},
1576 {.begin = 320, .end = 329,},
1577};
1578
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame^]1579/* - IRQC ------------------------------------------------------------------- */
1580#define IRQC_PINS_MUX(pin, irq_mark) \
1581static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1582 pin, \
1583}; \
1584static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1585 IRQ##irq_mark##_MARK, \
1586}
1587IRQC_PINS_MUX(0, 0);
1588IRQC_PINS_MUX(1, 1);
1589IRQC_PINS_MUX(2, 2);
1590IRQC_PINS_MUX(3, 3);
1591IRQC_PINS_MUX(4, 4);
1592IRQC_PINS_MUX(5, 5);
1593IRQC_PINS_MUX(6, 6);
1594IRQC_PINS_MUX(7, 7);
1595IRQC_PINS_MUX(8, 8);
1596IRQC_PINS_MUX(9, 9);
1597IRQC_PINS_MUX(10, 10);
1598IRQC_PINS_MUX(11, 11);
1599IRQC_PINS_MUX(12, 12);
1600IRQC_PINS_MUX(13, 13);
1601IRQC_PINS_MUX(14, 14);
1602IRQC_PINS_MUX(15, 15);
1603IRQC_PINS_MUX(66, 40);
1604IRQC_PINS_MUX(84, 19);
1605IRQC_PINS_MUX(85, 18);
1606IRQC_PINS_MUX(102, 41);
1607IRQC_PINS_MUX(103, 42);
1608IRQC_PINS_MUX(109, 43);
1609IRQC_PINS_MUX(110, 44);
1610IRQC_PINS_MUX(111, 45);
1611IRQC_PINS_MUX(112, 46);
1612IRQC_PINS_MUX(113, 47);
1613IRQC_PINS_MUX(114, 48);
1614IRQC_PINS_MUX(115, 49);
1615IRQC_PINS_MUX(160, 20);
1616IRQC_PINS_MUX(161, 21);
1617IRQC_PINS_MUX(162, 22);
1618IRQC_PINS_MUX(163, 23);
1619IRQC_PINS_MUX(175, 24);
1620IRQC_PINS_MUX(176, 25);
1621IRQC_PINS_MUX(177, 26);
1622IRQC_PINS_MUX(178, 27);
1623IRQC_PINS_MUX(192, 31);
1624IRQC_PINS_MUX(193, 32);
1625IRQC_PINS_MUX(194, 33);
1626IRQC_PINS_MUX(195, 34);
1627IRQC_PINS_MUX(196, 35);
1628IRQC_PINS_MUX(197, 36);
1629IRQC_PINS_MUX(198, 37);
1630IRQC_PINS_MUX(199, 38);
1631IRQC_PINS_MUX(200, 39);
1632IRQC_PINS_MUX(290, 51);
1633IRQC_PINS_MUX(296, 52);
1634IRQC_PINS_MUX(301, 50);
1635IRQC_PINS_MUX(320, 16);
1636IRQC_PINS_MUX(321, 17);
1637IRQC_PINS_MUX(322, 28);
1638IRQC_PINS_MUX(323, 29);
1639IRQC_PINS_MUX(324, 30);
1640IRQC_PINS_MUX(325, 53);
1641IRQC_PINS_MUX(326, 54);
1642IRQC_PINS_MUX(327, 55);
1643IRQC_PINS_MUX(328, 56);
1644IRQC_PINS_MUX(329, 57);
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1645/* - SCIFA0 ----------------------------------------------------------------- */
1646static const unsigned int scifa0_data_pins[] = {
1647 /* SCIFA0_RXD, SCIFA0_TXD */
1648 117, 116,
1649};
1650static const unsigned int scifa0_data_mux[] = {
1651 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1652};
1653static const unsigned int scifa0_clk_pins[] = {
1654 /* SCIFA0_SCK */
1655 34,
1656};
1657static const unsigned int scifa0_clk_mux[] = {
1658 SCIFA0_SCK_MARK,
1659};
1660static const unsigned int scifa0_ctrl_pins[] = {
1661 /* SCIFA0_RTS, SCIFA0_CTS */
1662 32, 33,
1663};
1664static const unsigned int scifa0_ctrl_mux[] = {
1665 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1666};
1667/* - SCIFA1 ----------------------------------------------------------------- */
1668static const unsigned int scifa1_data_pins[] = {
1669 /* SCIFA1_RXD, SCIFA1_TXD */
1670 119, 118,
1671};
1672static const unsigned int scifa1_data_mux[] = {
1673 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1674};
1675static const unsigned int scifa1_clk_pins[] = {
1676 /* SCIFA1_SCK */
1677 37,
1678};
1679static const unsigned int scifa1_clk_mux[] = {
1680 SCIFA1_SCK_MARK,
1681};
1682static const unsigned int scifa1_ctrl_pins[] = {
1683 /* SCIFA1_RTS, SCIFA1_CTS */
1684 35, 36,
1685};
1686static const unsigned int scifa1_ctrl_mux[] = {
1687 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1688};
1689/* - SCIFB0 ----------------------------------------------------------------- */
1690static const unsigned int scifb0_data_pins[] = {
1691 /* SCIFB0_RXD, SCIFB0_TXD */
1692 123, 122,
1693};
1694static const unsigned int scifb0_data_mux[] = {
1695 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1696};
1697static const unsigned int scifb0_clk_pins[] = {
1698 /* SCIFB0_SCK */
1699 40,
1700};
1701static const unsigned int scifb0_clk_mux[] = {
1702 SCIFB0_SCK_MARK,
1703};
1704static const unsigned int scifb0_ctrl_pins[] = {
1705 /* SCIFB0_RTS, SCIFB0_CTS */
1706 38, 39,
1707};
1708static const unsigned int scifb0_ctrl_mux[] = {
1709 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1710};
1711/* - SCIFB1 ----------------------------------------------------------------- */
1712static const unsigned int scifb1_data_pins[] = {
1713 /* SCIFB1_RXD, SCIFB1_TXD */
1714 27, 26,
1715};
1716static const unsigned int scifb1_data_mux[] = {
1717 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1718};
1719static const unsigned int scifb1_clk_pins[] = {
1720 /* SCIFB1_SCK */
1721 28,
1722};
1723static const unsigned int scifb1_clk_mux[] = {
1724 SCIFB1_SCK_28_MARK,
1725};
1726static const unsigned int scifb1_ctrl_pins[] = {
1727 /* SCIFB1_RTS, SCIFB1_CTS */
1728 24, 25,
1729};
1730static const unsigned int scifb1_ctrl_mux[] = {
1731 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1732};
1733static const unsigned int scifb1_data_b_pins[] = {
1734 /* SCIFB1_RXD, SCIFB1_TXD */
1735 72, 67,
1736};
1737static const unsigned int scifb1_data_b_mux[] = {
1738 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1739};
1740static const unsigned int scifb1_clk_b_pins[] = {
1741 /* SCIFB1_SCK */
1742 261,
1743};
1744static const unsigned int scifb1_clk_b_mux[] = {
1745 SCIFB1_SCK_261_MARK,
1746};
1747static const unsigned int scifb1_ctrl_b_pins[] = {
1748 /* SCIFB1_RTS, SCIFB1_CTS */
1749 70, 71,
1750};
1751static const unsigned int scifb1_ctrl_b_mux[] = {
1752 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1753};
1754/* - SCIFB2 ----------------------------------------------------------------- */
1755static const unsigned int scifb2_data_pins[] = {
1756 /* SCIFB2_RXD, SCIFB2_TXD */
1757 69, 68,
1758};
1759static const unsigned int scifb2_data_mux[] = {
1760 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1761};
1762static const unsigned int scifb2_clk_pins[] = {
1763 /* SCIFB2_SCK */
1764 262,
1765};
1766static const unsigned int scifb2_clk_mux[] = {
1767 SCIFB2_SCK_262_MARK,
1768};
1769static const unsigned int scifb2_ctrl_pins[] = {
1770 /* SCIFB2_RTS, SCIFB2_CTS */
1771 73, 66,
1772};
1773static const unsigned int scifb2_ctrl_mux[] = {
1774 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1775};
1776static const unsigned int scifb2_data_b_pins[] = {
1777 /* SCIFB2_RXD, SCIFB2_TXD */
1778 297, 295,
1779};
1780static const unsigned int scifb2_data_b_mux[] = {
1781 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1782};
1783static const unsigned int scifb2_clk_b_pins[] = {
1784 /* SCIFB2_SCK */
1785 299,
1786};
1787static const unsigned int scifb2_clk_b_mux[] = {
1788 SCIFB2_SCK_299_MARK,
1789};
1790static const unsigned int scifb2_ctrl_b_pins[] = {
1791 /* SCIFB2_RTS, SCIFB2_CTS */
1792 300, 298,
1793};
1794static const unsigned int scifb2_ctrl_b_mux[] = {
1795 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1796};
1797/* - SCIFB3 ----------------------------------------------------------------- */
1798static const unsigned int scifb3_data_pins[] = {
1799 /* SCIFB3_RXD, SCIFB3_TXD */
1800 22, 21,
1801};
1802static const unsigned int scifb3_data_mux[] = {
1803 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1804};
1805static const unsigned int scifb3_clk_pins[] = {
1806 /* SCIFB3_SCK */
1807 23,
1808};
1809static const unsigned int scifb3_clk_mux[] = {
1810 SCIFB3_SCK_23_MARK,
1811};
1812static const unsigned int scifb3_ctrl_pins[] = {
1813 /* SCIFB3_RTS, SCIFB3_CTS */
1814 19, 20,
1815};
1816static const unsigned int scifb3_ctrl_mux[] = {
1817 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1818};
1819static const unsigned int scifb3_data_b_pins[] = {
1820 /* SCIFB3_RXD, SCIFB3_TXD */
1821 120, 121,
1822};
1823static const unsigned int scifb3_data_b_mux[] = {
1824 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1825};
1826static const unsigned int scifb3_clk_b_pins[] = {
1827 /* SCIFB3_SCK */
1828 40,
1829};
1830static const unsigned int scifb3_clk_b_mux[] = {
1831 SCIFB3_SCK_40_MARK,
1832};
1833static const unsigned int scifb3_ctrl_b_pins[] = {
1834 /* SCIFB3_RTS, SCIFB3_CTS */
1835 38, 39,
1836};
1837static const unsigned int scifb3_ctrl_b_mux[] = {
1838 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1839};
1840
1841static const struct sh_pfc_pin_group pinmux_groups[] = {
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame^]1842 SH_PFC_PIN_GROUP(irqc_irq0),
1843 SH_PFC_PIN_GROUP(irqc_irq1),
1844 SH_PFC_PIN_GROUP(irqc_irq2),
1845 SH_PFC_PIN_GROUP(irqc_irq3),
1846 SH_PFC_PIN_GROUP(irqc_irq4),
1847 SH_PFC_PIN_GROUP(irqc_irq5),
1848 SH_PFC_PIN_GROUP(irqc_irq6),
1849 SH_PFC_PIN_GROUP(irqc_irq7),
1850 SH_PFC_PIN_GROUP(irqc_irq8),
1851 SH_PFC_PIN_GROUP(irqc_irq9),
1852 SH_PFC_PIN_GROUP(irqc_irq10),
1853 SH_PFC_PIN_GROUP(irqc_irq11),
1854 SH_PFC_PIN_GROUP(irqc_irq12),
1855 SH_PFC_PIN_GROUP(irqc_irq13),
1856 SH_PFC_PIN_GROUP(irqc_irq14),
1857 SH_PFC_PIN_GROUP(irqc_irq15),
1858 SH_PFC_PIN_GROUP(irqc_irq16),
1859 SH_PFC_PIN_GROUP(irqc_irq17),
1860 SH_PFC_PIN_GROUP(irqc_irq18),
1861 SH_PFC_PIN_GROUP(irqc_irq19),
1862 SH_PFC_PIN_GROUP(irqc_irq20),
1863 SH_PFC_PIN_GROUP(irqc_irq21),
1864 SH_PFC_PIN_GROUP(irqc_irq22),
1865 SH_PFC_PIN_GROUP(irqc_irq23),
1866 SH_PFC_PIN_GROUP(irqc_irq24),
1867 SH_PFC_PIN_GROUP(irqc_irq25),
1868 SH_PFC_PIN_GROUP(irqc_irq26),
1869 SH_PFC_PIN_GROUP(irqc_irq27),
1870 SH_PFC_PIN_GROUP(irqc_irq28),
1871 SH_PFC_PIN_GROUP(irqc_irq29),
1872 SH_PFC_PIN_GROUP(irqc_irq30),
1873 SH_PFC_PIN_GROUP(irqc_irq31),
1874 SH_PFC_PIN_GROUP(irqc_irq32),
1875 SH_PFC_PIN_GROUP(irqc_irq33),
1876 SH_PFC_PIN_GROUP(irqc_irq34),
1877 SH_PFC_PIN_GROUP(irqc_irq35),
1878 SH_PFC_PIN_GROUP(irqc_irq36),
1879 SH_PFC_PIN_GROUP(irqc_irq37),
1880 SH_PFC_PIN_GROUP(irqc_irq38),
1881 SH_PFC_PIN_GROUP(irqc_irq39),
1882 SH_PFC_PIN_GROUP(irqc_irq40),
1883 SH_PFC_PIN_GROUP(irqc_irq41),
1884 SH_PFC_PIN_GROUP(irqc_irq42),
1885 SH_PFC_PIN_GROUP(irqc_irq43),
1886 SH_PFC_PIN_GROUP(irqc_irq44),
1887 SH_PFC_PIN_GROUP(irqc_irq45),
1888 SH_PFC_PIN_GROUP(irqc_irq46),
1889 SH_PFC_PIN_GROUP(irqc_irq47),
1890 SH_PFC_PIN_GROUP(irqc_irq48),
1891 SH_PFC_PIN_GROUP(irqc_irq49),
1892 SH_PFC_PIN_GROUP(irqc_irq50),
1893 SH_PFC_PIN_GROUP(irqc_irq51),
1894 SH_PFC_PIN_GROUP(irqc_irq52),
1895 SH_PFC_PIN_GROUP(irqc_irq53),
1896 SH_PFC_PIN_GROUP(irqc_irq54),
1897 SH_PFC_PIN_GROUP(irqc_irq55),
1898 SH_PFC_PIN_GROUP(irqc_irq56),
1899 SH_PFC_PIN_GROUP(irqc_irq57),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1900 SH_PFC_PIN_GROUP(scifa0_data),
1901 SH_PFC_PIN_GROUP(scifa0_clk),
1902 SH_PFC_PIN_GROUP(scifa0_ctrl),
1903 SH_PFC_PIN_GROUP(scifa1_data),
1904 SH_PFC_PIN_GROUP(scifa1_clk),
1905 SH_PFC_PIN_GROUP(scifa1_ctrl),
1906 SH_PFC_PIN_GROUP(scifb0_data),
1907 SH_PFC_PIN_GROUP(scifb0_clk),
1908 SH_PFC_PIN_GROUP(scifb0_ctrl),
1909 SH_PFC_PIN_GROUP(scifb1_data),
1910 SH_PFC_PIN_GROUP(scifb1_clk),
1911 SH_PFC_PIN_GROUP(scifb1_ctrl),
1912 SH_PFC_PIN_GROUP(scifb1_data_b),
1913 SH_PFC_PIN_GROUP(scifb1_clk_b),
1914 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1915 SH_PFC_PIN_GROUP(scifb2_data),
1916 SH_PFC_PIN_GROUP(scifb2_clk),
1917 SH_PFC_PIN_GROUP(scifb2_ctrl),
1918 SH_PFC_PIN_GROUP(scifb2_data_b),
1919 SH_PFC_PIN_GROUP(scifb2_clk_b),
1920 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1921 SH_PFC_PIN_GROUP(scifb3_data),
1922 SH_PFC_PIN_GROUP(scifb3_clk),
1923 SH_PFC_PIN_GROUP(scifb3_ctrl),
1924 SH_PFC_PIN_GROUP(scifb3_data_b),
1925 SH_PFC_PIN_GROUP(scifb3_clk_b),
1926 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1927};
1928
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame^]1929static const char * const irqc_groups[] = {
1930 "irqc_irq0",
1931 "irqc_irq1",
1932 "irqc_irq2",
1933 "irqc_irq3",
1934 "irqc_irq4",
1935 "irqc_irq5",
1936 "irqc_irq6",
1937 "irqc_irq7",
1938 "irqc_irq8",
1939 "irqc_irq9",
1940 "irqc_irq10",
1941 "irqc_irq11",
1942 "irqc_irq12",
1943 "irqc_irq13",
1944 "irqc_irq14",
1945 "irqc_irq15",
1946 "irqc_irq16",
1947 "irqc_irq17",
1948 "irqc_irq18",
1949 "irqc_irq19",
1950 "irqc_irq20",
1951 "irqc_irq21",
1952 "irqc_irq22",
1953 "irqc_irq23",
1954 "irqc_irq24",
1955 "irqc_irq25",
1956 "irqc_irq26",
1957 "irqc_irq27",
1958 "irqc_irq28",
1959 "irqc_irq29",
1960 "irqc_irq30",
1961 "irqc_irq31",
1962 "irqc_irq32",
1963 "irqc_irq33",
1964 "irqc_irq34",
1965 "irqc_irq35",
1966 "irqc_irq36",
1967 "irqc_irq37",
1968 "irqc_irq38",
1969 "irqc_irq39",
1970 "irqc_irq40",
1971 "irqc_irq41",
1972 "irqc_irq42",
1973 "irqc_irq43",
1974 "irqc_irq44",
1975 "irqc_irq45",
1976 "irqc_irq46",
1977 "irqc_irq47",
1978 "irqc_irq48",
1979 "irqc_irq49",
1980 "irqc_irq50",
1981 "irqc_irq51",
1982 "irqc_irq52",
1983 "irqc_irq53",
1984 "irqc_irq54",
1985 "irqc_irq55",
1986 "irqc_irq56",
1987 "irqc_irq57",
1988};
1989
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1990static const char * const scifa0_groups[] = {
1991 "scifa0_data",
1992 "scifa0_clk",
1993 "scifa0_ctrl",
1994};
1995
1996static const char * const scifa1_groups[] = {
1997 "scifa1_data",
1998 "scifa1_clk",
1999 "scifa1_ctrl",
2000};
2001
2002static const char * const scifb0_groups[] = {
2003 "scifb0_data",
2004 "scifb0_clk",
2005 "scifb0_ctrl",
2006};
2007
2008static const char * const scifb1_groups[] = {
2009 "scifb1_data",
2010 "scifb1_clk",
2011 "scifb1_ctrl",
2012 "scifb1_data_b",
2013 "scifb1_clk_b",
2014 "scifb1_ctrl_b",
2015};
2016
2017static const char * const scifb2_groups[] = {
2018 "scifb2_data",
2019 "scifb2_clk",
2020 "scifb2_ctrl",
2021 "scifb2_data_b",
2022 "scifb2_clk_b",
2023 "scifb2_ctrl_b",
2024};
2025
2026static const char * const scifb3_groups[] = {
2027 "scifb3_data",
2028 "scifb3_clk",
2029 "scifb3_ctrl",
2030 "scifb3_data_b",
2031 "scifb3_clk_b",
2032 "scifb3_ctrl_b",
2033};
2034
2035static const struct sh_pfc_function pinmux_functions[] = {
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame^]2036 SH_PFC_FUNCTION(irqc),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]2037 SH_PFC_FUNCTION(scifa0),
2038 SH_PFC_FUNCTION(scifa1),
2039 SH_PFC_FUNCTION(scifb0),
2040 SH_PFC_FUNCTION(scifb1),
2041 SH_PFC_FUNCTION(scifb2),
2042 SH_PFC_FUNCTION(scifb3),
2043};
2044
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2045#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2046
2047static const struct pinmux_func pinmux_func_gpios[] = {
2048 /* Port0 */
2049 GPIO_FN(LCDD0),
2050 GPIO_FN(PDM2_CLK_0),
2051 GPIO_FN(DU0_DR0),
2052 GPIO_FN(IRQ0),
2053
2054 /* Port1 */
2055 GPIO_FN(LCDD1),
2056 GPIO_FN(PDM2_DATA_1),
2057 GPIO_FN(DU0_DR19),
2058 GPIO_FN(IRQ1),
2059
2060 /* Port2 */
2061 GPIO_FN(LCDD2),
2062 GPIO_FN(PDM3_CLK_2),
2063 GPIO_FN(DU0_DR2),
2064 GPIO_FN(IRQ2),
2065
2066 /* Port3 */
2067 GPIO_FN(LCDD3),
2068 GPIO_FN(PDM3_DATA_3),
2069 GPIO_FN(DU0_DR3),
2070 GPIO_FN(IRQ3),
2071
2072 /* Port4 */
2073 GPIO_FN(LCDD4),
2074 GPIO_FN(PDM4_CLK_4),
2075 GPIO_FN(DU0_DR4),
2076 GPIO_FN(IRQ4),
2077
2078 /* Port5 */
2079 GPIO_FN(LCDD5),
2080 GPIO_FN(PDM4_DATA_5),
2081 GPIO_FN(DU0_DR5),
2082 GPIO_FN(IRQ5),
2083
2084 /* Port6 */
2085 GPIO_FN(LCDD6),
2086 GPIO_FN(PDM0_OUTCLK_6),
2087 GPIO_FN(DU0_DR6),
2088 GPIO_FN(IRQ6),
2089
2090 /* Port7 */
2091 GPIO_FN(LCDD7),
2092 GPIO_FN(PDM0_OUTDATA_7),
2093 GPIO_FN(DU0_DR7),
2094 GPIO_FN(IRQ7),
2095
2096 /* Port8 */
2097 GPIO_FN(LCDD8),
2098 GPIO_FN(PDM1_OUTCLK_8),
2099 GPIO_FN(DU0_DG0),
2100 GPIO_FN(IRQ8),
2101
2102 /* Port9 */
2103 GPIO_FN(LCDD9),
2104 GPIO_FN(PDM1_OUTDATA_9),
2105 GPIO_FN(DU0_DG1),
2106 GPIO_FN(IRQ9),
2107
2108 /* Port10 */
2109 GPIO_FN(LCDD10),
2110 GPIO_FN(FSICCK),
2111 GPIO_FN(DU0_DG2),
2112 GPIO_FN(IRQ10),
2113
2114 /* Port11 */
2115 GPIO_FN(LCDD11),
2116 GPIO_FN(FSICISLD),
2117 GPIO_FN(DU0_DG3),
2118 GPIO_FN(IRQ11),
2119
2120 /* Port12 */
2121 GPIO_FN(LCDD12),
2122 GPIO_FN(FSICOMC),
2123 GPIO_FN(DU0_DG4),
2124 GPIO_FN(IRQ12),
2125
2126 /* Port13 */
2127 GPIO_FN(LCDD13),
2128 GPIO_FN(FSICOLR),
2129 GPIO_FN(FSICILR),
2130 GPIO_FN(DU0_DG5),
2131 GPIO_FN(IRQ13),
2132
2133 /* Port14 */
2134 GPIO_FN(LCDD14),
2135 GPIO_FN(FSICOBT),
2136 GPIO_FN(FSICIBT),
2137 GPIO_FN(DU0_DG6),
2138 GPIO_FN(IRQ14),
2139
2140 /* Port15 */
2141 GPIO_FN(LCDD15),
2142 GPIO_FN(FSICOSLD),
2143 GPIO_FN(DU0_DG7),
2144 GPIO_FN(IRQ15),
2145
2146 /* Port16 */
2147 GPIO_FN(LCDD16),
2148 GPIO_FN(TPU1TO1),
2149 GPIO_FN(DU0_DB0),
2150
2151 /* Port17 */
2152 GPIO_FN(LCDD17),
2153 GPIO_FN(SF_IRQ_00),
2154 GPIO_FN(DU0_DB1),
2155
2156 /* Port18 */
2157 GPIO_FN(LCDD18),
2158 GPIO_FN(SF_IRQ_01),
2159 GPIO_FN(DU0_DB2),
2160
2161 /* Port19 */
2162 GPIO_FN(LCDD19),
2163 GPIO_FN(SCIFB3_RTS_19),
2164 GPIO_FN(DU0_DB3),
2165
2166 /* Port20 */
2167 GPIO_FN(LCDD20),
2168 GPIO_FN(SCIFB3_CTS_20),
2169 GPIO_FN(DU0_DB4),
2170
2171 /* Port21 */
2172 GPIO_FN(LCDD21),
2173 GPIO_FN(SCIFB3_TXD_21),
2174 GPIO_FN(DU0_DB5),
2175
2176 /* Port22 */
2177 GPIO_FN(LCDD22),
2178 GPIO_FN(SCIFB3_RXD_22),
2179 GPIO_FN(DU0_DB6),
2180
2181 /* Port23 */
2182 GPIO_FN(LCDD23),
2183 GPIO_FN(SCIFB3_SCK_23),
2184 GPIO_FN(DU0_DB7),
2185
2186 /* Port24 */
2187 GPIO_FN(LCDHSYN),
2188 GPIO_FN(LCDCS),
2189 GPIO_FN(SCIFB1_RTS_24),
2190 GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
2191
2192 /* Port25 */
2193 GPIO_FN(LCDVSYN),
2194 GPIO_FN(SCIFB1_CTS_25),
2195 GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
2196
2197 /* Port26 */
2198 GPIO_FN(LCDDCK),
2199 GPIO_FN(LCDWR),
2200 GPIO_FN(SCIFB1_TXD_26),
2201 GPIO_FN(DU0_DOTCLKIN),
2202
2203 /* Port27 */
2204 GPIO_FN(LCDDISP),
2205 GPIO_FN(LCDRS),
2206 GPIO_FN(SCIFB1_RXD_27),
2207 GPIO_FN(DU0_DOTCLKOUT),
2208
2209 /* Port28 */
2210 GPIO_FN(LCDRD_N),
2211 GPIO_FN(SCIFB1_SCK_28),
2212 GPIO_FN(DU0_DOTCLKOUTB),
2213
2214 /* Port29 */
2215 GPIO_FN(LCDLCLK),
2216 GPIO_FN(SF_IRQ_02),
2217 GPIO_FN(DU0_DISP_CSYNC_N_DE),
2218
2219 /* Port30 */
2220 GPIO_FN(LCDDON),
2221 GPIO_FN(SF_IRQ_03),
2222 GPIO_FN(DU0_ODDF_N_CLAMP),
2223
2224 /* Port32 */
2225 GPIO_FN(SCIFA0_RTS),
2226 GPIO_FN(SIM0_DET),
2227 GPIO_FN(CSCIF0_RTS),
2228
2229 /* Port33 */
2230 GPIO_FN(SCIFA0_CTS),
2231 GPIO_FN(SIM1_DET),
2232 GPIO_FN(CSCIF0_CTS),
2233
2234 /* Port34 */
2235 GPIO_FN(SCIFA0_SCK),
2236 GPIO_FN(SIM0_PWRON),
2237 GPIO_FN(CSCIF0_SCK),
2238
2239 /* Port35 */
2240 GPIO_FN(SCIFA1_RTS),
2241 GPIO_FN(CSCIF1_RTS),
2242
2243 /* Port36 */
2244 GPIO_FN(SCIFA1_CTS),
2245 GPIO_FN(CSCIF1_CTS),
2246
2247 /* Port37 */
2248 GPIO_FN(SCIFA1_SCK),
2249 GPIO_FN(CSCIF1_SCK),
2250
2251 /* Port38 */
2252 GPIO_FN(SCIFB0_RTS),
2253 GPIO_FN(TPU0TO1),
2254 GPIO_FN(SCIFB3_RTS_38),
2255 GPIO_FN(CHSCIF0_HRTS),
2256
2257 /* Port39 */
2258 GPIO_FN(SCIFB0_CTS),
2259 GPIO_FN(TPU0TO2),
2260 GPIO_FN(SCIFB3_CTS_39),
2261 GPIO_FN(CHSCIF0_HCTS),
2262
2263 /* Port40 */
2264 GPIO_FN(SCIFB0_SCK),
2265 GPIO_FN(TPU0TO3),
2266 GPIO_FN(SCIFB3_SCK_40),
2267 GPIO_FN(CHSCIF0_HSCK),
2268
2269 /* Port64 */
2270 GPIO_FN(PDM0_DATA),
2271
2272 /* Port65 */
2273 GPIO_FN(PDM1_DATA),
2274
2275 /* Port66 */
2276 GPIO_FN(HSI_RX_WAKE),
2277 GPIO_FN(SCIFB2_CTS_66),
2278 GPIO_FN(MSIOF3_SYNC),
2279 GPIO_FN(GenIO4),
2280 GPIO_FN(IRQ40),
2281
2282 /* Port67 */
2283 GPIO_FN(HSI_RX_READY),
2284 GPIO_FN(SCIFB1_TXD_67),
2285 GPIO_FN(GIO_OUT3_67),
2286 GPIO_FN(CHSCIF1_HTX),
2287
2288 /* Port68 */
2289 GPIO_FN(HSI_RX_FLAG),
2290 GPIO_FN(SCIFB2_TXD_68),
2291 GPIO_FN(MSIOF3_TXD),
2292 GPIO_FN(GIO_OUT4_68),
2293
2294 /* Port69 */
2295 GPIO_FN(HSI_RX_DATA),
2296 GPIO_FN(SCIFB2_RXD_69),
2297 GPIO_FN(MSIOF3_RXD),
2298 GPIO_FN(GIO_OUT5_69),
2299
2300 /* Port70 */
2301 GPIO_FN(HSI_TX_FLAG),
2302 GPIO_FN(SCIFB1_RTS_70),
2303 GPIO_FN(GIO_OUT1_70),
2304 GPIO_FN(HSIC_TSTCLK0),
2305 GPIO_FN(CHSCIF1_HRTS),
2306
2307 /* Port71 */
2308 GPIO_FN(HSI_TX_DATA),
2309 GPIO_FN(SCIFB1_CTS_71),
2310 GPIO_FN(GIO_OUT2_71),
2311 GPIO_FN(HSIC_TSTCLK1),
2312 GPIO_FN(CHSCIF1_HCTS),
2313
2314 /* Port72 */
2315 GPIO_FN(HSI_TX_WAKE),
2316 GPIO_FN(SCIFB1_RXD_72),
2317 GPIO_FN(GenIO8),
2318 GPIO_FN(CHSCIF1_HRX),
2319
2320 /* Port73 */
2321 GPIO_FN(HSI_TX_READY),
2322 GPIO_FN(SCIFB2_RTS_73),
2323 GPIO_FN(MSIOF3_SCK),
2324 GPIO_FN(GIO_OUT0_73),
2325
2326 /* Port74 - Port85 */
2327 GPIO_FN(IRDA_OUT),
2328 GPIO_FN(IRDA_IN),
2329 GPIO_FN(IRDA_FIRSEL),
2330 GPIO_FN(TPU0TO0),
2331 GPIO_FN(DIGRFEN),
2332 GPIO_FN(GPS_TIMESTAMP),
2333 GPIO_FN(TXP),
2334 GPIO_FN(TXP2),
2335 GPIO_FN(COEX_0),
2336 GPIO_FN(COEX_1),
2337 GPIO_FN(IRQ19),
2338 GPIO_FN(IRQ18),
2339
2340 /* Port96 - Port101 */
2341 GPIO_FN(KEYIN0),
2342 GPIO_FN(KEYIN1),
2343 GPIO_FN(KEYIN2),
2344 GPIO_FN(KEYIN3),
2345 GPIO_FN(KEYIN4),
2346 GPIO_FN(KEYIN5),
2347
2348 /* Port102 */
2349 GPIO_FN(KEYIN6),
2350 GPIO_FN(IRQ41),
2351
2352 /* Port103 */
2353 GPIO_FN(KEYIN7),
2354 GPIO_FN(IRQ42),
2355
2356 /* Port104 - Port108 */
2357 GPIO_FN(KEYOUT0),
2358 GPIO_FN(KEYOUT1),
2359 GPIO_FN(KEYOUT2),
2360 GPIO_FN(KEYOUT3),
2361 GPIO_FN(KEYOUT4),
2362
2363 /* Port109 */
2364 GPIO_FN(KEYOUT5),
2365 GPIO_FN(IRQ43),
2366
2367 /* Port110 */
2368 GPIO_FN(KEYOUT6),
2369 GPIO_FN(IRQ44),
2370
2371 /* Port111 */
2372 GPIO_FN(KEYOUT7),
2373 GPIO_FN(RFANAEN),
2374 GPIO_FN(IRQ45),
2375
2376 /* Port112 */
2377 GPIO_FN(KEYIN8),
2378 GPIO_FN(KEYOUT8),
2379 GPIO_FN(SF_IRQ_04),
2380 GPIO_FN(IRQ46),
2381
2382 /* Port113 */
2383 GPIO_FN(KEYIN9),
2384 GPIO_FN(KEYOUT9),
2385 GPIO_FN(SF_IRQ_05),
2386 GPIO_FN(IRQ47),
2387
2388 /* Port114 */
2389 GPIO_FN(KEYIN10),
2390 GPIO_FN(KEYOUT10),
2391 GPIO_FN(SF_IRQ_06),
2392 GPIO_FN(IRQ48),
2393
2394 /* Port115 */
2395 GPIO_FN(KEYIN11),
2396 GPIO_FN(KEYOUT11),
2397 GPIO_FN(SF_IRQ_07),
2398 GPIO_FN(IRQ49),
2399
2400 /* Port116 */
2401 GPIO_FN(SCIFA0_TXD),
2402 GPIO_FN(CSCIF0_TX),
2403
2404 /* Port117 */
2405 GPIO_FN(SCIFA0_RXD),
2406 GPIO_FN(CSCIF0_RX),
2407
2408 /* Port118 */
2409 GPIO_FN(SCIFA1_TXD),
2410 GPIO_FN(CSCIF1_TX),
2411
2412 /* Port119 */
2413 GPIO_FN(SCIFA1_RXD),
2414 GPIO_FN(CSCIF1_RX),
2415
2416 /* Port120 */
2417 GPIO_FN(SF_PORT_1_120),
2418 GPIO_FN(SCIFB3_RXD_120),
2419 GPIO_FN(DU0_CDE),
2420
2421 /* Port121 */
2422 GPIO_FN(SF_PORT_0_121),
2423 GPIO_FN(SCIFB3_TXD_121),
2424
2425 /* Port122 */
2426 GPIO_FN(SCIFB0_TXD),
2427 GPIO_FN(CHSCIF0_HTX),
2428
2429 /* Port123 */
2430 GPIO_FN(SCIFB0_RXD),
2431 GPIO_FN(CHSCIF0_HRX),
2432
2433 /* Port124 */
2434 GPIO_FN(ISP_STROBE_124),
2435
2436 /* Port125 */
2437 GPIO_FN(STP_ISD_0),
2438 GPIO_FN(PDM4_CLK_125),
2439 GPIO_FN(MSIOF2_TXD),
2440 GPIO_FN(SIM0_VOLTSEL0),
2441
2442 /* Port126 */
2443 GPIO_FN(TS_SDEN),
2444 GPIO_FN(MSIOF7_SYNC),
2445 GPIO_FN(STP_ISEN_1),
2446
2447 /* Port128 */
2448 GPIO_FN(STP_ISEN_0),
2449 GPIO_FN(PDM1_OUTDATA_128),
2450 GPIO_FN(MSIOF2_SYNC),
2451 GPIO_FN(SIM1_VOLTSEL1),
2452
2453 /* Port129 */
2454 GPIO_FN(TS_SPSYNC),
2455 GPIO_FN(MSIOF7_RXD),
2456 GPIO_FN(STP_ISSYNC_1),
2457
2458 /* Port130 */
2459 GPIO_FN(STP_ISSYNC_0),
2460 GPIO_FN(PDM4_DATA_130),
2461 GPIO_FN(MSIOF2_RXD),
2462 GPIO_FN(SIM0_VOLTSEL1),
2463
2464 /* Port131 */
2465 GPIO_FN(STP_OPWM_0),
2466 GPIO_FN(SIM1_PWRON),
2467
2468 /* Port132 */
2469 GPIO_FN(TS_SCK),
2470 GPIO_FN(MSIOF7_SCK),
2471 GPIO_FN(STP_ISCLK_1),
2472
2473 /* Port133 */
2474 GPIO_FN(STP_ISCLK_0),
2475 GPIO_FN(PDM1_OUTCLK_133),
2476 GPIO_FN(MSIOF2_SCK),
2477 GPIO_FN(SIM1_VOLTSEL0),
2478
2479 /* Port134 */
2480 GPIO_FN(TS_SDAT),
2481 GPIO_FN(MSIOF7_TXD),
2482 GPIO_FN(STP_ISD_1),
2483
2484 /* Port160 - Port178 */
2485 GPIO_FN(IRQ20),
2486 GPIO_FN(IRQ21),
2487 GPIO_FN(IRQ22),
2488 GPIO_FN(IRQ23),
2489 GPIO_FN(MMCD0_0),
2490 GPIO_FN(MMCD0_1),
2491 GPIO_FN(MMCD0_2),
2492 GPIO_FN(MMCD0_3),
2493 GPIO_FN(MMCD0_4),
2494 GPIO_FN(MMCD0_5),
2495 GPIO_FN(MMCD0_6),
2496 GPIO_FN(MMCD0_7),
2497 GPIO_FN(MMCCMD0),
2498 GPIO_FN(MMCCLK0),
2499 GPIO_FN(MMCRST),
2500 GPIO_FN(IRQ24),
2501 GPIO_FN(IRQ25),
2502 GPIO_FN(IRQ26),
2503 GPIO_FN(IRQ27),
2504
2505 /* Port192 - Port200 FN1 */
2506 GPIO_FN(A10),
2507 GPIO_FN(A9),
2508 GPIO_FN(A8),
2509 GPIO_FN(A7),
2510 GPIO_FN(A6),
2511 GPIO_FN(A5),
2512 GPIO_FN(A4),
2513 GPIO_FN(A3),
2514 GPIO_FN(A2),
2515
2516 /* Port192 - Port200 FN2 */
2517 GPIO_FN(MMCD1_7),
2518 GPIO_FN(MMCD1_6),
2519 GPIO_FN(MMCD1_5),
2520 GPIO_FN(MMCD1_4),
2521 GPIO_FN(MMCD1_3),
2522 GPIO_FN(MMCD1_2),
2523 GPIO_FN(MMCD1_1),
2524 GPIO_FN(MMCD1_0),
2525 GPIO_FN(MMCCMD1),
2526
2527 /* Port192 - Port200 IRQ */
2528 GPIO_FN(IRQ31),
2529 GPIO_FN(IRQ32),
2530 GPIO_FN(IRQ33),
2531 GPIO_FN(IRQ34),
2532 GPIO_FN(IRQ35),
2533 GPIO_FN(IRQ36),
2534 GPIO_FN(IRQ37),
2535 GPIO_FN(IRQ38),
2536 GPIO_FN(IRQ39),
2537
2538 /* Port201 */
2539 GPIO_FN(A1),
2540
2541 /* Port202 */
2542 GPIO_FN(A0),
2543 GPIO_FN(BS),
2544
2545 /* Port203 */
2546 GPIO_FN(CKO),
2547 GPIO_FN(MMCCLK1),
2548
2549 /* Port204 */
2550 GPIO_FN(CS0_N),
2551 GPIO_FN(SIM0_GPO1),
2552
2553 /* Port205 */
2554 GPIO_FN(CS2_N),
2555 GPIO_FN(SIM0_GPO2),
2556
2557 /* Port206 */
2558 GPIO_FN(CS4_N),
2559 GPIO_FN(VIO_VD),
2560 GPIO_FN(SIM1_GPO0),
2561
2562 /* Port207 - Port212 FN1 */
2563 GPIO_FN(D15),
2564 GPIO_FN(D14),
2565 GPIO_FN(D13),
2566 GPIO_FN(D12),
2567 GPIO_FN(D11),
2568 GPIO_FN(D10),
2569
2570 /* Port207 - Port212 FN5 */
2571 GPIO_FN(GIO_OUT15),
2572 GPIO_FN(GIO_OUT14),
2573 GPIO_FN(GIO_OUT13),
2574 GPIO_FN(GIO_OUT12),
2575 GPIO_FN(WGM_TXP2),
2576 GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK),
2577
2578 /* Port213 - Port222 FN1 */
2579 GPIO_FN(D9),
2580 GPIO_FN(D8),
2581 GPIO_FN(D7),
2582 GPIO_FN(D6),
2583 GPIO_FN(D5),
2584 GPIO_FN(D4),
2585 GPIO_FN(D3),
2586 GPIO_FN(D2),
2587 GPIO_FN(D1),
2588 GPIO_FN(D0),
2589
2590 /* Port213 - Port222 FN2 */
2591 GPIO_FN(VIO_D9),
2592 GPIO_FN(VIO_D8),
2593 GPIO_FN(VIO_D7),
2594 GPIO_FN(VIO_D6),
2595 GPIO_FN(VIO_D5),
2596 GPIO_FN(VIO_D4),
2597 GPIO_FN(VIO_D3),
2598 GPIO_FN(VIO_D2),
2599 GPIO_FN(VIO_D1),
2600 GPIO_FN(VIO_D0),
2601
2602 /* Port213 - Port222 FN5 */
2603 GPIO_FN(GIO_OUT9),
2604 GPIO_FN(GIO_OUT8),
2605 GPIO_FN(GIO_OUT7),
2606 GPIO_FN(GIO_OUT6),
2607 GPIO_FN(GIO_OUT5_217),
2608 GPIO_FN(GIO_OUT4_218),
2609 GPIO_FN(GIO_OUT3_219),
2610 GPIO_FN(GIO_OUT2_220),
2611 GPIO_FN(GIO_OUT1_221),
2612 GPIO_FN(GIO_OUT0_222),
2613
2614 /* Port224 */
2615 GPIO_FN(RDWR_224),
2616 GPIO_FN(VIO_HD),
2617 GPIO_FN(SIM1_GPO2),
2618
2619 /* Port225 */
2620 GPIO_FN(RD_N),
2621
2622 /* Port226 */
2623 GPIO_FN(WAIT_N),
2624 GPIO_FN(VIO_CLK),
2625 GPIO_FN(SIM1_GPO1),
2626
2627 /* Port227 */
2628 GPIO_FN(WE0_N),
2629 GPIO_FN(RDWR_227),
2630
2631 /* Port228 */
2632 GPIO_FN(WE1_N),
2633 GPIO_FN(SIM0_GPO0),
2634
2635 /* Port229 */
2636 GPIO_FN(PWMO),
2637 GPIO_FN(VIO_CKO1_229),
2638
2639 /* Port230 */
2640 GPIO_FN(SLIM_CLK),
2641 GPIO_FN(VIO_CKO4_230),
2642
2643 /* Port231 */
2644 GPIO_FN(SLIM_DATA),
2645 GPIO_FN(VIO_CKO5_231),
2646
2647 /* Port232 */
2648 GPIO_FN(VIO_CKO2_232),
2649 GPIO_FN(SF_PORT_0_232),
2650
2651 /* Port233 */
2652 GPIO_FN(VIO_CKO3_233),
2653 GPIO_FN(SF_PORT_1_233),
2654
2655 /* Port234 */
2656 GPIO_FN(FSIACK),
2657 GPIO_FN(PDM3_CLK_234),
2658 GPIO_FN(ISP_IRIS1_234),
2659
2660 /* Port235 */
2661 GPIO_FN(FSIAISLD),
2662 GPIO_FN(PDM3_DATA_235),
2663
2664 /* Port236 */
2665 GPIO_FN(FSIAOMC),
2666 GPIO_FN(PDM0_OUTCLK_236),
2667 GPIO_FN(ISP_IRIS0_236),
2668
2669 /* Port237 */
2670 GPIO_FN(FSIAOLR),
2671 GPIO_FN(FSIAILR),
2672
2673 /* Port238 */
2674 GPIO_FN(FSIAOBT),
2675 GPIO_FN(FSIAIBT),
2676
2677 /* Port239 */
2678 GPIO_FN(FSIAOSLD),
2679 GPIO_FN(PDM0_OUTDATA_239),
2680
2681 /* Port240 */
2682 GPIO_FN(FSIBISLD),
2683
2684 /* Port241 */
2685 GPIO_FN(FSIBOLR),
2686 GPIO_FN(FSIBILR),
2687
2688 /* Port242 */
2689 GPIO_FN(FSIBOMC),
2690 GPIO_FN(ISP_SHUTTER1_242),
2691
2692 /* Port243 */
2693 GPIO_FN(FSIBOBT),
2694 GPIO_FN(FSIBIBT),
2695
2696 /* Port244 */
2697 GPIO_FN(FSIBOSLD),
2698 GPIO_FN(FSIASPDIF),
2699
2700 /* Port245 */
2701 GPIO_FN(FSIBCK),
2702 GPIO_FN(ISP_SHUTTER0_245),
2703
2704 /* Port246 - Port250 FN1 */
2705 GPIO_FN(ISP_IRIS1_246),
2706 GPIO_FN(ISP_IRIS0_247),
2707 GPIO_FN(ISP_SHUTTER1_248),
2708 GPIO_FN(ISP_SHUTTER0_249),
2709 GPIO_FN(ISP_STROBE_250),
2710
2711 /* Port256 - Port258 */
2712 GPIO_FN(MSIOF0_SYNC),
2713 GPIO_FN(MSIOF0_RXD),
2714 GPIO_FN(MSIOF0_SCK),
2715
2716 /* Port259 */
2717 GPIO_FN(MSIOF0_SS2),
2718 GPIO_FN(VIO_CKO3_259),
2719
2720 /* Port260 */
2721 GPIO_FN(MSIOF0_TXD),
2722
2723 /* Port261 */
2724 GPIO_FN(SCIFB1_SCK_261),
2725 GPIO_FN(CHSCIF1_HSCK),
2726
2727 /* Port262 */
2728 GPIO_FN(SCIFB2_SCK_262),
2729
2730 /* Port263 - Port266 FN1 */
2731 GPIO_FN(MSIOF1_SS2),
2732 GPIO_FN(MSIOF1_TXD),
2733 GPIO_FN(MSIOF1_RXD),
2734 GPIO_FN(MSIOF1_SS1),
2735
2736 /* Port263 - Port266 FN4 */
2737 GPIO_FN(MSIOF5_SS2),
2738 GPIO_FN(MSIOF5_TXD),
2739 GPIO_FN(MSIOF5_RXD),
2740 GPIO_FN(MSIOF5_SS1),
2741
2742 /* Port267 */
2743 GPIO_FN(MSIOF0_SS1),
2744
2745 /* Port268 */
2746 GPIO_FN(MSIOF1_SCK),
2747 GPIO_FN(MSIOF5_SCK),
2748
2749 /* Port269 */
2750 GPIO_FN(MSIOF1_SYNC),
2751 GPIO_FN(MSIOF5_SYNC),
2752
2753 /* Port270 - Port273 FN1 */
2754 GPIO_FN(MSIOF2_SS1),
2755 GPIO_FN(MSIOF2_SS2),
2756 GPIO_FN(MSIOF3_SS2),
2757 GPIO_FN(MSIOF3_SS1),
2758
2759 /* Port270 - Port273 FN3 */
2760 GPIO_FN(VIO_CKO5_270),
2761 GPIO_FN(VIO_CKO2_271),
2762 GPIO_FN(VIO_CKO1_272),
2763 GPIO_FN(VIO_CKO4_273),
2764
2765 /* Port274 */
2766 GPIO_FN(MSIOF4_SS2),
2767 GPIO_FN(TPU1TO0),
2768
2769 /* Port275 - Port280 */
2770 GPIO_FN(IC_DP),
2771 GPIO_FN(SIM0_RST),
2772 GPIO_FN(IC_DM),
2773 GPIO_FN(SIM0_BSICOMP),
2774 GPIO_FN(SIM0_CLK),
2775 GPIO_FN(SIM0_IO),
2776
2777 /* Port281 */
2778 GPIO_FN(SIM1_IO),
2779 GPIO_FN(PDM2_DATA_281),
2780
2781 /* Port282 */
2782 GPIO_FN(SIM1_CLK),
2783 GPIO_FN(PDM2_CLK_282),
2784
2785 /* Port283 */
2786 GPIO_FN(SIM1_RST),
2787
2788 /* Port289 */
2789 GPIO_FN(SDHID1_0),
2790 GPIO_FN(STMDATA0_2),
2791
2792 /* Port290 */
2793 GPIO_FN(SDHID1_1),
2794 GPIO_FN(STMDATA1_2),
2795 GPIO_FN(IRQ51),
2796
2797 /* Port291 - Port294 FN1 */
2798 GPIO_FN(SDHID1_2),
2799 GPIO_FN(SDHID1_3),
2800 GPIO_FN(SDHICLK1),
2801 GPIO_FN(SDHICMD1),
2802
2803 /* Port291 - Port294 FN3 */
2804 GPIO_FN(STMDATA2_2),
2805 GPIO_FN(STMDATA3_2),
2806 GPIO_FN(STMCLK_2),
2807 GPIO_FN(STMSIDI_2),
2808
2809 /* Port295 */
2810 GPIO_FN(SDHID2_0),
2811 GPIO_FN(MSIOF4_TXD),
2812 GPIO_FN(SCIFB2_TXD_295),
2813 GPIO_FN(MSIOF6_TXD),
2814
2815 /* Port296 */
2816 GPIO_FN(SDHID2_1),
2817 GPIO_FN(MSIOF6_SS2),
2818 GPIO_FN(IRQ52),
2819
2820 /* Port297 - Port300 FN1 */
2821 GPIO_FN(SDHID2_2),
2822 GPIO_FN(SDHID2_3),
2823 GPIO_FN(SDHICLK2),
2824 GPIO_FN(SDHICMD2),
2825
2826 /* Port297 - Port300 FN2 */
2827 GPIO_FN(MSIOF4_RXD),
2828 GPIO_FN(MSIOF4_SYNC),
2829 GPIO_FN(MSIOF4_SCK),
2830 GPIO_FN(MSIOF4_SS1),
2831
2832 /* Port297 - Port300 FN3 */
2833 GPIO_FN(SCIFB2_RXD_297),
2834 GPIO_FN(SCIFB2_CTS_298),
2835 GPIO_FN(SCIFB2_SCK_299),
2836 GPIO_FN(SCIFB2_RTS_300),
2837
2838 /* Port297 - Port300 FN4 */
2839 GPIO_FN(MSIOF6_RXD),
2840 GPIO_FN(MSIOF6_SYNC),
2841 GPIO_FN(MSIOF6_SCK),
2842 GPIO_FN(MSIOF6_SS1),
2843
2844 /* Port301 */
2845 GPIO_FN(SDHICD0),
2846 GPIO_FN(IRQ50),
2847
2848 /* Port302 - Port306 FN1 */
2849 GPIO_FN(SDHID0_0),
2850 GPIO_FN(SDHID0_1),
2851 GPIO_FN(SDHID0_2),
2852 GPIO_FN(SDHID0_3),
2853 GPIO_FN(SDHICMD0),
2854
2855 /* Port302 - Port306 FN3 */
2856 GPIO_FN(STMDATA0_1),
2857 GPIO_FN(STMDATA1_1),
2858 GPIO_FN(STMDATA2_1),
2859 GPIO_FN(STMDATA3_1),
2860 GPIO_FN(STMSIDI_1),
2861
2862 /* Port307 */
2863 GPIO_FN(SDHIWP0),
2864
2865 /* Port308 */
2866 GPIO_FN(SDHICLK0),
2867 GPIO_FN(STMCLK_1),
2868
2869 /* Port320 - Port329 */
2870 GPIO_FN(IRQ16),
2871 GPIO_FN(IRQ17),
2872 GPIO_FN(IRQ28),
2873 GPIO_FN(IRQ29),
2874 GPIO_FN(IRQ30),
2875 GPIO_FN(IRQ53),
2876 GPIO_FN(IRQ54),
2877 GPIO_FN(IRQ55),
2878 GPIO_FN(IRQ56),
2879 GPIO_FN(IRQ57),
2880};
2881
2882static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2883
2884 PORTCR(0, 0xe6050000),
2885 PORTCR(1, 0xe6050001),
2886 PORTCR(2, 0xe6050002),
2887 PORTCR(3, 0xe6050003),
2888 PORTCR(4, 0xe6050004),
2889 PORTCR(5, 0xe6050005),
2890 PORTCR(6, 0xe6050006),
2891 PORTCR(7, 0xe6050007),
2892 PORTCR(8, 0xe6050008),
2893 PORTCR(9, 0xe6050009),
2894 PORTCR(10, 0xe605000A),
2895 PORTCR(11, 0xe605000B),
2896 PORTCR(12, 0xe605000C),
2897 PORTCR(13, 0xe605000D),
2898 PORTCR(14, 0xe605000E),
2899 PORTCR(15, 0xe605000F),
2900 PORTCR(16, 0xe6050010),
2901 PORTCR(17, 0xe6050011),
2902 PORTCR(18, 0xe6050012),
2903 PORTCR(19, 0xe6050013),
2904 PORTCR(20, 0xe6050014),
2905 PORTCR(21, 0xe6050015),
2906 PORTCR(22, 0xe6050016),
2907 PORTCR(23, 0xe6050017),
2908 PORTCR(24, 0xe6050018),
2909 PORTCR(25, 0xe6050019),
2910 PORTCR(26, 0xe605001A),
2911 PORTCR(27, 0xe605001B),
2912 PORTCR(28, 0xe605001C),
2913 PORTCR(29, 0xe605001D),
2914 PORTCR(30, 0xe605001E),
2915 PORTCR(32, 0xe6051020),
2916 PORTCR(33, 0xe6051021),
2917 PORTCR(34, 0xe6051022),
2918 PORTCR(35, 0xe6051023),
2919 PORTCR(36, 0xe6051024),
2920 PORTCR(37, 0xe6051025),
2921 PORTCR(38, 0xe6051026),
2922 PORTCR(39, 0xe6051027),
2923 PORTCR(40, 0xe6051028),
2924 PORTCR(64, 0xe6050040),
2925 PORTCR(65, 0xe6050041),
2926 PORTCR(66, 0xe6050042),
2927 PORTCR(67, 0xe6050043),
2928 PORTCR(68, 0xe6050044),
2929 PORTCR(69, 0xe6050045),
2930 PORTCR(70, 0xe6050046),
2931 PORTCR(71, 0xe6050047),
2932 PORTCR(72, 0xe6050048),
2933 PORTCR(73, 0xe6050049),
2934 PORTCR(74, 0xe605004A),
2935 PORTCR(75, 0xe605004B),
2936 PORTCR(76, 0xe605004C),
2937 PORTCR(77, 0xe605004D),
2938 PORTCR(78, 0xe605004E),
2939 PORTCR(79, 0xe605004F),
2940 PORTCR(80, 0xe6050050),
2941 PORTCR(81, 0xe6050051),
2942 PORTCR(82, 0xe6050052),
2943 PORTCR(83, 0xe6050053),
2944 PORTCR(84, 0xe6050054),
2945 PORTCR(85, 0xe6050055),
2946 PORTCR(96, 0xe6051060),
2947 PORTCR(97, 0xe6051061),
2948 PORTCR(98, 0xe6051062),
2949 PORTCR(99, 0xe6051063),
2950 PORTCR(100, 0xe6051064),
2951 PORTCR(101, 0xe6051065),
2952 PORTCR(102, 0xe6051066),
2953 PORTCR(103, 0xe6051067),
2954 PORTCR(104, 0xe6051068),
2955 PORTCR(105, 0xe6051069),
2956 PORTCR(106, 0xe605106A),
2957 PORTCR(107, 0xe605106B),
2958 PORTCR(108, 0xe605106C),
2959 PORTCR(109, 0xe605106D),
2960 PORTCR(110, 0xe605106E),
2961 PORTCR(111, 0xe605106F),
2962 PORTCR(112, 0xe6051070),
2963 PORTCR(113, 0xe6051071),
2964 PORTCR(114, 0xe6051072),
2965 PORTCR(115, 0xe6051073),
2966 PORTCR(116, 0xe6051074),
2967 PORTCR(117, 0xe6051075),
2968 PORTCR(118, 0xe6051076),
2969 PORTCR(119, 0xe6051077),
2970 PORTCR(120, 0xe6051078),
2971 PORTCR(121, 0xe6051079),
2972 PORTCR(122, 0xe605107A),
2973 PORTCR(123, 0xe605107B),
2974 PORTCR(124, 0xe605107C),
2975 PORTCR(125, 0xe605107D),
2976 PORTCR(126, 0xe605107E),
2977 PORTCR(128, 0xe6051080),
2978 PORTCR(129, 0xe6051081),
2979 PORTCR(130, 0xe6051082),
2980 PORTCR(131, 0xe6051083),
2981 PORTCR(132, 0xe6051084),
2982 PORTCR(133, 0xe6051085),
2983 PORTCR(134, 0xe6051086),
2984 PORTCR(160, 0xe60520A0),
2985 PORTCR(161, 0xe60520A1),
2986 PORTCR(162, 0xe60520A2),
2987 PORTCR(163, 0xe60520A3),
2988 PORTCR(164, 0xe60520A4),
2989 PORTCR(165, 0xe60520A5),
2990 PORTCR(166, 0xe60520A6),
2991 PORTCR(167, 0xe60520A7),
2992 PORTCR(168, 0xe60520A8),
2993 PORTCR(169, 0xe60520A9),
2994 PORTCR(170, 0xe60520AA),
2995 PORTCR(171, 0xe60520AB),
2996 PORTCR(172, 0xe60520AC),
2997 PORTCR(173, 0xe60520AD),
2998 PORTCR(174, 0xe60520AE),
2999 PORTCR(175, 0xe60520AF),
3000 PORTCR(176, 0xe60520B0),
3001 PORTCR(177, 0xe60520B1),
3002 PORTCR(178, 0xe60520B2),
3003 PORTCR(192, 0xe60520C0),
3004 PORTCR(193, 0xe60520C1),
3005 PORTCR(194, 0xe60520C2),
3006 PORTCR(195, 0xe60520C3),
3007 PORTCR(196, 0xe60520C4),
3008 PORTCR(197, 0xe60520C5),
3009 PORTCR(198, 0xe60520C6),
3010 PORTCR(199, 0xe60520C7),
3011 PORTCR(200, 0xe60520C8),
3012 PORTCR(201, 0xe60520C9),
3013 PORTCR(202, 0xe60520CA),
3014 PORTCR(203, 0xe60520CB),
3015 PORTCR(204, 0xe60520CC),
3016 PORTCR(205, 0xe60520CD),
3017 PORTCR(206, 0xe60520CE),
3018 PORTCR(207, 0xe60520CF),
3019 PORTCR(208, 0xe60520D0),
3020 PORTCR(209, 0xe60520D1),
3021 PORTCR(210, 0xe60520D2),
3022 PORTCR(211, 0xe60520D3),
3023 PORTCR(212, 0xe60520D4),
3024 PORTCR(213, 0xe60520D5),
3025 PORTCR(214, 0xe60520D6),
3026 PORTCR(215, 0xe60520D7),
3027 PORTCR(216, 0xe60520D8),
3028 PORTCR(217, 0xe60520D9),
3029 PORTCR(218, 0xe60520DA),
3030 PORTCR(219, 0xe60520DB),
3031 PORTCR(220, 0xe60520DC),
3032 PORTCR(221, 0xe60520DD),
3033 PORTCR(222, 0xe60520DE),
3034 PORTCR(224, 0xe60520E0),
3035 PORTCR(225, 0xe60520E1),
3036 PORTCR(226, 0xe60520E2),
3037 PORTCR(227, 0xe60520E3),
3038 PORTCR(228, 0xe60520E4),
3039 PORTCR(229, 0xe60520E5),
3040 PORTCR(230, 0xe60520e6),
3041 PORTCR(231, 0xe60520E7),
3042 PORTCR(232, 0xe60520E8),
3043 PORTCR(233, 0xe60520E9),
3044 PORTCR(234, 0xe60520EA),
3045 PORTCR(235, 0xe60520EB),
3046 PORTCR(236, 0xe60520EC),
3047 PORTCR(237, 0xe60520ED),
3048 PORTCR(238, 0xe60520EE),
3049 PORTCR(239, 0xe60520EF),
3050 PORTCR(240, 0xe60520F0),
3051 PORTCR(241, 0xe60520F1),
3052 PORTCR(242, 0xe60520F2),
3053 PORTCR(243, 0xe60520F3),
3054 PORTCR(244, 0xe60520F4),
3055 PORTCR(245, 0xe60520F5),
3056 PORTCR(246, 0xe60520F6),
3057 PORTCR(247, 0xe60520F7),
3058 PORTCR(248, 0xe60520F8),
3059 PORTCR(249, 0xe60520F9),
3060 PORTCR(250, 0xe60520FA),
3061 PORTCR(256, 0xe6052100),
3062 PORTCR(257, 0xe6052101),
3063 PORTCR(258, 0xe6052102),
3064 PORTCR(259, 0xe6052103),
3065 PORTCR(260, 0xe6052104),
3066 PORTCR(261, 0xe6052105),
3067 PORTCR(262, 0xe6052106),
3068 PORTCR(263, 0xe6052107),
3069 PORTCR(264, 0xe6052108),
3070 PORTCR(265, 0xe6052109),
3071 PORTCR(266, 0xe605210A),
3072 PORTCR(267, 0xe605210B),
3073 PORTCR(268, 0xe605210C),
3074 PORTCR(269, 0xe605210D),
3075 PORTCR(270, 0xe605210E),
3076 PORTCR(271, 0xe605210F),
3077 PORTCR(272, 0xe6052110),
3078 PORTCR(273, 0xe6052111),
3079 PORTCR(274, 0xe6052112),
3080 PORTCR(275, 0xe6052113),
3081 PORTCR(276, 0xe6052114),
3082 PORTCR(277, 0xe6052115),
3083 PORTCR(278, 0xe6052116),
3084 PORTCR(279, 0xe6052117),
3085 PORTCR(280, 0xe6052118),
3086 PORTCR(281, 0xe6052119),
3087 PORTCR(282, 0xe605211A),
3088 PORTCR(283, 0xe605211B),
3089 PORTCR(288, 0xe6053120),
3090 PORTCR(289, 0xe6053121),
3091 PORTCR(290, 0xe6053122),
3092 PORTCR(291, 0xe6053123),
3093 PORTCR(292, 0xe6053124),
3094 PORTCR(293, 0xe6053125),
3095 PORTCR(294, 0xe6053126),
3096 PORTCR(295, 0xe6053127),
3097 PORTCR(296, 0xe6053128),
3098 PORTCR(297, 0xe6053129),
3099 PORTCR(298, 0xe605312A),
3100 PORTCR(299, 0xe605312B),
3101 PORTCR(300, 0xe605312C),
3102 PORTCR(301, 0xe605312D),
3103 PORTCR(302, 0xe605312E),
3104 PORTCR(303, 0xe605312F),
3105 PORTCR(304, 0xe6053130),
3106 PORTCR(305, 0xe6053131),
3107 PORTCR(306, 0xe6053132),
3108 PORTCR(307, 0xe6053133),
3109 PORTCR(308, 0xe6053134),
3110 PORTCR(320, 0xe6053140),
3111 PORTCR(321, 0xe6053141),
3112 PORTCR(322, 0xe6053142),
3113 PORTCR(323, 0xe6053143),
3114 PORTCR(324, 0xe6053144),
3115 PORTCR(325, 0xe6053145),
3116 PORTCR(326, 0xe6053146),
3117 PORTCR(327, 0xe6053147),
3118 PORTCR(328, 0xe6053148),
3119 PORTCR(329, 0xe6053149),
3120
3121 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3122 MSEL1CR_31_0, MSEL1CR_31_1,
3123 0, 0,
3124 0, 0,
3125 0, 0,
3126 MSEL1CR_27_0, MSEL1CR_27_1,
3127 0, 0,
3128 MSEL1CR_25_0, MSEL1CR_25_1,
3129 MSEL1CR_24_0, MSEL1CR_24_1,
3130 0, 0,
3131 MSEL1CR_22_0, MSEL1CR_22_1,
3132 MSEL1CR_21_0, MSEL1CR_21_1,
3133 MSEL1CR_20_0, MSEL1CR_20_1,
3134 MSEL1CR_19_0, MSEL1CR_19_1,
3135 MSEL1CR_18_0, MSEL1CR_18_1,
3136 MSEL1CR_17_0, MSEL1CR_17_1,
3137 MSEL1CR_16_0, MSEL1CR_16_1,
3138 MSEL1CR_15_0, MSEL1CR_15_1,
3139 MSEL1CR_14_0, MSEL1CR_14_1,
3140 MSEL1CR_13_0, MSEL1CR_13_1,
3141 MSEL1CR_12_0, MSEL1CR_12_1,
3142 MSEL1CR_11_0, MSEL1CR_11_1,
3143 MSEL1CR_10_0, MSEL1CR_10_1,
3144 MSEL1CR_09_0, MSEL1CR_09_1,
3145 MSEL1CR_08_0, MSEL1CR_08_1,
3146 MSEL1CR_07_0, MSEL1CR_07_1,
3147 MSEL1CR_06_0, MSEL1CR_06_1,
3148 MSEL1CR_05_0, MSEL1CR_05_1,
3149 MSEL1CR_04_0, MSEL1CR_04_1,
3150 MSEL1CR_03_0, MSEL1CR_03_1,
3151 MSEL1CR_02_0, MSEL1CR_02_1,
3152 MSEL1CR_01_0, MSEL1CR_01_1,
3153 MSEL1CR_00_0, MSEL1CR_00_1,
3154 }
3155 },
3156 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3157 MSEL3CR_31_0, MSEL3CR_31_1,
3158 0, 0,
3159 0, 0,
3160 MSEL3CR_28_0, MSEL3CR_28_1,
3161 MSEL3CR_27_0, MSEL3CR_27_1,
3162 MSEL3CR_26_0, MSEL3CR_26_1,
3163 0, 0,
3164 0, 0,
3165 MSEL3CR_23_0, MSEL3CR_23_1,
3166 MSEL3CR_22_0, MSEL3CR_22_1,
3167 MSEL3CR_21_0, MSEL3CR_21_1,
3168 MSEL3CR_20_0, MSEL3CR_20_1,
3169 MSEL3CR_19_0, MSEL3CR_19_1,
3170 MSEL3CR_18_0, MSEL3CR_18_1,
3171 MSEL3CR_17_0, MSEL3CR_17_1,
3172 MSEL3CR_16_0, MSEL3CR_16_1,
3173 MSEL3CR_15_0, MSEL3CR_15_1,
3174 0, 0,
3175 0, 0,
3176 MSEL3CR_12_0, MSEL3CR_12_1,
3177 MSEL3CR_11_0, MSEL3CR_11_1,
3178 MSEL3CR_10_0, MSEL3CR_10_1,
3179 MSEL3CR_09_0, MSEL3CR_09_1,
3180 0, 0,
3181 0, 0,
3182 MSEL3CR_06_0, MSEL3CR_06_1,
3183 0, 0,
3184 0, 0,
3185 MSEL3CR_03_0, MSEL3CR_03_1,
3186 0, 0,
3187 MSEL3CR_01_0, MSEL3CR_01_1,
3188 MSEL3CR_00_0, MSEL3CR_00_1,
3189 }
3190 },
3191 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3192 0, 0,
3193 MSEL4CR_30_0, MSEL4CR_30_1,
3194 MSEL4CR_29_0, MSEL4CR_29_1,
3195 MSEL4CR_28_0, MSEL4CR_28_1,
3196 MSEL4CR_27_0, MSEL4CR_27_1,
3197 MSEL4CR_26_0, MSEL4CR_26_1,
3198 MSEL4CR_25_0, MSEL4CR_25_1,
3199 MSEL4CR_24_0, MSEL4CR_24_1,
3200 MSEL4CR_23_0, MSEL4CR_23_1,
3201 MSEL4CR_22_0, MSEL4CR_22_1,
3202 MSEL4CR_21_0, MSEL4CR_21_1,
3203 MSEL4CR_20_0, MSEL4CR_20_1,
3204 MSEL4CR_19_0, MSEL4CR_19_1,
3205 MSEL4CR_18_0, MSEL4CR_18_1,
3206 MSEL4CR_17_0, MSEL4CR_17_1,
3207 MSEL4CR_16_0, MSEL4CR_16_1,
3208 MSEL4CR_15_0, MSEL4CR_15_1,
3209 MSEL4CR_14_0, MSEL4CR_14_1,
3210 MSEL4CR_13_0, MSEL4CR_13_1,
3211 MSEL4CR_12_0, MSEL4CR_12_1,
3212 MSEL4CR_11_0, MSEL4CR_11_1,
3213 MSEL4CR_10_0, MSEL4CR_10_1,
3214 MSEL4CR_09_0, MSEL4CR_09_1,
3215 0, 0,
3216 MSEL4CR_07_0, MSEL4CR_07_1,
3217 0, 0,
3218 0, 0,
3219 MSEL4CR_04_0, MSEL4CR_04_1,
3220 0, 0,
3221 0, 0,
3222 MSEL4CR_01_0, MSEL4CR_01_1,
3223 0, 0,
3224 }
3225 },
3226 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
3227 MSEL5CR_31_0, MSEL5CR_31_1,
3228 MSEL5CR_30_0, MSEL5CR_30_1,
3229 MSEL5CR_29_0, MSEL5CR_29_1,
3230 MSEL5CR_28_0, MSEL5CR_28_1,
3231 MSEL5CR_27_0, MSEL5CR_27_1,
3232 MSEL5CR_26_0, MSEL5CR_26_1,
3233 MSEL5CR_25_0, MSEL5CR_25_1,
3234 MSEL5CR_24_0, MSEL5CR_24_1,
3235 MSEL5CR_23_0, MSEL5CR_23_1,
3236 MSEL5CR_22_0, MSEL5CR_22_1,
3237 MSEL5CR_21_0, MSEL5CR_21_1,
3238 MSEL5CR_20_0, MSEL5CR_20_1,
3239 MSEL5CR_19_0, MSEL5CR_19_1,
3240 MSEL5CR_18_0, MSEL5CR_18_1,
3241 MSEL5CR_17_0, MSEL5CR_17_1,
3242 MSEL5CR_16_0, MSEL5CR_16_1,
3243 MSEL5CR_15_0, MSEL5CR_15_1,
3244 MSEL5CR_14_0, MSEL5CR_14_1,
3245 MSEL5CR_13_0, MSEL5CR_13_1,
3246 MSEL5CR_12_0, MSEL5CR_12_1,
3247 MSEL5CR_11_0, MSEL5CR_11_1,
3248 MSEL5CR_10_0, MSEL5CR_10_1,
3249 MSEL5CR_09_0, MSEL5CR_09_1,
3250 MSEL5CR_08_0, MSEL5CR_08_1,
3251 MSEL5CR_07_0, MSEL5CR_07_1,
3252 MSEL5CR_06_0, MSEL5CR_06_1,
3253 0, 0,
3254 0, 0,
3255 0, 0,
3256 0, 0,
3257 0, 0,
3258 0, 0,
3259 }
3260 },
3261 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
3262 0, 0,
3263 0, 0,
3264 0, 0,
3265 0, 0,
3266 0, 0,
3267 0, 0,
3268 0, 0,
3269 0, 0,
3270 0, 0,
3271 0, 0,
3272 0, 0,
3273 0, 0,
3274 0, 0,
3275 0, 0,
3276 0, 0,
3277 MSEL8CR_16_0, MSEL8CR_16_1,
3278 0, 0,
3279 0, 0,
3280 0, 0,
3281 0, 0,
3282 0, 0,
3283 0, 0,
3284 0, 0,
3285 0, 0,
3286 0, 0,
3287 0, 0,
3288 0, 0,
3289 0, 0,
3290 0, 0,
3291 0, 0,
3292 MSEL8CR_01_0, MSEL8CR_01_1,
3293 MSEL8CR_00_0, MSEL8CR_00_1,
3294 }
3295 },
3296 { },
3297};
3298
3299static const struct pinmux_data_reg pinmux_data_regs[] = {
3300
3301 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3302 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3303 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3304 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3305 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3306 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3307 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3308 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3309 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
3310 }
3311 },
3312 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3313 0, 0, 0, 0,
3314 0, 0, 0, 0,
3315 0, 0, 0, 0,
3316 0, 0, 0, 0,
3317 0, 0, 0, 0,
3318 0, 0, 0, PORT40_DATA,
3319 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3320 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
3321 }
3322 },
3323 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
3324 0, 0, 0, 0,
3325 0, 0, 0, 0,
3326 0, 0, PORT85_DATA, PORT84_DATA,
3327 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3328 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3329 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3330 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3331 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
3332 }
3333 },
3334 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
3335 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3336 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3337 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3338 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3339 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3340 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3341 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3342 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
3343 }
3344 },
3345 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
3346 0, 0, 0, 0,
3347 0, 0, 0, 0,
3348 0, 0, 0, 0,
3349 0, 0, 0, 0,
3350 0, 0, 0, 0,
3351 0, 0, 0, 0,
3352 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3353 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
3354 }
3355 },
3356 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
3357 0, 0, 0, 0,
3358 0, 0, 0, 0,
3359 0, 0, 0, 0,
3360 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3361 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3362 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3363 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3364 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
3365 }
3366 },
3367 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
3368 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
3369 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
3370 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
3371 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
3372 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3373 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3374 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3375 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
3376 }
3377 },
3378 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
3379 0, 0, 0, 0,
3380 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
3381 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
3382 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
3383 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
3384 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
3385 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
3386 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
3387 }
3388 },
3389 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
3390 0, 0, 0, 0,
3391 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
3392 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
3393 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
3394 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
3395 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
3396 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
3397 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
3398 }
3399 },
3400 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
3401 0, 0, 0, 0,
3402 0, 0, 0, 0,
3403 0, 0, 0, PORT308_DATA,
3404 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
3405 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
3406 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
3407 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
3408 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
3409 }
3410 },
3411 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
3412 0, 0, 0, 0,
3413 0, 0, 0, 0,
3414 0, 0, 0, 0,
3415 0, 0, 0, 0,
3416 0, 0, 0, 0,
3417 0, 0, PORT329_DATA, PORT328_DATA,
3418 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
3419 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
3420 }
3421 },
3422 { },
3423};
3424
Magnus Dammc96931c2013-03-26 22:50:09 +0900[diff] [blame]3425static const struct pinmux_irq pinmux_irqs[] = {
3426 PINMUX_IRQ(irq_pin(0), 0),
3427 PINMUX_IRQ(irq_pin(1), 1),
3428 PINMUX_IRQ(irq_pin(2), 2),
3429 PINMUX_IRQ(irq_pin(3), 3),
3430 PINMUX_IRQ(irq_pin(4), 4),
3431 PINMUX_IRQ(irq_pin(5), 5),
3432 PINMUX_IRQ(irq_pin(6), 6),
3433 PINMUX_IRQ(irq_pin(7), 7),
3434 PINMUX_IRQ(irq_pin(8), 8),
3435 PINMUX_IRQ(irq_pin(9), 9),
3436 PINMUX_IRQ(irq_pin(10), 10),
3437 PINMUX_IRQ(irq_pin(11), 11),
3438 PINMUX_IRQ(irq_pin(12), 12),
3439 PINMUX_IRQ(irq_pin(13), 13),
3440 PINMUX_IRQ(irq_pin(14), 14),
3441 PINMUX_IRQ(irq_pin(15), 15),
3442 PINMUX_IRQ(irq_pin(16), 320),
3443 PINMUX_IRQ(irq_pin(17), 321),
3444 PINMUX_IRQ(irq_pin(18), 85),
3445 PINMUX_IRQ(irq_pin(19), 84),
3446 PINMUX_IRQ(irq_pin(20), 160),
3447 PINMUX_IRQ(irq_pin(21), 161),
3448 PINMUX_IRQ(irq_pin(22), 162),
3449 PINMUX_IRQ(irq_pin(23), 163),
3450 PINMUX_IRQ(irq_pin(24), 175),
3451 PINMUX_IRQ(irq_pin(25), 176),
3452 PINMUX_IRQ(irq_pin(26), 177),
3453 PINMUX_IRQ(irq_pin(27), 178),
3454 PINMUX_IRQ(irq_pin(28), 322),
3455 PINMUX_IRQ(irq_pin(29), 323),
3456 PINMUX_IRQ(irq_pin(30), 324),
3457 PINMUX_IRQ(irq_pin(31), 192),
3458 PINMUX_IRQ(irq_pin(32), 193),
3459 PINMUX_IRQ(irq_pin(33), 194),
3460 PINMUX_IRQ(irq_pin(34), 195),
3461 PINMUX_IRQ(irq_pin(35), 196),
3462 PINMUX_IRQ(irq_pin(36), 197),
3463 PINMUX_IRQ(irq_pin(37), 198),
3464 PINMUX_IRQ(irq_pin(38), 199),
3465 PINMUX_IRQ(irq_pin(39), 200),
3466 PINMUX_IRQ(irq_pin(40), 66),
3467 PINMUX_IRQ(irq_pin(41), 102),
3468 PINMUX_IRQ(irq_pin(42), 103),
3469 PINMUX_IRQ(irq_pin(43), 109),
3470 PINMUX_IRQ(irq_pin(44), 110),
3471 PINMUX_IRQ(irq_pin(45), 111),
3472 PINMUX_IRQ(irq_pin(46), 112),
3473 PINMUX_IRQ(irq_pin(47), 113),
3474 PINMUX_IRQ(irq_pin(48), 114),
3475 PINMUX_IRQ(irq_pin(49), 115),
3476 PINMUX_IRQ(irq_pin(50), 301),
3477 PINMUX_IRQ(irq_pin(51), 290),
3478 PINMUX_IRQ(irq_pin(52), 296),
3479 PINMUX_IRQ(irq_pin(53), 325),
3480 PINMUX_IRQ(irq_pin(54), 326),
3481 PINMUX_IRQ(irq_pin(55), 327),
3482 PINMUX_IRQ(irq_pin(56), 328),
3483 PINMUX_IRQ(irq_pin(57), 329),
3484};
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]3485
3486#define PORTCR_PULMD_OFF (0 << 6)
3487#define PORTCR_PULMD_DOWN (2 << 6)
3488#define PORTCR_PULMD_UP (3 << 6)
3489#define PORTCR_PULMD_MASK (3 << 6)
3490
3491static const unsigned int r8a73a4_portcr_offsets[] = {
3492 0x00000000, 0x00001000, 0x00000000, 0x00001000,
3493 0x00001000, 0x00002000, 0x00002000, 0x00002000,
3494 0x00002000, 0x00003000, 0x00003000,
3495};
3496
3497static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
3498 unsigned int pin)
3499{
3500 void __iomem *addr;
3501
3502 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
3503
3504 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
3505 case PORTCR_PULMD_UP:
3506 return PIN_CONFIG_BIAS_PULL_UP;
3507 case PORTCR_PULMD_DOWN:
3508 return PIN_CONFIG_BIAS_PULL_DOWN;
3509 case PORTCR_PULMD_OFF:
3510 default:
3511 return PIN_CONFIG_BIAS_DISABLE;
3512 }
3513}
3514
3515static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3516 unsigned int bias)
3517{
3518 void __iomem *addr;
3519 u32 value;
3520
3521 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
3522 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
3523
3524 switch (bias) {
3525 case PIN_CONFIG_BIAS_PULL_UP:
3526 value |= PORTCR_PULMD_UP;
3527 break;
3528 case PIN_CONFIG_BIAS_PULL_DOWN:
3529 value |= PORTCR_PULMD_DOWN;
3530 break;
3531 }
3532
3533 iowrite8(value, addr);
3534}
3535
3536static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
3537 .get_bias = r8a73a4_pinmux_get_bias,
3538 .set_bias = r8a73a4_pinmux_set_bias,
3539};
3540
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3541const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
3542 .name = "r8a73a4_pfc",
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]3543 .ops = &r8a73a4_pinmux_ops,
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3544
3545 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3546 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
3547 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
3548 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3549 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3550
3551 .pins = pinmux_pins,
3552 .nr_pins = ARRAY_SIZE(pinmux_pins),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]3553
Magnus Dammf365bfc2013-03-26 22:49:59 +0900[diff] [blame]3554 .ranges = pinmux_ranges,
3555 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]3556
3557 .groups = pinmux_groups,
3558 .nr_groups = ARRAY_SIZE(pinmux_groups),
3559 .functions = pinmux_functions,
3560 .nr_functions = ARRAY_SIZE(pinmux_functions),
3561
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3562 .func_gpios = pinmux_func_gpios,
3563 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3564
3565 .cfg_regs = pinmux_config_regs,
3566 .data_regs = pinmux_data_regs,
3567
3568 .gpio_data = pinmux_data,
3569 .gpio_data_size = ARRAY_SIZE(pinmux_data),
Magnus Dammc96931c2013-03-26 22:50:09 +0900[diff] [blame]3570
3571 .gpio_irq = pinmux_irqs,
3572 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3573};