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review.evervolv.com / android_kernel_oneplus_msm8996 / 53dfa8e4aa740cc7a19a39d6d4542f856c6b49ae / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 110d6cbb795b384aa330c422d6409057839bb3ee [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 };
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]11 intc: interrupt-controller {
12 compatible = "marvell,orion-intc", "marvell,intc";
13 interrupt-controller;
14 #interrupt-cells = <1>;
15 reg = <0xf1020204 0x04>,
16 <0xf1020214 0x04>;
17 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]18
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]19 ocp@f1000000 {
20 compatible = "simple-bus";
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]21 ranges = <0x00000000 0xf1000000 0x4000000
22 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]23 #address-cells = <1>;
24 #size-cells = <1>;
25
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]26 core_clk: core-clocks@10030 {
27 compatible = "marvell,kirkwood-core-clock";
28 reg = <0x10030 0x4>;
29 #clock-cells = <1>;
30 };
31
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]32 gpio0: gpio@10100 {
33 compatible = "marvell,orion-gpio";
34 #gpio-cells = <2>;
35 gpio-controller;
36 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]37 ngpios = <32>;
38 interrupt-controller;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]39 interrupts = <35>, <36>, <37>, <38>;
40 };
41
42 gpio1: gpio@10140 {
43 compatible = "marvell,orion-gpio";
44 #gpio-cells = <2>;
45 gpio-controller;
46 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]47 ngpios = <18>;
48 interrupt-controller;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]49 interrupts = <39>, <40>, <41>;
50 };
51
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]52 serial@12000 {
53 compatible = "ns16550a";
54 reg = <0x12000 0x100>;
55 reg-shift = <2>;
56 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]57 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]58 /* set clock-frequency in board dts */
59 status = "disabled";
60 };
61
62 serial@12100 {
63 compatible = "ns16550a";
64 reg = <0x12100 0x100>;
65 reg-shift = <2>;
66 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]67 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]68 /* set clock-frequency in board dts */
69 status = "disabled";
70 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]71
72 rtc@10300 {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]73 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]74 reg = <0x10300 0x20>;
75 interrupts = <53>;
76 };
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]77
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]78 spi@10600 {
79 compatible = "marvell,orion-spi";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 cell-index = <0>;
83 interrupts = <23>;
84 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]85 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]86 status = "disabled";
87 };
88
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]89 gate_clk: clock-gating-control@2011c {
90 compatible = "marvell,kirkwood-gating-clock";
91 reg = <0x2011c 0x4>;
92 clocks = <&core_clk 0>;
93 #clock-cells = <1>;
94 };
95
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]96 wdt@20300 {
97 compatible = "marvell,orion-wdt";
98 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]99 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]100 status = "okay";
101 };
102
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame]103 xor@60800 {
104 compatible = "marvell,orion-xor";
105 reg = <0x60800 0x100
106 0x60A00 0x100>;
107 status = "okay";
108 clocks = <&gate_clk 8>;
109
110 xor00 {
111 interrupts = <5>;
112 dmacap,memcpy;
113 dmacap,xor;
114 };
115 xor01 {
116 interrupts = <6>;
117 dmacap,memcpy;
118 dmacap,xor;
119 dmacap,memset;
120 };
121 };
122
123 xor@60900 {
124 compatible = "marvell,orion-xor";
125 reg = <0x60900 0x100
126 0xd0B00 0x100>;
127 status = "okay";
128 clocks = <&gate_clk 16>;
129
130 xor00 {
131 interrupts = <7>;
132 dmacap,memcpy;
133 dmacap,xor;
134 };
135 xor01 {
136 interrupts = <8>;
137 dmacap,memcpy;
138 dmacap,xor;
139 dmacap,memset;
140 };
141 };
142
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]143 ehci@50000 {
144 compatible = "marvell,orion-ehci";
145 reg = <0x50000 0x1000>;
146 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100[diff] [blame^]147 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]148 status = "okay";
149 };
150
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]151 sata@80000 {
152 compatible = "marvell,orion-sata";
153 reg = <0x80000 0x5000>;
154 interrupts = <21>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]155 clocks = <&gate_clk 14>, <&gate_clk 15>;
156 clock-names = "0", "1";
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]157 status = "disabled";
158 };
159
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]160 nand@3000000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 cle = <0>;
164 ale = <1>;
165 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]166 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]167 reg = <0x3000000 0x400>;
168 chip-delay = <25>;
169 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]170 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]171 status = "disabled";
172 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]173
174 i2c@11000 {
175 compatible = "marvell,mv64xxx-i2c";
176 reg = <0x11000 0x20>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 interrupts = <29>;
180 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]181 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]182 status = "disabled";
183 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]184
185 crypto@30000 {
186 compatible = "marvell,orion-crypto";
187 reg = <0x30000 0x10000>,
188 <0xf5000000 0x800>;
189 reg-names = "regs", "sram";
190 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]191 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]192 status = "okay";
193 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]194 };
195};