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review.evervolv.com / android_kernel_oneplus_msm8996 / 547dc12858146efa2720d62052642b2b6095919b / . / arch / arm / boot / dts / imx6dl.dtsi
blob: 023ac83937c98027ec9152a33145f75d27013efd [file] [log] [blame]
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]11#include "imx6qdl.dtsi"
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]12#include "imx6dl-pinfunc.h"
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24
25 cpu@1 {
26 compatible = "arm,cortex-a9";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
31
32 soc {
33 aips1: aips-bus@02000000 {
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]34 iomuxc: iomuxc@020e0000 {
35 compatible = "fsl,imx6dl-iomuxc";
36 reg = <0x020e0000 0x4000>;
37
Nicolin Chen547dc122013-06-13 19:50:59 +0800[diff] [blame^]38 audmux {
39 pinctrl_audmux_2: audmux-2 {
40 fsl,pins = <
41 MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
42 MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
43 MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
44 MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
45 >;
46 };
47 };
48
Huang Shijie32d77d12013-05-09 11:29:00 +0800[diff] [blame]49 ecspi1 {
50 pinctrl_ecspi1_1: ecspi1grp-1 {
51 fsl,pins = <
52 MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
53 MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
54 MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
55 >;
56 };
57 };
58
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]59 enet {
60 pinctrl_enet_1: enetgrp-1 {
61 fsl,pins = <
62 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
63 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
64 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
65 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
66 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
67 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
68 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
69 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
70 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
71 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
72 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
73 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
74 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
75 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
76 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
77 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
78 >;
79 };
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]80
81 pinctrl_enet_2: enetgrp-2 {
82 fsl,pins = <
83 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
84 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
85 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
86 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
87 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
88 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
89 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
90 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
91 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
92 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
93 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
94 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
95 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
96 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
97 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
98 >;
99 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]100 };
101
Huang Shijiedb372422013-05-07 15:39:19 +0800[diff] [blame]102 gpmi-nand {
103 pinctrl_gpmi_nand_1: gpmi-nand-1 {
104 fsl,pins = <
105 MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
106 MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
107 MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
108 MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
109 MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
110 MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
111 MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
112 MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
113 MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
114 MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
115 MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
116 MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
117 MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
118 MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
119 MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
120 MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
121 MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
122 >;
123 };
124 };
125
Nicolin Chenee531432013-06-13 19:50:58 +0800[diff] [blame]126 i2c1 {
127 pinctrl_i2c1_2: i2c1grp-2 {
128 fsl,pins = <
129 MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
130 MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
131 >;
132 };
133 };
134
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]135 uart1 {
136 pinctrl_uart1_1: uart1grp-1 {
137 fsl,pins = <
138 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
139 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
140 >;
141 };
142 };
143
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]144 uart4 {
145 pinctrl_uart4_1: uart4grp-1 {
146 fsl,pins = <
147 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
148 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
149 >;
150 };
151 };
152
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]153 usbotg {
154 pinctrl_usbotg_2: usbotggrp-2 {
155 fsl,pins = <
156 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
157 >;
158 };
159 };
160
161 usdhc2 {
162 pinctrl_usdhc2_1: usdhc2grp-1 {
163 fsl,pins = <
164 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
165 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
166 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
167 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
168 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
169 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
170 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
171 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
172 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
173 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
174 >;
175 };
176 };
177
178 usdhc3 {
179 pinctrl_usdhc3_1: usdhc3grp-1 {
180 fsl,pins = <
181 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
182 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
183 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
184 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
185 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
186 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
187 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
188 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
189 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
190 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
191 >;
192 };
Fabio Estevam89b82912013-04-03 09:29:16 -0300[diff] [blame]193
194 pinctrl_usdhc3_2: usdhc3grp_2 {
195 fsl,pins = <
196 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
197 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
198 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
199 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
200 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
201 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
202 >;
203 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]204 };
205
Huang Shijie9feded12013-05-28 14:20:11 +0800[diff] [blame]206 weim {
207 pinctrl_weim_cs0_1: weim_cs0grp-1 {
208 fsl,pins = <
209 MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
210 >;
211 };
212
213 pinctrl_weim_nor_1: weim_norgrp-1 {
214 fsl,pins = <
215 MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
216 MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
217 MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
218 /* data */
219 MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
220 MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
221 MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
222 MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
223 MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
224 MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
225 MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
226 MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
227 MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
228 MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
229 MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
230 MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
231 MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
232 MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
233 MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
234 MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
235 /* address */
236 MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
237 MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
238 MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
239 MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
240 MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
241 MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
242 MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
243 MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
244 MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
245 MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
246 MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
247 MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
248 MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
249 MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
250 MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
251 MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
252 MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
253 MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
254 MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
255 MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
256 MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
257 MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
258 MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
259 MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
260 >;
261 };
262
263 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]264
265 };
266
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]267 pxp: pxp@020f0000 {
268 reg = <0x020f0000 0x4000>;
269 interrupts = <0 98 0x04>;
270 };
271
272 epdc: epdc@020f4000 {
273 reg = <0x020f4000 0x4000>;
274 interrupts = <0 97 0x04>;
275 };
276
277 lcdif: lcdif@020f8000 {
278 reg = <0x020f8000 0x4000>;
279 interrupts = <0 39 0x04>;
280 };
281 };
282
283 aips2: aips-bus@02100000 {
284 i2c4: i2c@021f8000 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "fsl,imx1-i2c";
288 reg = <0x021f8000 0x4000>;
289 interrupts = <0 35 0x04>;
290 status = "disabled";
291 };
292 };
293 };
294};