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review.evervolv.com / android_kernel_oneplus_msm8996 / 549985ee9c723fea8fd7759b5046fb8249896d50 / . / Documentation / devicetree / bindings / net / cpsw.txt
blob: 6ddd0286a9b7514fe00a5f150e05859da0f25e36 [file] [log] [blame]
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]1TI SoC Ethernet Switch Controller Device Tree Bindings
2------------------------------------------------------
3
4Required properties:
5- compatible : Should be "ti,cpsw"
6- reg : physical base address and size of the cpsw
7 registers map
8- interrupts : property with a value describing the interrupt
9 number
10- interrupt-parent : The parent interrupt controller
11- cpdma_channels : Specifies number of channels in CPDMA
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]12- ale_entries : Specifies No of entries ALE can hold
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]13- bd_ram_size : Specifies internal descriptor RAM size
14- rx_descs : Specifies number of Rx descriptors
15- mac_control : Specifies Default MAC control register content
16 for the specific platform
17- slaves : Specifies number for slaves
Richard Cochran78ca0b22012-10-29 08:45:18 +0000[diff] [blame]18- cpts_active_slave : Specifies the slave to use for time stamping
Richard Cochran00ab94e2012-10-29 08:45:19 +0000[diff] [blame]19- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds
20- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]21- phy_id : Specifies slave phy id
22- mac-address : Specifies slave MAC address
23
24Optional properties:
25- ti,hwmods : Must be "cpgmac0"
26- no_bd_ram : Must be 0 or 1
27
28Note: "ti,hwmods" field is used to fetch the base address and irq
29resources from TI, omap hwmod data base during device registration.
30Future plan is to migrate hwmod data base contents into device tree
31blob so that, all the required data will be used from device tree dts
32file.
33
34Examples:
35
36 mac: ethernet@4A100000 {
37 compatible = "ti,cpsw";
38 reg = <0x4A100000 0x1000>;
39 interrupts = <55 0x4>;
40 interrupt-parent = <&intc>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]41 cpdma_channels = <8>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]42 ale_entries = <1024>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]43 bd_ram_size = <0x2000>;
44 no_bd_ram = <0>;
45 rx_descs = <64>;
46 mac_control = <0x20>;
47 slaves = <2>;
Richard Cochran78ca0b22012-10-29 08:45:18 +0000[diff] [blame]48 cpts_active_slave = <0>;
Richard Cochran00ab94e2012-10-29 08:45:19 +0000[diff] [blame]49 cpts_clock_mult = <0x80000000>;
50 cpts_clock_shift = <29>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]51 cpsw_emac0: slave@0 {
Richard Cochran549985e2012-11-14 09:07:56 +0000[diff] [blame^]52 phy_id = <&davinci_mdio>, <0>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]53 /* Filled in by U-Boot */
54 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]55 };
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]56 cpsw_emac1: slave@1 {
Richard Cochran549985e2012-11-14 09:07:56 +0000[diff] [blame^]57 phy_id = <&davinci_mdio>, <1>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]58 /* Filled in by U-Boot */
59 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]60 };
61 };
62
63(or)
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]64 mac: ethernet@4A100000 {
65 compatible = "ti,cpsw";
66 ti,hwmods = "cpgmac0";
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]67 cpdma_channels = <8>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]68 ale_entries = <1024>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]69 bd_ram_size = <0x2000>;
70 no_bd_ram = <0>;
71 rx_descs = <64>;
72 mac_control = <0x20>;
73 slaves = <2>;
Richard Cochran78ca0b22012-10-29 08:45:18 +0000[diff] [blame]74 cpts_active_slave = <0>;
Richard Cochran00ab94e2012-10-29 08:45:19 +0000[diff] [blame]75 cpts_clock_mult = <0x80000000>;
76 cpts_clock_shift = <29>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]77 cpsw_emac0: slave@0 {
Richard Cochran549985e2012-11-14 09:07:56 +0000[diff] [blame^]78 phy_id = <&davinci_mdio>, <0>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]79 /* Filled in by U-Boot */
80 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]81 };
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]82 cpsw_emac1: slave@1 {
Richard Cochran549985e2012-11-14 09:07:56 +0000[diff] [blame^]83 phy_id = <&davinci_mdio>, <1>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]84 /* Filled in by U-Boot */
85 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]86 };
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]87 };