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review.evervolv.com / android_kernel_oneplus_msm8996 / 570727b5520878d1263e33f118463d77d7fd92d1 / . / drivers / dma / ioat / hw.h
blob: 8cfa07789888be3f7adc955dd678bb0a47417449 [file] [log] [blame]
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]1/*
Maciej Sosnowski211a22c2009-02-26 11:05:43 +0100[diff] [blame]2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef _IOAT_HW_H_
22#define _IOAT_HW_H_
23
24/* PCI Configuration Space Values */
Dan Williamse6c0b692009-09-08 17:29:44 -0700[diff] [blame]25#define IOAT_MMIO_BAR 0
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800[diff] [blame]26
27/* CB device ID's */
28#define IOAT_PCI_DID_5000 0x1A38
29#define IOAT_PCI_DID_CNB 0x360B
30#define IOAT_PCI_DID_SCNB 0x65FF
31#define IOAT_PCI_DID_SNB 0x402F
32
Dave Jiang1a363062012-12-03 16:08:37 -0700[diff] [blame]33#define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
34#define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
35#define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
36#define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
37#define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
38#define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
39#define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
40#define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
41#define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
42#define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
43
Dave Jiang570727b2013-03-25 14:37:31 -0700[diff] [blame^]44#define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
45#define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
46#define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
47#define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
48#define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
49#define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
50#define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
51#define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
52#define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
53#define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
54
55#define IOAT_VER_1_2 0x12 /* Version 1.2 */
56#define IOAT_VER_2_0 0x20 /* Version 2.0 */
57#define IOAT_VER_3_0 0x30 /* Version 3.0 */
58#define IOAT_VER_3_2 0x32 /* Version 3.2 */
59
60
Dan Williams228c4f52009-11-19 17:07:10 -0700[diff] [blame]61int system_has_dca_enabled(struct pci_dev *pdev);
62
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]63struct ioat_dma_descriptor {
64 uint32_t size;
Dan Williamsc7984f42009-07-28 14:44:04 -0700[diff] [blame]65 union {
66 uint32_t ctl;
67 struct {
68 unsigned int int_en:1;
69 unsigned int src_snoop_dis:1;
70 unsigned int dest_snoop_dis:1;
71 unsigned int compl_write:1;
72 unsigned int fence:1;
73 unsigned int null:1;
74 unsigned int src_brk:1;
75 unsigned int dest_brk:1;
76 unsigned int bundle:1;
77 unsigned int dest_dca:1;
78 unsigned int hint:1;
79 unsigned int rsvd2:13;
Dan Williams2aec0482009-09-08 17:42:54 -0700[diff] [blame]80 #define IOAT_OP_COPY 0x00
Dan Williamsc7984f42009-07-28 14:44:04 -0700[diff] [blame]81 unsigned int op:8;
82 } ctl_f;
83 };
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]84 uint64_t src_addr;
85 uint64_t dst_addr;
86 uint64_t next;
87 uint64_t rsv1;
88 uint64_t rsv2;
Dan Williamsad643f52009-09-08 12:01:38 -0700[diff] [blame]89 /* store some driver data in an unused portion of the descriptor */
90 union {
91 uint64_t user1;
92 uint64_t tx_cnt;
93 };
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]94 uint64_t user2;
95};
Dan Williams2aec0482009-09-08 17:42:54 -0700[diff] [blame]96
97struct ioat_fill_descriptor {
98 uint32_t size;
99 union {
100 uint32_t ctl;
101 struct {
102 unsigned int int_en:1;
103 unsigned int rsvd:1;
104 unsigned int dest_snoop_dis:1;
105 unsigned int compl_write:1;
106 unsigned int fence:1;
107 unsigned int rsvd2:2;
108 unsigned int dest_brk:1;
109 unsigned int bundle:1;
110 unsigned int rsvd4:15;
111 #define IOAT_OP_FILL 0x01
112 unsigned int op:8;
113 } ctl_f;
114 };
115 uint64_t src_data;
116 uint64_t dst_addr;
117 uint64_t next;
118 uint64_t rsv1;
119 uint64_t next_dst_addr;
120 uint64_t user1;
121 uint64_t user2;
122};
123
124struct ioat_xor_descriptor {
125 uint32_t size;
126 union {
127 uint32_t ctl;
128 struct {
129 unsigned int int_en:1;
130 unsigned int src_snoop_dis:1;
131 unsigned int dest_snoop_dis:1;
132 unsigned int compl_write:1;
133 unsigned int fence:1;
134 unsigned int src_cnt:3;
135 unsigned int bundle:1;
136 unsigned int dest_dca:1;
137 unsigned int hint:1;
138 unsigned int rsvd:13;
139 #define IOAT_OP_XOR 0x87
140 #define IOAT_OP_XOR_VAL 0x88
141 unsigned int op:8;
142 } ctl_f;
143 };
144 uint64_t src_addr;
145 uint64_t dst_addr;
146 uint64_t next;
147 uint64_t src_addr2;
148 uint64_t src_addr3;
149 uint64_t src_addr4;
150 uint64_t src_addr5;
151};
152
153struct ioat_xor_ext_descriptor {
154 uint64_t src_addr6;
155 uint64_t src_addr7;
156 uint64_t src_addr8;
157 uint64_t next;
158 uint64_t rsvd[4];
159};
160
161struct ioat_pq_descriptor {
162 uint32_t size;
163 union {
164 uint32_t ctl;
165 struct {
166 unsigned int int_en:1;
167 unsigned int src_snoop_dis:1;
168 unsigned int dest_snoop_dis:1;
169 unsigned int compl_write:1;
170 unsigned int fence:1;
171 unsigned int src_cnt:3;
172 unsigned int bundle:1;
173 unsigned int dest_dca:1;
174 unsigned int hint:1;
175 unsigned int p_disable:1;
176 unsigned int q_disable:1;
177 unsigned int rsvd:11;
178 #define IOAT_OP_PQ 0x89
179 #define IOAT_OP_PQ_VAL 0x8a
180 unsigned int op:8;
181 } ctl_f;
182 };
183 uint64_t src_addr;
184 uint64_t p_addr;
185 uint64_t next;
186 uint64_t src_addr2;
187 uint64_t src_addr3;
188 uint8_t coef[8];
189 uint64_t q_addr;
190};
191
192struct ioat_pq_ext_descriptor {
193 uint64_t src_addr4;
194 uint64_t src_addr5;
195 uint64_t src_addr6;
196 uint64_t next;
197 uint64_t src_addr7;
198 uint64_t src_addr8;
199 uint64_t rsvd[2];
200};
201
202struct ioat_pq_update_descriptor {
203 uint32_t size;
204 union {
205 uint32_t ctl;
206 struct {
207 unsigned int int_en:1;
208 unsigned int src_snoop_dis:1;
209 unsigned int dest_snoop_dis:1;
210 unsigned int compl_write:1;
211 unsigned int fence:1;
212 unsigned int src_cnt:3;
213 unsigned int bundle:1;
214 unsigned int dest_dca:1;
215 unsigned int hint:1;
216 unsigned int p_disable:1;
217 unsigned int q_disable:1;
218 unsigned int rsvd:3;
219 unsigned int coef:8;
220 #define IOAT_OP_PQ_UP 0x8b
221 unsigned int op:8;
222 } ctl_f;
223 };
224 uint64_t src_addr;
225 uint64_t p_addr;
226 uint64_t next;
227 uint64_t src_addr2;
228 uint64_t p_src;
229 uint64_t q_src;
230 uint64_t q_addr;
231};
232
233struct ioat_raw_descriptor {
234 uint64_t field[8];
235};
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]236#endif