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review.evervolv.com / android_kernel_oneplus_msm8996 / 5ab134ad09988ca8225e759a052df7a1bbd26145 / . / arch / arm / boot / dts / tegra20.dtsi
blob: f40cfbaa7c7e3a70438570dd2dde4626191dafad [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame^]7 cache-controller@50043000 {
8 compatible = "arm,pl310-cache";
9 reg = <0x50043000 0x1000>;
10 arm,data-latency = <5 5 2>;
11 arm,tag-latency = <4 4 2>;
12 cache-unified;
13 cache-level = <2>;
14 };
15
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]16 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]17 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]18 reg = <0x50041000 0x1000
19 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]20 interrupt-controller;
21 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]22 };
23
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]24 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]25 compatible = "nvidia,tegra20-apbdma";
26 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]27 interrupts = <0 104 0x04
28 0 105 0x04
29 0 106 0x04
30 0 107 0x04
31 0 108 0x04
32 0 109 0x04
33 0 110 0x04
34 0 111 0x04
35 0 112 0x04
36 0 113 0x04
37 0 114 0x04
38 0 115 0x04
39 0 116 0x04
40 0 117 0x04
41 0 118 0x04
42 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]43 };
44
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]45 ahb {
46 compatible = "nvidia,tegra20-ahb";
47 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]48 };
49
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]50 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]51 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]52 reg = <0x6000d000 0x1000>;
53 interrupts = <0 32 0x04
54 0 33 0x04
55 0 34 0x04
56 0 35 0x04
57 0 55 0x04
58 0 87 0x04
59 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]60 #gpio-cells = <2>;
61 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]62 #interrupt-cells = <2>;
63 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]64 };
65
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]66 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]67 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]68 reg = <0x70000014 0x10 /* Tri-state registers */
69 0x70000080 0x20 /* Mux registers */
70 0x700000a0 0x14 /* Pull-up/down registers */
71 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]72 };
73
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]74 das {
75 compatible = "nvidia,tegra20-das";
76 reg = <0x70000c00 0x80>;
77 };
78
79 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>;
82 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = <&apbdma 2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]84 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]85 };
86
87 tegra_i2s2: i2s@70002a00 {
88 compatible = "nvidia,tegra20-i2s";
89 reg = <0x70002a00 0x200>;
90 interrupts = <0 3 0x04>;
91 nvidia,dma-request-selector = <&apbdma 1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]92 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]93 };
94
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]95 serial@70006000 {
96 compatible = "nvidia,tegra20-uart";
97 reg = <0x70006000 0x40>;
98 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]99 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]100 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]101 };
102
103 serial@70006040 {
104 compatible = "nvidia,tegra20-uart";
105 reg = <0x70006040 0x40>;
106 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]107 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]108 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]109 };
110
111 serial@70006200 {
112 compatible = "nvidia,tegra20-uart";
113 reg = <0x70006200 0x100>;
114 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]115 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]116 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]117 };
118
119 serial@70006300 {
120 compatible = "nvidia,tegra20-uart";
121 reg = <0x70006300 0x100>;
122 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]123 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]124 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]125 };
126
127 serial@70006400 {
128 compatible = "nvidia,tegra20-uart";
129 reg = <0x70006400 0x100>;
130 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]131 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]132 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]133 };
134
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]135 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]136 compatible = "nvidia,tegra20-pwm";
137 reg = <0x7000a000 0x100>;
138 #pwm-cells = <2>;
139 };
140
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]141 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]142 compatible = "nvidia,tegra20-i2c";
143 reg = <0x7000c000 0x100>;
144 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]145 #address-cells = <1>;
146 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]147 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]148 };
149
150 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]151 compatible = "nvidia,tegra20-i2c";
152 reg = <0x7000c400 0x100>;
153 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]154 #address-cells = <1>;
155 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]156 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]157 };
158
159 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]160 compatible = "nvidia,tegra20-i2c";
161 reg = <0x7000c500 0x100>;
162 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]163 #address-cells = <1>;
164 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]165 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]166 };
167
168 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]169 compatible = "nvidia,tegra20-i2c-dvc";
170 reg = <0x7000d000 0x200>;
171 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]172 #address-cells = <1>;
173 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]174 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]175 };
176
177 pmc {
178 compatible = "nvidia,tegra20-pmc";
179 reg = <0x7000e400 0x400>;
180 };
181
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]182 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]183 compatible = "nvidia,tegra20-mc";
184 reg = <0x7000f000 0x024
185 0x7000f03c 0x3c4>;
186 interrupts = <0 77 0x04>;
187 };
188
189 gart {
190 compatible = "nvidia,tegra20-gart";
191 reg = <0x7000f024 0x00000018 /* controller registers */
192 0x58000000 0x02000000>; /* GART aperture */
193 };
194
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]195 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]196 compatible = "nvidia,tegra20-emc";
197 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]198 #address-cells = <1>;
199 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]200 };
201
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]202 usb@c5000000 {
203 compatible = "nvidia,tegra20-ehci", "usb-ehci";
204 reg = <0xc5000000 0x4000>;
205 interrupts = <0 20 0x04>;
206 phy_type = "utmi";
207 nvidia,has-legacy-mode;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]208 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]209 };
210
211 usb@c5004000 {
212 compatible = "nvidia,tegra20-ehci", "usb-ehci";
213 reg = <0xc5004000 0x4000>;
214 interrupts = <0 21 0x04>;
215 phy_type = "ulpi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]216 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]217 };
218
219 usb@c5008000 {
220 compatible = "nvidia,tegra20-ehci", "usb-ehci";
221 reg = <0xc5008000 0x4000>;
222 interrupts = <0 97 0x04>;
223 phy_type = "utmi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]224 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]225 };
226
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]227 sdhci@c8000000 {
228 compatible = "nvidia,tegra20-sdhci";
229 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]230 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]231 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]232 };
233
234 sdhci@c8000200 {
235 compatible = "nvidia,tegra20-sdhci";
236 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]237 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]238 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]239 };
240
241 sdhci@c8000400 {
242 compatible = "nvidia,tegra20-sdhci";
243 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]244 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]245 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]246 };
247
248 sdhci@c8000600 {
249 compatible = "nvidia,tegra20-sdhci";
250 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]251 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]252 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]253 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]254
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]255 pmu {
256 compatible = "arm,cortex-a9-pmu";
257 interrupts = <0 56 0x04
258 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]259 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]260};