| Shawn Guo | 69c31b7 | 2011-09-06 14:59:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | #include <linux/linkage.h> |
| 14 | #include <linux/init.h> |
| Shawn Guo | a1f1c7e | 2011-09-06 15:08:40 +0800 | [diff] [blame] | 15 | #include <asm/asm-offsets.h> |
| Shawn Guo | 69c31b7 | 2011-09-06 14:59:40 +0800 | [diff] [blame] | 16 | #include <asm/hardware/cache-l2x0.h> |
| 17 | |
| 18 | .section ".text.head", "ax" |
| 19 | __CPUINIT |
| 20 | |
| 21 | /* |
| 22 | * The secondary kernel init calls v7_flush_dcache_all before it enables |
| 23 | * the L1; however, the L1 comes out of reset in an undefined state, so |
| 24 | * the clean + invalidate performed by v7_flush_dcache_all causes a bunch |
| 25 | * of cache lines with uninitialized data and uninitialized tags to get |
| 26 | * written out to memory, which does really unpleasant things to the main |
| 27 | * processor. We fix this by performing an invalidate, rather than a |
| 28 | * clean + invalidate, before jumping into the kernel. |
| 29 | * |
| 30 | * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs |
| 31 | * to be called for both secondary cores startup and primary core resume |
| 32 | * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. |
| 33 | */ |
| 34 | ENTRY(v7_invalidate_l1) |
| 35 | mov r0, #0 |
| Shawn Guo | 5b2acf3 | 2011-12-30 16:16:07 +0800 | [diff] [blame^] | 36 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
| Shawn Guo | 69c31b7 | 2011-09-06 14:59:40 +0800 | [diff] [blame] | 37 | mcr p15, 2, r0, c0, c0, 0 |
| 38 | mrc p15, 1, r0, c0, c0, 0 |
| 39 | |
| 40 | ldr r1, =0x7fff |
| 41 | and r2, r1, r0, lsr #13 |
| 42 | |
| 43 | ldr r1, =0x3ff |
| 44 | |
| 45 | and r3, r1, r0, lsr #3 @ NumWays - 1 |
| 46 | add r2, r2, #1 @ NumSets |
| 47 | |
| 48 | and r0, r0, #0x7 |
| 49 | add r0, r0, #4 @ SetShift |
| 50 | |
| 51 | clz r1, r3 @ WayShift |
| 52 | add r4, r3, #1 @ NumWays |
| 53 | 1: sub r2, r2, #1 @ NumSets-- |
| 54 | mov r3, r4 @ Temp = NumWays |
| 55 | 2: subs r3, r3, #1 @ Temp-- |
| 56 | mov r5, r3, lsl r1 |
| 57 | mov r6, r2, lsl r0 |
| 58 | orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) |
| 59 | mcr p15, 0, r5, c7, c6, 2 |
| 60 | bgt 2b |
| 61 | cmp r2, #0 |
| 62 | bgt 1b |
| 63 | dsb |
| 64 | isb |
| 65 | mov pc, lr |
| 66 | ENDPROC(v7_invalidate_l1) |
| 67 | |
| 68 | #ifdef CONFIG_SMP |
| 69 | ENTRY(v7_secondary_startup) |
| 70 | bl v7_invalidate_l1 |
| 71 | b secondary_startup |
| 72 | ENDPROC(v7_secondary_startup) |
| 73 | #endif |
| Shawn Guo | a1f1c7e | 2011-09-06 15:08:40 +0800 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * The following code is located into the .data section. This is to |
| 77 | * allow phys_l2x0_saved_regs to be accessed with a relative load |
| 78 | * as we are running on physical address here. |
| 79 | */ |
| 80 | .data |
| 81 | .align |
| 82 | |
| 83 | .macro pl310_resume |
| 84 | ldr r2, phys_l2x0_saved_regs |
| 85 | ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 |
| 86 | ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value |
| 87 | str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl |
| 88 | mov r1, #0x1 |
| 89 | str r1, [r0, #L2X0_CTRL] @ re-enable L2 |
| 90 | .endm |
| 91 | |
| 92 | ENTRY(v7_cpu_resume) |
| 93 | bl v7_invalidate_l1 |
| 94 | pl310_resume |
| 95 | b cpu_resume |
| 96 | ENDPROC(v7_cpu_resume) |
| 97 | |
| 98 | .globl phys_l2x0_saved_regs |
| 99 | phys_l2x0_saved_regs: |
| 100 | .long 0 |