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review.evervolv.com / android_kernel_oneplus_msm8996 / 5bdfba29f18f0a36df8e28328315213ea47eb529 / . / arch / arm / mach-imx / clk-imx25.c
blob: f1d75e72e0023b3c48d71f1dcf977466fa252980 [file] [log] [blame]
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]1/*
2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/list.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/clkdev.h>
25#include <linux/err.h>
26
27#include <mach/hardware.h>
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]28#include <mach/mx25.h>
Shawn Guoe3372472012-09-13 21:01:00 +0800[diff] [blame]29
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]30#include "clk.h"
Shawn Guoe3372472012-09-13 21:01:00 +0800[diff] [blame]31#include "common.h"
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]32
33#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
34
35#define CCM_MPCTL 0x00
36#define CCM_UPCTL 0x04
37#define CCM_CCTL 0x08
38#define CCM_CGCR0 0x0C
39#define CCM_CGCR1 0x10
40#define CCM_CGCR2 0x14
41#define CCM_PCDR0 0x18
42#define CCM_PCDR1 0x1C
43#define CCM_PCDR2 0x20
44#define CCM_PCDR3 0x24
45#define CCM_RCSR 0x28
46#define CCM_CRDR 0x2C
47#define CCM_DCVR0 0x30
48#define CCM_DCVR1 0x34
49#define CCM_DCVR2 0x38
50#define CCM_DCVR3 0x3c
51#define CCM_LTR0 0x40
52#define CCM_LTR1 0x44
53#define CCM_LTR2 0x48
54#define CCM_LTR3 0x4c
55#define CCM_MCR 0x64
56
57#define ccm(x) (CRM_BASE + (x))
58
59static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
60static const char *per_sel_clks[] = { "ahb", "upll", };
61
62enum mx25_clks {
63 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
64 per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
65 per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
66 per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
67 per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
68 csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
69 lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
70 csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
71 usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
72 cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
73 kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
74 ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
75 uart4_ipg, uart5_ipg, wdt_ipg, clk_max
76};
77
78static struct clk *clk[clk_max];
79
80int __init mx25_clocks_init(void)
81{
82 int i;
83
84 clk[dummy] = imx_clk_fixed("dummy", 0);
85 clk[osc] = imx_clk_fixed("osc", 24000000);
86 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
87 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
88 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
89 clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
90 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
91 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
92 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6);
93 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
94 clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
95 clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
96 clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
97 clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
98 clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
99 clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
100 clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
101 clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
102 clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
103 clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
104 clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
105 clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
106 clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
107 clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
108 clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
109 clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
110 clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
111 clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
112 clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
113 clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
114 clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
115 clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
116 clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
117 clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
118 clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
119 clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
120 clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
121 clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
122 clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
123 clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
124 clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
125 clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
126 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
127 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3);
128 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
129 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
130 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
131 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0), 7);
132 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0), 8);
133 clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
134 clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
135 clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
136 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
137 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
138 clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
139 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
140 clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
141 clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
142 clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
143 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2);
144 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3);
145 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4);
146 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5);
147 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6);
148 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7);
149 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8);
150 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
151 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
152 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
153 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
154 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
155 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
156 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
157 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0);
158 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1);
159 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2);
160 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6);
161 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
162 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
163 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
164 clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
165 clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
166 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
167 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
168 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
169 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
170
171 for (i = 0; i < ARRAY_SIZE(clk); i++)
172 if (IS_ERR(clk[i]))
173 pr_err("i.MX25 clk %d: register failed with %ld\n",
174 i, PTR_ERR(clk[i]));
175
176 /* i.mx25 has the i.mx21 type uart */
177 clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
178 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
179 clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
180 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
181 clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
182 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
183 clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
184 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
185 clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
186 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
187 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
188 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
189 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
190 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
191 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
192 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
193 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
194 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
195 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
196 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
197 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
198 clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
199 clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
200 clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
201 clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
202 /* i.mx25 has the i.mx35 type cspi */
203 clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
204 clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
205 clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
206 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
207 clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
208 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
209 clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
210 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
211 clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
212 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
213 clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
214 clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
215 clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame^]216 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
217 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
218 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]219 clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
220 clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
221 clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
222 clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx-fb.0");
223 clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
224 clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
225 clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
Fabio Estevam912bfe72012-08-19 14:05:59 -0300[diff] [blame]226 clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
227 clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]228 clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
229 clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
230 clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
231 clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
232 clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
233 clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
234 clk_register_clkdev(clk[csi_ipg_per], "per", "mx2-camera.0");
235 clk_register_clkdev(clk[csi_ipg], "ipg", "mx2-camera.0");
236 clk_register_clkdev(clk[csi_ahb], "ahb", "mx2-camera.0");
237 clk_register_clkdev(clk[dummy], "audmux", NULL);
238 clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
239 clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
240 /* i.mx25 has the i.mx35 type sdma */
241 clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
242 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
243 clk_register_clkdev(clk[iim_ipg], "iim", NULL);
244
Sascha Hauer42a3f892012-09-18 10:05:31 +0200[diff] [blame]245 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
Sascha Hauer6bbaec52012-03-08 22:24:12 +0100[diff] [blame]246 return 0;
247}