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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04002 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
Alan Coxab771632008-10-27 15:09:10 +000017 * Copyright (C) 2003 Red Hat Inc
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040018 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
Alan Coxd96212e2005-12-08 19:19:50 +000040 * Documentation
Lucas De Marchi25985ed2011-03-30 22:57:33 -030041 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
Alan2c5ff672006-12-04 16:33:20 +000043 * driver the list of errata that are relevant is below, going back to
Alan Coxd96212e2005-12-08 19:19:50 +000044 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
Thomas Weber88393162010-03-16 11:47:56 +010046 * The chipsets all follow very much the same design. The original Triton
Lucas De Marchi25985ed2011-03-30 22:57:33 -030047 * series chipsets do _not_ support independent device timings, but this
Alan Coxd96212e2005-12-08 19:19:50 +000048 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
Lucas De Marchi25985ed2011-03-30 22:57:33 -030050 * driver supports only the chips with independent timing (that is those
Alan Coxd96212e2005-12-08 19:19:50 +000051 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
Alan Coxc611bed2009-05-06 17:08:44 +010075 * ICH7 errata #16 - MWDMA1 timings are incorrect
Alan Coxd96212e2005-12-08 19:19:50 +000076 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 */
85
86#include <linux/kernel.h>
87#include <linux/module.h>
88#include <linux/pci.h>
89#include <linux/init.h>
90#include <linux/blkdev.h>
91#include <linux/delay.h>
Jeff Garzik6248e642005-10-30 06:42:18 -050092#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090093#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070094#include <scsi/scsi_host.h>
95#include <linux/libata.h>
Tejun Heob8b275e2007-07-10 15:55:43 +090096#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
98#define DRV_NAME "ata_piix"
Alan Coxc611bed2009-05-06 17:08:44 +010099#define DRV_VERSION "2.13"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
Tejun Heoc7290722008-01-18 18:36:30 +0900105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
Tejun Heoff0fc142005-12-18 17:17:07 +0900110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
Tejun Heoc7290722008-01-18 18:36:30 +0900111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
Tejun Heo800b3992006-12-03 21:34:13 +0900113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
Tejun Heob3362f82006-11-10 18:08:10 +0900115
Ming Lei5e5a4f52011-10-07 11:50:22 +0800116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
Tejun Heod33f58b2006-03-01 01:25:39 +0900121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300127 NA = -2, /* not available */
Tejun Heod33f58b2006-03-01 01:25:39 +0900128 RV = -3, /* reserved */
129
Greg Felix7b6dbd62005-07-28 15:54:15 -0400130 PIIX_AHCI_DEVICE = 6,
Tejun Heob8b275e2007-07-10 15:55:43 +0900131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134};
135
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900136enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
Alan Coxc611bed2009-05-06 17:08:44 +0100143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900144 ich5_sata,
145 ich6_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900146 ich6m_sata,
147 ich8_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900148 ich8_2port_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800152 ich8_sata_snb,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900153};
154
Tejun Heod33f58b2006-03-01 01:25:39 +0900155struct piix_map_db {
156 const u32 mask;
Jeff Garzik73291a12006-07-11 13:11:17 -0400157 const u16 port_enable;
Tejun Heod33f58b2006-03-01 01:25:39 +0900158 const int map[][4];
159};
160
Tejun Heod96715c2006-06-29 01:58:28 +0900161struct piix_host_priv {
162 const int *map;
Tejun Heo2852bcf2009-01-02 12:04:48 +0900163 u32 saved_iocfg;
Tejun Heoc7290722008-01-18 18:36:30 +0900164 void __iomem *sidpr;
Tejun Heod96715c2006-06-29 01:58:28 +0900165};
166
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400167static int piix_init_one(struct pci_dev *pdev,
168 const struct pci_device_id *ent);
Tejun Heo2852bcf2009-01-02 12:04:48 +0900169static void piix_remove_one(struct pci_dev *pdev);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900170static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400171static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
172static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
173static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
Alan Coxeb4a2c72007-04-11 00:04:20 +0100174static int ich_pata_cable_detect(struct ata_port *ap);
Tejun Heo25f98132008-01-07 19:38:53 +0900175static u8 piix_vmw_bmdma_status(struct ata_port *ap);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900176static int piix_sidpr_scr_read(struct ata_link *link,
177 unsigned int reg, u32 *val);
178static int piix_sidpr_scr_write(struct ata_link *link,
179 unsigned int reg, u32 val);
Tejun Heoa97c40062010-09-01 17:50:08 +0200180static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
181 unsigned hints);
Tejun Heo27943622010-01-19 10:49:19 +0900182static bool piix_irq_check(struct ata_port *ap);
Ming Lei5e5a4f52011-10-07 11:50:22 +0800183static int piix_port_start(struct ata_port *ap);
Tejun Heob8b275e2007-07-10 15:55:43 +0900184#ifdef CONFIG_PM
185static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
186static int piix_pci_device_resume(struct pci_dev *pdev);
187#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
189static unsigned int in_module_init = 1;
190
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500191static const struct pci_device_id piix_pci_tbl[] = {
Aland2cdfc02007-01-10 17:13:38 +0000192 /* Intel PIIX3 for the 430HX etc */
193 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
Tejun Heo25f98132008-01-07 19:38:53 +0900194 /* VMware ICH4 */
195 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400196 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
197 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
198 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400199 /* Intel PIIX4 */
200 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
201 /* Intel PIIX4 */
202 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
203 /* Intel PIIX */
204 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
205 /* Intel ICH (i810, i815, i840) UDMA 66*/
206 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
207 /* Intel ICH0 : UDMA 33*/
208 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
209 /* Intel ICH2M */
210 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
212 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH3M */
214 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* Intel ICH3 (E7500/1) UDMA 100 */
216 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Ben Hutchings4bb969d2010-10-10 22:42:21 +0100217 /* Intel ICH4-L */
218 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400219 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
220 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
222 /* Intel ICH5 */
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700223 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400224 /* C-ICH (i810E2) */
225 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400226 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400227 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228 /* ICH6 (and 6) (i915) UDMA 100 */
229 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
230 /* ICH7/7-R (i945, i975) UDMA 100*/
Alan Coxc611bed2009-05-06 17:08:44 +0100231 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
232 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
Christian Lamparterc1e6f282007-07-03 10:19:20 -0400233 /* ICH8 Mobile PATA Controller */
234 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
Alan Cox7654db12009-05-06 17:10:17 +0100236 /* SATA ports */
Jeff Garzik4fca3772011-02-15 01:13:24 -0500237
Tejun Heo1d076e52006-03-01 01:25:39 +0900238 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900240 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900242 /* 6300ESB (ICH5 variant with broken PCS present bits) */
Tejun Heo5e56a372006-11-10 18:08:10 +0900243 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900244 /* 6300ESB pretending RAID */
Tejun Heo5e56a372006-11-10 18:08:10 +0900245 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900246 /* 82801FB/FW (ICH6/ICH6W) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900248 /* 82801FR/FRW (ICH6R/ICH6RW) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900249 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo5016d7d2008-03-26 15:46:58 +0900250 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
251 * Attach iff the controller is in IDE mode. */
252 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900253 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900254 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900255 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900256 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900257 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800258 /* Enterprise Southbridge 2 (631xESB/632xESB) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900259 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800260 /* SATA Controller 1 IDE (ICH8) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900261 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800262 /* SATA Controller 2 IDE (ICH8) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900263 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900264 /* Mobile SATA Controller IDE (ICH8M), Apple */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900265 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900266 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
Tejun Heo487eff62008-07-29 15:06:26 +0900267 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900268 /* Mobile SATA Controller IDE (ICH8M) */
269 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800270 /* SATA Controller IDE (ICH9) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900271 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800272 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900273 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800274 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900275 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800276 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900277 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800278 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900279 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800280 /* SATA Controller IDE (ICH9M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900281 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700282 /* SATA Controller IDE (Tolapai) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900283 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800284 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900285 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800286 /* SATA Controller IDE (ICH10) */
287 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900289 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800290 /* SATA Controller IDE (ICH10) */
291 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
294 /* SATA Controller IDE (PCH) */
Seth Heasley0395e612008-08-27 16:40:06 -0700295 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (PCH) */
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700297 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
298 /* SATA Controller IDE (PCH) */
Seth Heasley0395e612008-08-27 16:40:06 -0700299 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
300 /* SATA Controller IDE (PCH) */
Seth Heasleyc6c6a1a2008-08-11 17:03:18 -0700301 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (PCH) */
303 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Seth Heasley88e82012010-01-12 17:01:28 -0800304 /* SATA Controller IDE (CPT) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800305 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley88e82012010-01-12 17:01:28 -0800306 /* SATA Controller IDE (CPT) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800307 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley88e82012010-01-12 17:01:28 -0800308 /* SATA Controller IDE (CPT) */
309 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 /* SATA Controller IDE (CPT) */
311 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasley238e1492010-09-09 09:42:40 -0700312 /* SATA Controller IDE (PBG) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800313 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley238e1492010-09-09 09:42:40 -0700314 /* SATA Controller IDE (PBG) */
315 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Seth Heasley4a836c72011-04-20 08:43:37 -0700316 /* SATA Controller IDE (Panther Point) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800317 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley4a836c72011-04-20 08:43:37 -0700318 /* SATA Controller IDE (Panther Point) */
Ming Lei5e5a4f52011-10-07 11:50:22 +0800319 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
Seth Heasley4a836c72011-04-20 08:43:37 -0700320 /* SATA Controller IDE (Panther Point) */
321 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
322 /* SATA Controller IDE (Panther Point) */
323 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 { } /* terminate list */
325};
326
327static struct pci_driver piix_pci_driver = {
328 .name = DRV_NAME,
329 .id_table = piix_pci_tbl,
330 .probe = piix_init_one,
Tejun Heo2852bcf2009-01-02 12:04:48 +0900331 .remove = piix_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900332#ifdef CONFIG_PM
Tejun Heob8b275e2007-07-10 15:55:43 +0900333 .suspend = piix_pci_device_suspend,
334 .resume = piix_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900335#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336};
337
Jeff Garzik193515d2005-11-07 00:59:37 -0500338static struct scsi_host_template piix_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900339 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340};
341
Tejun Heo27943622010-01-19 10:49:19 +0900342static struct ata_port_operations piix_sata_ops = {
Alan Cox871af122009-01-05 14:16:39 +0000343 .inherits = &ata_bmdma32_port_ops,
Tejun Heo27943622010-01-19 10:49:19 +0900344 .sff_irq_check = piix_irq_check,
Ming Lei5e5a4f52011-10-07 11:50:22 +0800345 .port_start = piix_port_start,
Tejun Heo27943622010-01-19 10:49:19 +0900346};
347
348static struct ata_port_operations piix_pata_ops = {
349 .inherits = &piix_sata_ops,
Alan Coxeb4a2c72007-04-11 00:04:20 +0100350 .cable_detect = ata_cable_40wire,
Tejun Heo25f98132008-01-07 19:38:53 +0900351 .set_piomode = piix_set_piomode,
352 .set_dmamode = piix_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900353 .prereset = piix_pata_prereset,
Tejun Heo029cfd62008-03-25 12:22:49 +0900354};
Tejun Heo25f98132008-01-07 19:38:53 +0900355
Tejun Heo029cfd62008-03-25 12:22:49 +0900356static struct ata_port_operations piix_vmw_ops = {
357 .inherits = &piix_pata_ops,
Tejun Heo25f98132008-01-07 19:38:53 +0900358 .bmdma_status = piix_vmw_bmdma_status,
Tejun Heo25f98132008-01-07 19:38:53 +0900359};
360
Tejun Heo029cfd62008-03-25 12:22:49 +0900361static struct ata_port_operations ich_pata_ops = {
362 .inherits = &piix_pata_ops,
363 .cable_detect = ich_pata_cable_detect,
364 .set_dmamode = ich_set_dmamode,
365};
Tejun Heoc7290722008-01-18 18:36:30 +0900366
Tejun Heoa97c40062010-09-01 17:50:08 +0200367static struct device_attribute *piix_sidpr_shost_attrs[] = {
368 &dev_attr_link_power_management_policy,
369 NULL
370};
371
372static struct scsi_host_template piix_sidpr_sht = {
373 ATA_BMDMA_SHT(DRV_NAME),
374 .shost_attrs = piix_sidpr_shost_attrs,
375};
376
Tejun Heo029cfd62008-03-25 12:22:49 +0900377static struct ata_port_operations piix_sidpr_sata_ops = {
378 .inherits = &piix_sata_ops,
Tejun Heo57c9efd2008-04-07 22:47:19 +0900379 .hardreset = sata_std_hardreset,
Tejun Heoc7290722008-01-18 18:36:30 +0900380 .scr_read = piix_sidpr_scr_read,
381 .scr_write = piix_sidpr_scr_write,
Tejun Heoa97c40062010-09-01 17:50:08 +0200382 .set_lpm = piix_sidpr_set_lpm,
Tejun Heoc7290722008-01-18 18:36:30 +0900383};
384
Tejun Heod96715c2006-06-29 01:58:28 +0900385static const struct piix_map_db ich5_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900386 .mask = 0x7,
Jeff Garzikea35d292006-07-11 11:48:50 -0400387 .port_enable = 0x3,
Tejun Heod33f58b2006-03-01 01:25:39 +0900388 .map = {
389 /* PM PS SM SS MAP */
390 { P0, NA, P1, NA }, /* 000b */
391 { P1, NA, P0, NA }, /* 001b */
392 { RV, RV, RV, RV },
393 { RV, RV, RV, RV },
394 { P0, P1, IDE, IDE }, /* 100b */
395 { P1, P0, IDE, IDE }, /* 101b */
396 { IDE, IDE, P0, P1 }, /* 110b */
397 { IDE, IDE, P1, P0 }, /* 111b */
398 },
399};
400
Tejun Heod96715c2006-06-29 01:58:28 +0900401static const struct piix_map_db ich6_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900402 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400403 .port_enable = 0xf,
Tejun Heod33f58b2006-03-01 01:25:39 +0900404 .map = {
405 /* PM PS SM SS MAP */
Tejun Heo79ea24e2006-03-31 20:01:50 +0900406 { P0, P2, P1, P3 }, /* 00b */
Tejun Heod33f58b2006-03-01 01:25:39 +0900407 { IDE, IDE, P1, P3 }, /* 01b */
408 { P0, P2, IDE, IDE }, /* 10b */
409 { RV, RV, RV, RV },
410 },
411};
412
Tejun Heod96715c2006-06-29 01:58:28 +0900413static const struct piix_map_db ich6m_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900414 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400415 .port_enable = 0x5,
Tejun Heo67083742006-09-11 06:29:03 +0900416
417 /* Map 01b isn't specified in the doc but some notebooks use
Tejun Heoc6446a42006-10-09 13:23:58 +0900418 * it anyway. MAP 01b have been spotted on both ICH6M and
419 * ICH7M.
Tejun Heo67083742006-09-11 06:29:03 +0900420 */
421 .map = {
422 /* PM PS SM SS MAP */
Tejun Heoe04b3b92007-07-10 17:58:21 +0900423 { P0, P2, NA, NA }, /* 00b */
Tejun Heo67083742006-09-11 06:29:03 +0900424 { IDE, IDE, P1, P3 }, /* 01b */
425 { P0, P2, IDE, IDE }, /* 10b */
426 { RV, RV, RV, RV },
427 },
428};
429
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400430static const struct piix_map_db ich8_map_db = {
431 .mask = 0x3,
Tejun Heoa0ce9ac2007-11-19 12:06:37 +0900432 .port_enable = 0xf,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400433 .map = {
434 /* PM PS SM SS MAP */
Kristen Carlson Accardi158f30c82006-10-19 13:27:39 -0700435 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400436 { RV, RV, RV, RV },
Tejun Heoac2b0432007-08-07 02:43:27 +0900437 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400438 { RV, RV, RV, RV },
439 },
440};
441
Tejun Heo00242ec2007-11-19 11:24:25 +0900442static const struct piix_map_db ich8_2port_map_db = {
Jason Gastone2d352a2007-09-07 17:21:03 -0700443 .mask = 0x3,
444 .port_enable = 0x3,
445 .map = {
446 /* PM PS SM SS MAP */
447 { P0, NA, P1, NA }, /* 00b */
448 { RV, RV, RV, RV }, /* 01b */
449 { RV, RV, RV, RV }, /* 10b */
450 { RV, RV, RV, RV },
451 },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700452};
453
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900454static const struct piix_map_db ich8m_apple_map_db = {
455 .mask = 0x3,
456 .port_enable = 0x1,
457 .map = {
458 /* PM PS SM SS MAP */
459 { P0, NA, NA, NA }, /* 00b */
460 { RV, RV, RV, RV },
461 { P0, P2, IDE, IDE }, /* 10b */
462 { RV, RV, RV, RV },
463 },
464};
465
Tejun Heo00242ec2007-11-19 11:24:25 +0900466static const struct piix_map_db tolapai_map_db = {
Jason Gaston8f73a682007-10-11 16:05:15 -0700467 .mask = 0x3,
468 .port_enable = 0x3,
469 .map = {
470 /* PM PS SM SS MAP */
471 { P0, NA, P1, NA }, /* 00b */
472 { RV, RV, RV, RV }, /* 01b */
473 { RV, RV, RV, RV }, /* 10b */
474 { RV, RV, RV, RV },
475 },
476};
477
Tejun Heod96715c2006-06-29 01:58:28 +0900478static const struct piix_map_db *piix_map_db_table[] = {
479 [ich5_sata] = &ich5_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900480 [ich6_sata] = &ich6_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900481 [ich6m_sata] = &ich6m_map_db,
482 [ich8_sata] = &ich8_map_db,
Tejun Heo00242ec2007-11-19 11:24:25 +0900483 [ich8_2port_sata] = &ich8_2port_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900484 [ich8m_apple_sata] = &ich8m_apple_map_db,
485 [tolapai_sata] = &tolapai_map_db,
Ming Lei5e5a4f52011-10-07 11:50:22 +0800486 [ich8_sata_snb] = &ich8_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900487};
488
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489static struct ata_port_info piix_port_info[] = {
Tejun Heo00242ec2007-11-19 11:24:25 +0900490 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
491 {
Tejun Heo00242ec2007-11-19 11:24:25 +0900492 .flags = PIIX_PATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100493 .pio_mask = ATA_PIO4,
494 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
Tejun Heo00242ec2007-11-19 11:24:25 +0900495 .port_ops = &piix_pata_ops,
496 },
497
Jeff Garzikec300d92007-09-01 07:17:36 -0400498 [piix_pata_33] = /* PIIX4 at 33MHz */
Tejun Heo1d076e52006-03-01 01:25:39 +0900499 {
Tejun Heob3362f82006-11-10 18:08:10 +0900500 .flags = PIIX_PATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100501 .pio_mask = ATA_PIO4,
502 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
503 .udma_mask = ATA_UDMA2,
Tejun Heo1d076e52006-03-01 01:25:39 +0900504 .port_ops = &piix_pata_ops,
505 },
506
Jeff Garzikec300d92007-09-01 07:17:36 -0400507 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 {
Tejun Heob3362f82006-11-10 18:08:10 +0900509 .flags = PIIX_PATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100510 .pio_mask = ATA_PIO4,
511 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
512 .udma_mask = ATA_UDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400513 .port_ops = &ich_pata_ops,
514 },
Jeff Garzikec300d92007-09-01 07:17:36 -0400515
516 [ich_pata_66] = /* ICH controllers up to 66MHz */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400517 {
Tejun Heob3362f82006-11-10 18:08:10 +0900518 .flags = PIIX_PATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100519 .pio_mask = ATA_PIO4,
520 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400521 .udma_mask = ATA_UDMA4,
522 .port_ops = &ich_pata_ops,
523 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400524
Jeff Garzikec300d92007-09-01 07:17:36 -0400525 [ich_pata_100] =
Jeff Garzik669a5db2006-08-29 18:12:40 -0400526 {
Tejun Heob3362f82006-11-10 18:08:10 +0900527 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100528 .pio_mask = ATA_PIO4,
529 .mwdma_mask = ATA_MWDMA12_ONLY,
530 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400531 .port_ops = &ich_pata_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532 },
533
Alan Coxc611bed2009-05-06 17:08:44 +0100534 [ich_pata_100_nomwdma1] =
535 {
536 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
537 .pio_mask = ATA_PIO4,
538 .mwdma_mask = ATA_MWDMA2_ONLY,
539 .udma_mask = ATA_UDMA5,
540 .port_ops = &ich_pata_ops,
541 },
542
Jeff Garzikec300d92007-09-01 07:17:36 -0400543 [ich5_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 {
Tejun Heo228c1592006-11-10 18:08:10 +0900545 .flags = PIIX_SATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100546 .pio_mask = ATA_PIO4,
547 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400548 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 .port_ops = &piix_sata_ops,
550 },
551
Jeff Garzikec300d92007-09-01 07:17:36 -0400552 [ich6_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 {
Tejun Heo723159c2008-01-04 18:42:20 +0900554 .flags = PIIX_SATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100555 .pio_mask = ATA_PIO4,
556 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400557 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 .port_ops = &piix_sata_ops,
559 },
560
Tejun Heo9c0bf672008-03-26 16:00:58 +0900561 [ich6m_sata] =
Jason Gastonc368ca42005-04-16 15:24:44 -0700562 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900563 .flags = PIIX_SATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100564 .pio_mask = ATA_PIO4,
565 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400566 .udma_mask = ATA_UDMA6,
Jason Gastonc368ca42005-04-16 15:24:44 -0700567 .port_ops = &piix_sata_ops,
568 },
Tejun Heo1d076e52006-03-01 01:25:39 +0900569
Tejun Heo9c0bf672008-03-26 16:00:58 +0900570 [ich8_sata] =
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400571 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900572 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100573 .pio_mask = ATA_PIO4,
574 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400575 .udma_mask = ATA_UDMA6,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400576 .port_ops = &piix_sata_ops,
577 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400578
Tejun Heo00242ec2007-11-19 11:24:25 +0900579 [ich8_2port_sata] =
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700580 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900581 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100582 .pio_mask = ATA_PIO4,
583 .mwdma_mask = ATA_MWDMA2,
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700584 .udma_mask = ATA_UDMA6,
585 .port_ops = &piix_sata_ops,
586 },
Jason Gaston8f73a682007-10-11 16:05:15 -0700587
Tejun Heo9c0bf672008-03-26 16:00:58 +0900588 [tolapai_sata] =
Jason Gaston8f73a682007-10-11 16:05:15 -0700589 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900590 .flags = PIIX_SATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100591 .pio_mask = ATA_PIO4,
592 .mwdma_mask = ATA_MWDMA2,
Jason Gaston8f73a682007-10-11 16:05:15 -0700593 .udma_mask = ATA_UDMA6,
594 .port_ops = &piix_sata_ops,
595 },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900596
Tejun Heo9c0bf672008-03-26 16:00:58 +0900597 [ich8m_apple_sata] =
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900598 {
Tejun Heo23cf2962008-05-29 22:04:22 +0900599 .flags = PIIX_SATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100600 .pio_mask = ATA_PIO4,
601 .mwdma_mask = ATA_MWDMA2,
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900602 .udma_mask = ATA_UDMA6,
603 .port_ops = &piix_sata_ops,
604 },
605
Tejun Heo25f98132008-01-07 19:38:53 +0900606 [piix_pata_vmw] =
607 {
Tejun Heo25f98132008-01-07 19:38:53 +0900608 .flags = PIIX_PATA_FLAGS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100609 .pio_mask = ATA_PIO4,
610 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
611 .udma_mask = ATA_UDMA2,
Tejun Heo25f98132008-01-07 19:38:53 +0900612 .port_ops = &piix_vmw_ops,
613 },
614
Ming Lei5e5a4f52011-10-07 11:50:22 +0800615 /*
616 * some Sandybridge chipsets have broken 32 mode up to now,
617 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
618 */
619 [ich8_sata_snb] =
620 {
621 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
622 .pio_mask = ATA_PIO4,
623 .mwdma_mask = ATA_MWDMA2,
624 .udma_mask = ATA_UDMA6,
625 .port_ops = &piix_sata_ops,
626 },
627
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628};
629
630static struct pci_bits piix_enable_bits[] = {
631 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
632 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
633};
634
635MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
636MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
637MODULE_LICENSE("GPL");
638MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
639MODULE_VERSION(DRV_VERSION);
640
Alan Coxfc085152006-10-10 14:28:11 -0700641struct ich_laptop {
642 u16 device;
643 u16 subvendor;
644 u16 subdevice;
645};
646
647/*
648 * List of laptops that use short cables rather than 80 wire
649 */
650
651static const struct ich_laptop ich_laptop[] = {
652 /* devid, subvendor, subdev */
653 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
Alan Cox2655e2c2007-11-05 22:51:09 +0000654 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
J Jbabfb682007-01-09 02:26:30 +0900655 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
Steve Conklin60347342009-07-16 16:27:56 -0500656 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
Robin H\. Johnson12340102007-03-28 18:02:07 -0700657 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
Jeff Garzik54174db2007-09-29 04:01:43 -0400658 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200659 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
Herton Ronaldo Krzesinskid09addf2008-09-17 14:29:05 -0300660 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
Steve Conklin60347342009-07-16 16:27:56 -0500661 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
Tejun Heob33620f2007-05-22 11:34:22 +0200662 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
Colin Ian Kinge1fefea2008-06-03 18:59:02 +0200663 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
664 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
Dan McGee01ce2602008-04-20 22:03:27 -0500665 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
Alan Cox124a6ee2009-05-06 17:09:41 +0100666 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
Alan Coxfc085152006-10-10 14:28:11 -0700667 /* end marker */
668 { 0, }
669};
670
Ming Lei5e5a4f52011-10-07 11:50:22 +0800671static int piix_port_start(struct ata_port *ap)
672{
673 if (!(ap->flags & PIIX_FLAG_PIO16))
674 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
675
676 return ata_bmdma_port_start(ap);
677}
678
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679/**
Alan Coxeb4a2c72007-04-11 00:04:20 +0100680 * ich_pata_cable_detect - Probe host controller cable detect info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 * @ap: Port for which cable detect info is desired
682 *
683 * Read 80c cable indicator from ATA PCI device's PCI config
684 * register. This register is normally set by firmware (BIOS).
685 *
686 * LOCKING:
687 * None (inherited from caller).
688 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400689
Alan Coxeb4a2c72007-04-11 00:04:20 +0100690static int ich_pata_cable_detect(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691{
Jeff Garzikcca39742006-08-24 03:19:22 -0400692 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo2852bcf2009-01-02 12:04:48 +0900693 struct piix_host_priv *hpriv = ap->host->private_data;
Alan Coxfc085152006-10-10 14:28:11 -0700694 const struct ich_laptop *lap = &ich_laptop[0];
Tejun Heo2852bcf2009-01-02 12:04:48 +0900695 u8 mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696
Alan Coxfc085152006-10-10 14:28:11 -0700697 /* Check for specials - Acer Aspire 5602WLMi */
698 while (lap->device) {
699 if (lap->device == pdev->device &&
700 lap->subvendor == pdev->subsystem_vendor &&
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400701 lap->subdevice == pdev->subsystem_device)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100702 return ATA_CBL_PATA40_SHORT;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400703
Alan Coxfc085152006-10-10 14:28:11 -0700704 lap++;
705 }
706
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 /* check BIOS cable detect results */
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900708 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
Tejun Heo2852bcf2009-01-02 12:04:48 +0900709 if ((hpriv->saved_iocfg & mask) == 0)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100710 return ATA_CBL_PATA40;
711 return ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712}
713
714/**
Tejun Heoccc46722006-05-31 18:28:14 +0900715 * piix_pata_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900716 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900717 * @deadline: deadline jiffies for the operation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 * LOCKING:
720 * None (inherited from caller).
721 */
Tejun Heocc0680a2007-08-06 18:36:23 +0900722static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723{
Tejun Heocc0680a2007-08-06 18:36:23 +0900724 struct ata_port *ap = link->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400725 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726
Alan Coxc9619222006-09-26 17:53:38 +0100727 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
728 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +0900729 return ata_sff_prereset(link, deadline);
Tejun Heoccc46722006-05-31 18:28:14 +0900730}
731
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200732static DEFINE_SPINLOCK(piix_lock);
733
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734/**
735 * piix_set_piomode - Initialize host controller PATA PIO timings
736 * @ap: Port whose timings we are configuring
737 * @adev: um
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 *
739 * Set PIO mode for device, in host controller PCI config space.
740 *
741 * LOCKING:
742 * None (inherited from caller).
743 */
744
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400745static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746{
Jeff Garzikcca39742006-08-24 03:19:22 -0400747 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200748 unsigned long flags;
749 unsigned int pio = adev->pio_mode - XFER_PIO_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 unsigned int is_slave = (adev->devno != 0);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900751 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 unsigned int slave_port = 0x44;
753 u16 master_data;
754 u8 slave_data;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400755 u8 udma_enable;
756 int control = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400757
Jeff Garzik669a5db2006-08-29 18:12:40 -0400758 /*
759 * See Intel Document 298600-004 for the timing programing rules
760 * for ICH controllers.
761 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762
763 static const /* ISP RTC */
764 u8 timings[][2] = { { 0, 0 },
765 { 0, 0 },
766 { 1, 0 },
767 { 2, 1 },
768 { 2, 3 }, };
769
Jeff Garzik669a5db2006-08-29 18:12:40 -0400770 if (pio >= 2)
771 control |= 1; /* TIME1 enable */
772 if (ata_pio_need_iordy(adev))
773 control |= 2; /* IE enable */
774
Jeff Garzik85cd7252006-08-31 00:03:49 -0400775 /* Intel specifies that the PPE functionality is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400776 if (adev->class == ATA_DEV_ATA)
777 control |= 4; /* PPE enable */
778
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200779 spin_lock_irqsave(&piix_lock, flags);
780
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200781 /* PIO configuration clears DTE unconditionally. It will be
782 * programmed in set_dmamode which is guaranteed to be called
783 * after set_piomode if any DMA mode is available.
784 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 pci_read_config_word(dev, master_port, &master_data);
786 if (is_slave) {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200787 /* clear TIME1|IE1|PPE1|DTE1 */
788 master_data &= 0xff0f;
Joe Perches1967b7f2008-02-03 17:08:11 +0200789 /* Enable SITRE (separate slave timing register) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 master_data |= 0x4000;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400791 /* enable PPE1, IE1 and TIME1 as needed */
792 master_data |= (control << 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 pci_read_config_byte(dev, slave_port, &slave_data);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900794 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400795 /* Load the timing nibble for this slave */
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200796 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
797 << (ap->port_no ? 4 : 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 } else {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200799 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
800 master_data &= 0xccf0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400801 /* Enable PPE, IE and TIME as appropriate */
802 master_data |= control;
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200803 /* load ISP and RCT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 master_data |=
805 (timings[pio][0] << 12) |
806 (timings[pio][1] << 8);
807 }
808 pci_write_config_word(dev, master_port, master_data);
809 if (is_slave)
810 pci_write_config_byte(dev, slave_port, slave_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400811
812 /* Ensure the UDMA bit is off - it will be turned back on if
813 UDMA is selected */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400814
Jeff Garzik669a5db2006-08-29 18:12:40 -0400815 if (ap->udma_mask) {
816 pci_read_config_byte(dev, 0x48, &udma_enable);
817 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
818 pci_write_config_byte(dev, 0x48, udma_enable);
819 }
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200820
821 spin_unlock_irqrestore(&piix_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822}
823
824/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400825 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 * @ap: Port whose timings we are configuring
Jeff Garzik669a5db2006-08-29 18:12:40 -0400827 * @adev: Drive in question
Hennec32a8fd2006-09-25 22:00:46 +0200828 * @isich: set if the chip is an ICH device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 *
830 * Set UDMA mode for device, in host controller PCI config space.
831 *
832 * LOCKING:
833 * None (inherited from caller).
834 */
835
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400836static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837{
Jeff Garzikcca39742006-08-24 03:19:22 -0400838 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200839 unsigned long flags;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400840 u8 master_port = ap->port_no ? 0x42 : 0x40;
841 u16 master_data;
842 u8 speed = adev->dma_mode;
843 int devid = adev->devno + 2 * ap->port_no;
Andrew Mortondedf61d2007-01-10 17:20:34 -0800844 u8 udma_enable = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400845
Jeff Garzik669a5db2006-08-29 18:12:40 -0400846 static const /* ISP RTC */
847 u8 timings[][2] = { { 0, 0 },
848 { 0, 0 },
849 { 1, 0 },
850 { 2, 1 },
851 { 2, 3 }, };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200853 spin_lock_irqsave(&piix_lock, flags);
854
Jeff Garzik669a5db2006-08-29 18:12:40 -0400855 pci_read_config_word(dev, master_port, &master_data);
Aland2cdfc02007-01-10 17:13:38 +0000856 if (ap->udma_mask)
857 pci_read_config_byte(dev, 0x48, &udma_enable);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858
859 if (speed >= XFER_UDMA_0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400860 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
861 u16 udma_timing;
862 u16 ideconf;
863 int u_clock, u_speed;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400864
Jeff Garzik669a5db2006-08-29 18:12:40 -0400865 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400866 * UDMA is handled by a combination of clock switching and
Jeff Garzik85cd7252006-08-31 00:03:49 -0400867 * selection of dividers
868 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400869 * Handy rule: Odd modes are UDMATIMx 01, even are 02
Jeff Garzik85cd7252006-08-31 00:03:49 -0400870 * except UDMA0 which is 00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400871 */
872 u_speed = min(2 - (udma & 1), udma);
873 if (udma == 5)
874 u_clock = 0x1000; /* 100Mhz */
875 else if (udma > 2)
876 u_clock = 1; /* 66Mhz */
877 else
878 u_clock = 0; /* 33Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400879
Jeff Garzik669a5db2006-08-29 18:12:40 -0400880 udma_enable |= (1 << devid);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400881
Jeff Garzik669a5db2006-08-29 18:12:40 -0400882 /* Load the CT/RP selection */
883 pci_read_config_word(dev, 0x4A, &udma_timing);
884 udma_timing &= ~(3 << (4 * devid));
885 udma_timing |= u_speed << (4 * devid);
886 pci_write_config_word(dev, 0x4A, udma_timing);
887
Jeff Garzik85cd7252006-08-31 00:03:49 -0400888 if (isich) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400889 /* Select a 33/66/100Mhz clock */
890 pci_read_config_word(dev, 0x54, &ideconf);
891 ideconf &= ~(0x1001 << devid);
892 ideconf |= u_clock << devid;
893 /* For ICH or later we should set bit 10 for better
894 performance (WR_PingPong_En) */
895 pci_write_config_word(dev, 0x54, ideconf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897 } else {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400898 /*
899 * MWDMA is driven by the PIO timings. We must also enable
900 * IORDY unconditionally along with TIME1. PPE has already
901 * been set when the PIO timing was set.
902 */
903 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
904 unsigned int control;
905 u8 slave_data;
906 const unsigned int needed_pio[3] = {
907 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
908 };
909 int pio = needed_pio[mwdma] - XFER_PIO_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400910
Jeff Garzik669a5db2006-08-29 18:12:40 -0400911 control = 3; /* IORDY|TIME1 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400912
Jeff Garzik669a5db2006-08-29 18:12:40 -0400913 /* If the drive MWDMA is faster than it can do PIO then
914 we must force PIO into PIO0 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400915
Jeff Garzik669a5db2006-08-29 18:12:40 -0400916 if (adev->pio_mode < needed_pio[mwdma])
917 /* Enable DMA timing only */
918 control |= 8; /* PIO cycles in PIO0 */
919
920 if (adev->devno) { /* Slave */
921 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
922 master_data |= control << 4;
923 pci_read_config_byte(dev, 0x44, &slave_data);
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200924 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400925 /* Load the matching timing */
926 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
927 pci_write_config_byte(dev, 0x44, slave_data);
928 } else { /* Master */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400929 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
Jeff Garzik669a5db2006-08-29 18:12:40 -0400930 and master timing bits */
931 master_data |= control;
932 master_data |=
933 (timings[pio][0] << 12) |
934 (timings[pio][1] << 8);
935 }
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200936
Bartlomiej Zolnierkiewicz69385942009-12-03 20:32:08 +0100937 if (ap->udma_mask)
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200938 udma_enable &= ~(1 << devid);
Bartlomiej Zolnierkiewicz69385942009-12-03 20:32:08 +0100939
940 pci_write_config_word(dev, master_port, master_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400942 /* Don't scribble on 0x48 if the controller does not support UDMA */
943 if (ap->udma_mask)
944 pci_write_config_byte(dev, 0x48, udma_enable);
Bartlomiej Zolnierkiewicz60c3be32009-08-30 14:56:30 +0200945
946 spin_unlock_irqrestore(&piix_lock, flags);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400947}
948
949/**
950 * piix_set_dmamode - Initialize host controller PATA DMA timings
951 * @ap: Port whose timings we are configuring
952 * @adev: um
953 *
954 * Set MW/UDMA mode for device, in host controller PCI config space.
955 *
956 * LOCKING:
957 * None (inherited from caller).
958 */
959
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400960static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400961{
962 do_pata_set_dmamode(ap, adev, 0);
963}
964
965/**
966 * ich_set_dmamode - Initialize host controller PATA DMA timings
967 * @ap: Port whose timings we are configuring
968 * @adev: um
969 *
970 * Set MW/UDMA mode for device, in host controller PCI config space.
971 *
972 * LOCKING:
973 * None (inherited from caller).
974 */
975
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400976static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400977{
978 do_pata_set_dmamode(ap, adev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979}
980
Tejun Heoc7290722008-01-18 18:36:30 +0900981/*
982 * Serial ATA Index/Data Pair Superset Registers access
983 *
984 * Beginning from ICH8, there's a sane way to access SCRs using index
Tejun Heobe77e432008-07-31 17:02:44 +0900985 * and data register pair located at BAR5 which means that we have
986 * separate SCRs for master and slave. This is handled using libata
987 * slave_link facility.
Tejun Heoc7290722008-01-18 18:36:30 +0900988 */
989static const int piix_sidx_map[] = {
990 [SCR_STATUS] = 0,
991 [SCR_ERROR] = 2,
992 [SCR_CONTROL] = 1,
993};
994
Tejun Heobe77e432008-07-31 17:02:44 +0900995static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
Tejun Heoc7290722008-01-18 18:36:30 +0900996{
Tejun Heobe77e432008-07-31 17:02:44 +0900997 struct ata_port *ap = link->ap;
Tejun Heoc7290722008-01-18 18:36:30 +0900998 struct piix_host_priv *hpriv = ap->host->private_data;
999
Tejun Heobe77e432008-07-31 17:02:44 +09001000 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
Tejun Heoc7290722008-01-18 18:36:30 +09001001 hpriv->sidpr + PIIX_SIDPR_IDX);
1002}
1003
Tejun Heo82ef04f2008-07-31 17:02:40 +09001004static int piix_sidpr_scr_read(struct ata_link *link,
1005 unsigned int reg, u32 *val)
Tejun Heoc7290722008-01-18 18:36:30 +09001006{
Tejun Heobe77e432008-07-31 17:02:44 +09001007 struct piix_host_priv *hpriv = link->ap->host->private_data;
Tejun Heoc7290722008-01-18 18:36:30 +09001008
1009 if (reg >= ARRAY_SIZE(piix_sidx_map))
1010 return -EINVAL;
1011
Tejun Heobe77e432008-07-31 17:02:44 +09001012 piix_sidpr_sel(link, reg);
1013 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
Tejun Heoc7290722008-01-18 18:36:30 +09001014 return 0;
1015}
1016
Tejun Heo82ef04f2008-07-31 17:02:40 +09001017static int piix_sidpr_scr_write(struct ata_link *link,
1018 unsigned int reg, u32 val)
Tejun Heoc7290722008-01-18 18:36:30 +09001019{
Tejun Heobe77e432008-07-31 17:02:44 +09001020 struct piix_host_priv *hpriv = link->ap->host->private_data;
Tejun Heo82ef04f2008-07-31 17:02:40 +09001021
Tejun Heoc7290722008-01-18 18:36:30 +09001022 if (reg >= ARRAY_SIZE(piix_sidx_map))
1023 return -EINVAL;
1024
Tejun Heobe77e432008-07-31 17:02:44 +09001025 piix_sidpr_sel(link, reg);
1026 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
Tejun Heoc7290722008-01-18 18:36:30 +09001027 return 0;
1028}
1029
Tejun Heoa97c40062010-09-01 17:50:08 +02001030static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1031 unsigned hints)
1032{
1033 return sata_link_scr_lpm(link, policy, false);
1034}
1035
Tejun Heo27943622010-01-19 10:49:19 +09001036static bool piix_irq_check(struct ata_port *ap)
1037{
1038 if (unlikely(!ap->ioaddr.bmdma_addr))
1039 return false;
1040
1041 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1042}
1043
Tejun Heob8b275e2007-07-10 15:55:43 +09001044#ifdef CONFIG_PM
Tejun Heo8c3832e2007-07-27 14:53:28 +09001045static int piix_broken_suspend(void)
1046{
Jeff Garzik18552562007-10-03 15:15:40 -04001047 static const struct dmi_system_id sysids[] = {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001048 {
Tejun Heo4c74d4e2007-09-30 01:11:20 -07001049 .ident = "TECRA M3",
1050 .matches = {
1051 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1052 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1053 },
1054 },
1055 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001056 .ident = "TECRA M3",
1057 .matches = {
1058 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1059 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1060 },
1061 },
1062 {
Peter Schwenked1aa6902007-12-05 10:39:49 +09001063 .ident = "TECRA M4",
1064 .matches = {
1065 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1066 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1067 },
1068 },
1069 {
Tejun Heo040dee52008-06-13 18:05:02 +09001070 .ident = "TECRA M4",
1071 .matches = {
1072 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1073 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1074 },
1075 },
1076 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001077 .ident = "TECRA M5",
1078 .matches = {
1079 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1080 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1081 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001082 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001083 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001084 .ident = "TECRA M6",
1085 .matches = {
1086 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1087 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1088 },
1089 },
1090 {
Tejun Heo5c08ea02007-08-14 19:56:04 +09001091 .ident = "TECRA M7",
1092 .matches = {
1093 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1094 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1095 },
1096 },
1097 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001098 .ident = "TECRA A8",
1099 .matches = {
1100 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1101 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1102 },
1103 },
1104 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001105 .ident = "Satellite R20",
1106 .matches = {
1107 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1108 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1109 },
1110 },
1111 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001112 .ident = "Satellite R25",
1113 .matches = {
1114 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1115 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1116 },
1117 },
1118 {
Tejun Heo3cc0b9d2007-08-25 08:31:02 +09001119 .ident = "Satellite U200",
1120 .matches = {
1121 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1122 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1123 },
1124 },
1125 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001126 .ident = "Satellite U200",
1127 .matches = {
1128 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1129 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1130 },
1131 },
1132 {
Yann Chachkoff62320e22007-11-07 12:02:27 +09001133 .ident = "Satellite Pro U200",
1134 .matches = {
1135 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1136 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1137 },
1138 },
1139 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001140 .ident = "Satellite U205",
1141 .matches = {
1142 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1143 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1144 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001145 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001146 {
Tejun Heode753e52007-11-12 17:56:24 +09001147 .ident = "SATELLITE U205",
1148 .matches = {
1149 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1150 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1151 },
1152 },
1153 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001154 .ident = "Portege M500",
1155 .matches = {
1156 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1157 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1158 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001159 },
Tejun Heoc3f93b82009-03-31 10:44:34 +09001160 {
1161 .ident = "VGN-BX297XP",
1162 .matches = {
1163 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1164 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1165 },
1166 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001167
1168 { } /* terminate list */
Tejun Heo8c3832e2007-07-27 14:53:28 +09001169 };
Tejun Heo7abe79c2007-07-27 14:55:07 +09001170 static const char *oemstrs[] = {
1171 "Tecra M3,",
1172 };
1173 int i;
Tejun Heo8c3832e2007-07-27 14:53:28 +09001174
1175 if (dmi_check_system(sysids))
1176 return 1;
1177
Tejun Heo7abe79c2007-07-27 14:55:07 +09001178 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1179 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1180 return 1;
1181
Tejun Heo1eedb4a2008-11-29 22:37:21 +09001182 /* TECRA M4 sometimes forgets its identify and reports bogus
1183 * DMI information. As the bogus information is a bit
1184 * generic, match as many entries as possible. This manual
1185 * matching is necessary because dmi_system_id.matches is
1186 * limited to four entries.
1187 */
Jiri Slaby3c387732008-12-10 14:07:22 +01001188 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1189 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1190 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1191 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1192 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1193 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1194 dmi_match(DMI_BOARD_VERSION, "Version A0"))
Tejun Heo1eedb4a2008-11-29 22:37:21 +09001195 return 1;
1196
Tejun Heo8c3832e2007-07-27 14:53:28 +09001197 return 0;
1198}
Tejun Heob8b275e2007-07-10 15:55:43 +09001199
1200static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1201{
1202 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1203 unsigned long flags;
1204 int rc = 0;
1205
1206 rc = ata_host_suspend(host, mesg);
1207 if (rc)
1208 return rc;
1209
1210 /* Some braindamaged ACPI suspend implementations expect the
1211 * controller to be awake on entry; otherwise, it burns cpu
1212 * cycles and power trying to do something to the sleeping
1213 * beauty.
1214 */
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001215 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
Tejun Heob8b275e2007-07-10 15:55:43 +09001216 pci_save_state(pdev);
1217
1218 /* mark its power state as "unknown", since we don't
1219 * know if e.g. the BIOS will change its device state
1220 * when we suspend.
1221 */
1222 if (pdev->current_state == PCI_D0)
1223 pdev->current_state = PCI_UNKNOWN;
1224
1225 /* tell resume that it's waking up from broken suspend */
1226 spin_lock_irqsave(&host->lock, flags);
1227 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1228 spin_unlock_irqrestore(&host->lock, flags);
1229 } else
1230 ata_pci_device_do_suspend(pdev, mesg);
1231
1232 return 0;
1233}
1234
1235static int piix_pci_device_resume(struct pci_dev *pdev)
1236{
1237 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1238 unsigned long flags;
1239 int rc;
1240
1241 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1242 spin_lock_irqsave(&host->lock, flags);
1243 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1244 spin_unlock_irqrestore(&host->lock, flags);
1245
1246 pci_set_power_state(pdev, PCI_D0);
1247 pci_restore_state(pdev);
1248
1249 /* PCI device wasn't disabled during suspend. Use
Tejun Heo0b62e132007-07-27 14:43:35 +09001250 * pci_reenable_device() to avoid affecting the enable
1251 * count.
Tejun Heob8b275e2007-07-10 15:55:43 +09001252 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001253 rc = pci_reenable_device(pdev);
Tejun Heob8b275e2007-07-10 15:55:43 +09001254 if (rc)
Joe Perchesa44fec12011-04-15 15:51:58 -07001255 dev_err(&pdev->dev,
1256 "failed to enable device after resume (%d)\n",
1257 rc);
Tejun Heob8b275e2007-07-10 15:55:43 +09001258 } else
1259 rc = ata_pci_device_do_resume(pdev);
1260
1261 if (rc == 0)
1262 ata_host_resume(host);
1263
1264 return rc;
1265}
1266#endif
1267
Tejun Heo25f98132008-01-07 19:38:53 +09001268static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1269{
1270 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1271}
1272
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273#define AHCI_PCI_BAR 5
1274#define AHCI_GLOBAL_CTL 0x04
1275#define AHCI_ENABLE (1 << 31)
1276static int piix_disable_ahci(struct pci_dev *pdev)
1277{
Jeff Garzikea6ba102005-08-30 05:18:18 -04001278 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279 u32 tmp;
1280 int rc = 0;
1281
1282 /* BUG: pci_enable_device has not yet been called. This
1283 * works because this device is usually set up by BIOS.
1284 */
1285
Jeff Garzik374b1872005-08-30 05:42:52 -04001286 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1287 !pci_resource_len(pdev, AHCI_PCI_BAR))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288 return 0;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001289
Jeff Garzik374b1872005-08-30 05:42:52 -04001290 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291 if (!mmio)
1292 return -ENOMEM;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001293
Alan Coxc47a6312007-11-19 14:28:28 +00001294 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295 if (tmp & AHCI_ENABLE) {
1296 tmp &= ~AHCI_ENABLE;
Alan Coxc47a6312007-11-19 14:28:28 +00001297 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298
Alan Coxc47a6312007-11-19 14:28:28 +00001299 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 if (tmp & AHCI_ENABLE)
1301 rc = -EIO;
1302 }
Greg Felix7b6dbd62005-07-28 15:54:15 -04001303
Jeff Garzik374b1872005-08-30 05:42:52 -04001304 pci_iounmap(pdev, mmio);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 return rc;
1306}
1307
1308/**
Alan Coxc621b142005-12-08 19:22:28 +00001309 * piix_check_450nx_errata - Check for problem 450NX setup
Randy Dunlapc893a3a2006-01-28 13:15:32 -05001310 * @ata_dev: the PCI device to check
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001311 *
Alan Coxc621b142005-12-08 19:22:28 +00001312 * Check for the present of 450NX errata #19 and errata #25. If
1313 * they are found return an error code so we can turn off DMA
1314 */
1315
1316static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1317{
1318 struct pci_dev *pdev = NULL;
1319 u16 cfg;
Alan Coxc621b142005-12-08 19:22:28 +00001320 int no_piix_dma = 0;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001321
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001322 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
Alan Coxc621b142005-12-08 19:22:28 +00001323 /* Look for 450NX PXB. Check for problem configurations
1324 A PCI quirk checks bit 6 already */
Alan Coxc621b142005-12-08 19:22:28 +00001325 pci_read_config_word(pdev, 0x41, &cfg);
1326 /* Only on the original revision: IDE DMA can hang */
Auke Kok44c10132007-06-08 15:46:36 -07001327 if (pdev->revision == 0x00)
Alan Coxc621b142005-12-08 19:22:28 +00001328 no_piix_dma = 1;
1329 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
Auke Kok44c10132007-06-08 15:46:36 -07001330 else if (cfg & (1<<14) && pdev->revision < 5)
Alan Coxc621b142005-12-08 19:22:28 +00001331 no_piix_dma = 2;
1332 }
Alan Cox31a34fe2006-05-22 22:58:14 +01001333 if (no_piix_dma)
Joe Perchesa44fec12011-04-15 15:51:58 -07001334 dev_warn(&ata_dev->dev,
1335 "450NX errata present, disabling IDE DMA%s\n",
1336 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1337 : "");
1338
Alan Coxc621b142005-12-08 19:22:28 +00001339 return no_piix_dma;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001340}
Alan Coxc621b142005-12-08 19:22:28 +00001341
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001342static void __devinit piix_init_pcs(struct ata_host *host,
Jeff Garzikea35d292006-07-11 11:48:50 -04001343 const struct piix_map_db *map_db)
1344{
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001345 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzikea35d292006-07-11 11:48:50 -04001346 u16 pcs, new_pcs;
1347
1348 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1349
1350 new_pcs = pcs | map_db->port_enable;
1351
1352 if (new_pcs != pcs) {
1353 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1354 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1355 msleep(150);
1356 }
1357}
1358
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001359static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1360 struct ata_port_info *pinfo,
1361 const struct piix_map_db *map_db)
Tejun Heod33f58b2006-03-01 01:25:39 +09001362{
Al Virob4482a42007-10-14 19:35:40 +01001363 const int *map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001364 int i, invalid_map = 0;
1365 u8 map_value;
1366
1367 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1368
1369 map = map_db->map[map_value & map_db->mask];
1370
Joe Perchesa44fec12011-04-15 15:51:58 -07001371 dev_info(&pdev->dev, "MAP [");
Tejun Heod33f58b2006-03-01 01:25:39 +09001372 for (i = 0; i < 4; i++) {
1373 switch (map[i]) {
1374 case RV:
1375 invalid_map = 1;
Joe Perchesa44fec12011-04-15 15:51:58 -07001376 pr_cont(" XX");
Tejun Heod33f58b2006-03-01 01:25:39 +09001377 break;
1378
1379 case NA:
Joe Perchesa44fec12011-04-15 15:51:58 -07001380 pr_cont(" --");
Tejun Heod33f58b2006-03-01 01:25:39 +09001381 break;
1382
1383 case IDE:
1384 WARN_ON((i & 1) || map[i + 1] != IDE);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001385 pinfo[i / 2] = piix_port_info[ich_pata_100];
Tejun Heod33f58b2006-03-01 01:25:39 +09001386 i++;
Joe Perchesa44fec12011-04-15 15:51:58 -07001387 pr_cont(" IDE IDE");
Tejun Heod33f58b2006-03-01 01:25:39 +09001388 break;
1389
1390 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07001391 pr_cont(" P%d", map[i]);
Tejun Heod33f58b2006-03-01 01:25:39 +09001392 if (i & 1)
Jeff Garzikcca39742006-08-24 03:19:22 -04001393 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
Tejun Heod33f58b2006-03-01 01:25:39 +09001394 break;
1395 }
1396 }
Joe Perchesa44fec12011-04-15 15:51:58 -07001397 pr_cont(" ]\n");
Tejun Heod33f58b2006-03-01 01:25:39 +09001398
1399 if (invalid_map)
Joe Perchesa44fec12011-04-15 15:51:58 -07001400 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
Tejun Heod33f58b2006-03-01 01:25:39 +09001401
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001402 return map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001403}
1404
Tejun Heoe9c16702009-03-03 13:52:16 +09001405static bool piix_no_sidpr(struct ata_host *host)
1406{
1407 struct pci_dev *pdev = to_pci_dev(host->dev);
1408
1409 /*
1410 * Samsung DB-P70 only has three ATA ports exposed and
1411 * curiously the unconnected first port reports link online
1412 * while not responding to SRST protocol causing excessive
1413 * detection delay.
1414 *
1415 * Unfortunately, the system doesn't carry enough DMI
1416 * information to identify the machine but does have subsystem
1417 * vendor and device set. As it's unclear whether the
1418 * subsystem vendor/device is used only for this specific
1419 * board, the port can't be disabled solely with the
1420 * information; however, turning off SIDPR access works around
1421 * the problem. Turn it off.
1422 *
1423 * This problem is reported in bnc#441240.
1424 *
1425 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1426 */
1427 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1428 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1429 pdev->subsystem_device == 0xb049) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001430 dev_warn(host->dev,
1431 "Samsung DB-P70 detected, disabling SIDPR\n");
Tejun Heoe9c16702009-03-03 13:52:16 +09001432 return true;
1433 }
1434
1435 return false;
1436}
1437
Tejun Heobe77e432008-07-31 17:02:44 +09001438static int __devinit piix_init_sidpr(struct ata_host *host)
Tejun Heoc7290722008-01-18 18:36:30 +09001439{
1440 struct pci_dev *pdev = to_pci_dev(host->dev);
1441 struct piix_host_priv *hpriv = host->private_data;
Tejun Heobe77e432008-07-31 17:02:44 +09001442 struct ata_link *link0 = &host->ports[0]->link;
Tejun Heocb6716c2008-05-01 10:03:08 +09001443 u32 scontrol;
Tejun Heobe77e432008-07-31 17:02:44 +09001444 int i, rc;
Tejun Heoc7290722008-01-18 18:36:30 +09001445
1446 /* check for availability */
1447 for (i = 0; i < 4; i++)
1448 if (hpriv->map[i] == IDE)
Tejun Heobe77e432008-07-31 17:02:44 +09001449 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001450
Tejun Heoe9c16702009-03-03 13:52:16 +09001451 /* is it blacklisted? */
1452 if (piix_no_sidpr(host))
1453 return 0;
1454
Tejun Heoc7290722008-01-18 18:36:30 +09001455 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
Tejun Heobe77e432008-07-31 17:02:44 +09001456 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001457
1458 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1459 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
Tejun Heobe77e432008-07-31 17:02:44 +09001460 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001461
1462 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
Tejun Heobe77e432008-07-31 17:02:44 +09001463 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001464
1465 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
Tejun Heocb6716c2008-05-01 10:03:08 +09001466
1467 /* SCR access via SIDPR doesn't work on some configurations.
1468 * Give it a test drive by inhibiting power save modes which
1469 * we'll do anyway.
1470 */
Tejun Heobe77e432008-07-31 17:02:44 +09001471 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
Tejun Heocb6716c2008-05-01 10:03:08 +09001472
1473 /* if IPM is already 3, SCR access is probably working. Don't
1474 * un-inhibit power save modes as BIOS might have inhibited
1475 * them for a reason.
1476 */
1477 if ((scontrol & 0xf00) != 0x300) {
1478 scontrol |= 0x300;
Tejun Heobe77e432008-07-31 17:02:44 +09001479 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1480 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
Tejun Heocb6716c2008-05-01 10:03:08 +09001481
1482 if ((scontrol & 0xf00) != 0x300) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001483 dev_info(host->dev,
1484 "SCR access via SIDPR is available but doesn't work\n");
Tejun Heobe77e432008-07-31 17:02:44 +09001485 return 0;
Tejun Heocb6716c2008-05-01 10:03:08 +09001486 }
1487 }
1488
Tejun Heobe77e432008-07-31 17:02:44 +09001489 /* okay, SCRs available, set ops and ask libata for slave_link */
1490 for (i = 0; i < 2; i++) {
1491 struct ata_port *ap = host->ports[i];
1492
1493 ap->ops = &piix_sidpr_sata_ops;
1494
1495 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1496 rc = ata_slave_link_init(ap);
1497 if (rc)
1498 return rc;
1499 }
1500 }
1501
1502 return 0;
Tejun Heoc7290722008-01-18 18:36:30 +09001503}
1504
Tejun Heo2852bcf2009-01-02 12:04:48 +09001505static void piix_iocfg_bit18_quirk(struct ata_host *host)
Tejun Heo43a98f02007-08-23 10:15:18 +09001506{
Jeff Garzik18552562007-10-03 15:15:40 -04001507 static const struct dmi_system_id sysids[] = {
Tejun Heo43a98f02007-08-23 10:15:18 +09001508 {
1509 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1510 * isn't used to boot the system which
1511 * disables the channel.
1512 */
1513 .ident = "M570U",
1514 .matches = {
1515 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1516 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1517 },
1518 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001519
1520 { } /* terminate list */
Tejun Heo43a98f02007-08-23 10:15:18 +09001521 };
Tejun Heo2852bcf2009-01-02 12:04:48 +09001522 struct pci_dev *pdev = to_pci_dev(host->dev);
1523 struct piix_host_priv *hpriv = host->private_data;
Tejun Heo43a98f02007-08-23 10:15:18 +09001524
1525 if (!dmi_check_system(sysids))
1526 return;
1527
1528 /* The datasheet says that bit 18 is NOOP but certain systems
1529 * seem to use it to disable a channel. Clear the bit on the
1530 * affected systems.
1531 */
Tejun Heo2852bcf2009-01-02 12:04:48 +09001532 if (hpriv->saved_iocfg & (1 << 18)) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001533 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
Tejun Heo2852bcf2009-01-02 12:04:48 +09001534 pci_write_config_dword(pdev, PIIX_IOCFG,
1535 hpriv->saved_iocfg & ~(1 << 18));
Tejun Heo43a98f02007-08-23 10:15:18 +09001536 }
1537}
1538
Rafael J. Wysocki5f451fe2009-01-19 20:59:22 +01001539static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1540{
1541 static const struct dmi_system_id broken_systems[] = {
1542 {
1543 .ident = "HP Compaq 2510p",
1544 .matches = {
1545 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1546 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1547 },
1548 /* PCI slot number of the controller */
1549 .driver_data = (void *)0x1FUL,
1550 },
Ville Syrjala65e31642009-05-19 01:37:44 +03001551 {
1552 .ident = "HP Compaq nc6000",
1553 .matches = {
1554 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1555 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1556 },
1557 /* PCI slot number of the controller */
1558 .driver_data = (void *)0x1FUL,
1559 },
Rafael J. Wysocki5f451fe2009-01-19 20:59:22 +01001560
1561 { } /* terminate list */
1562 };
1563 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1564
1565 if (dmi) {
1566 unsigned long slot = (unsigned long)dmi->driver_data;
1567 /* apply the quirk only to on-board controllers */
1568 return slot == PCI_SLOT(pdev->devfn);
1569 }
1570
1571 return false;
1572}
1573
Alan Coxc621b142005-12-08 19:22:28 +00001574/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575 * piix_init_one - Register PIIX ATA PCI device with kernel services
1576 * @pdev: PCI device to register
1577 * @ent: Entry in piix_pci_tbl matching with @pdev
1578 *
1579 * Called from kernel PCI layer. We probe for combined mode (sigh),
1580 * and then hand over control to libata, for it to do the rest.
1581 *
1582 * LOCKING:
1583 * Inherited from PCI layer (may sleep).
1584 *
1585 * RETURNS:
1586 * Zero on success, or -ERRNO value.
1587 */
1588
Adrian Bunkbc5468f2008-01-30 22:02:02 +02001589static int __devinit piix_init_one(struct pci_dev *pdev,
1590 const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591{
Tejun Heo24dc5f32007-01-20 16:00:28 +09001592 struct device *dev = &pdev->dev;
Tejun Heod33f58b2006-03-01 01:25:39 +09001593 struct ata_port_info port_info[2];
Tejun Heo1626aeb2007-05-04 12:43:58 +02001594 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
Tejun Heoa97c40062010-09-01 17:50:08 +02001595 struct scsi_host_template *sht = &piix_sht;
Jeff Garzikcca39742006-08-24 03:19:22 -04001596 unsigned long port_flags;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001597 struct ata_host *host;
1598 struct piix_host_priv *hpriv;
1599 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001600
Joe Perches06296a12011-04-15 15:52:00 -07001601 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602
Alan Cox347979a2009-05-06 17:10:08 +01001603 /* no hotplugging support for later devices (FIXME) */
1604 if (!in_module_init && ent->driver_data >= ich5_sata)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001605 return -ENODEV;
1606
Rafael J. Wysocki5f451fe2009-01-19 20:59:22 +01001607 if (piix_broken_system_poweroff(pdev)) {
1608 piix_port_info[ent->driver_data].flags |=
1609 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1610 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1611 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1612 "on poweroff and hibernation\n");
1613 }
1614
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001615 port_info[0] = piix_port_info[ent->driver_data];
1616 port_info[1] = piix_port_info[ent->driver_data];
1617
1618 port_flags = port_info[0].flags;
1619
1620 /* enable device and prepare host */
1621 rc = pcim_enable_device(pdev);
1622 if (rc)
1623 return rc;
1624
Tejun Heo2852bcf2009-01-02 12:04:48 +09001625 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1626 if (!hpriv)
1627 return -ENOMEM;
1628
1629 /* Save IOCFG, this will be used for cable detection, quirk
1630 * detection and restoration on detach. This is necessary
1631 * because some ACPI implementations mess up cable related
1632 * bits on _STM. Reported on kernel bz#11879.
1633 */
1634 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1635
Tejun Heo5016d7d2008-03-26 15:46:58 +09001636 /* ICH6R may be driven by either ata_piix or ahci driver
1637 * regardless of BIOS configuration. Make sure AHCI mode is
1638 * off.
1639 */
1640 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
Stephen Hemmingerda3ceb22008-09-08 09:31:39 -07001641 rc = piix_disable_ahci(pdev);
Tejun Heo5016d7d2008-03-26 15:46:58 +09001642 if (rc)
1643 return rc;
1644 }
1645
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001646 /* SATA map init can change port_info, do it before prepping host */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001647 if (port_flags & ATA_FLAG_SATA)
1648 hpriv->map = piix_init_sata_map(pdev, port_info,
1649 piix_map_db_table[ent->driver_data]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650
Tejun Heo1c5afdf2010-05-19 22:10:22 +02001651 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001652 if (rc)
1653 return rc;
1654 host->private_data = hpriv;
Tejun Heoff0fc142005-12-18 17:17:07 +09001655
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001656 /* initialize controller */
Tejun Heoc7290722008-01-18 18:36:30 +09001657 if (port_flags & ATA_FLAG_SATA) {
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001658 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
Tejun Heobe77e432008-07-31 17:02:44 +09001659 rc = piix_init_sidpr(host);
1660 if (rc)
1661 return rc;
Tejun Heoa97c40062010-09-01 17:50:08 +02001662 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1663 sht = &piix_sidpr_sht;
Tejun Heoc7290722008-01-18 18:36:30 +09001664 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665
Tejun Heo43a98f02007-08-23 10:15:18 +09001666 /* apply IOCFG bit18 quirk */
Tejun Heo2852bcf2009-01-02 12:04:48 +09001667 piix_iocfg_bit18_quirk(host);
Tejun Heo43a98f02007-08-23 10:15:18 +09001668
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669 /* On ICH5, some BIOSen disable the interrupt using the
1670 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1671 * On ICH6, this bit has the same effect, but only when
1672 * MSI is disabled (and it is disabled, as we don't use
1673 * message-signalled interrupts currently).
1674 */
Jeff Garzikcca39742006-08-24 03:19:22 -04001675 if (port_flags & PIIX_FLAG_CHECKINTR)
Brett M Russa04ce0f2005-08-15 15:23:41 -04001676 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001677
Alan Coxc621b142005-12-08 19:22:28 +00001678 if (piix_check_450nx_errata(pdev)) {
1679 /* This writes into the master table but it does not
1680 really matter for this errata as we will apply it to
1681 all the PIIX devices on the board */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001682 host->ports[0]->mwdma_mask = 0;
1683 host->ports[0]->udma_mask = 0;
1684 host->ports[1]->mwdma_mask = 0;
1685 host->ports[1]->udma_mask = 0;
Alan Coxc621b142005-12-08 19:22:28 +00001686 }
Arjan van de Ven517d3cc2009-05-13 15:02:42 +01001687 host->flags |= ATA_HOST_PARALLEL_SCAN;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001688
1689 pci_set_master(pdev);
Tejun Heoa97c40062010-09-01 17:50:08 +02001690 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691}
1692
Tejun Heo2852bcf2009-01-02 12:04:48 +09001693static void piix_remove_one(struct pci_dev *pdev)
1694{
1695 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1696 struct piix_host_priv *hpriv = host->private_data;
1697
1698 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1699
1700 ata_pci_remove_one(pdev);
1701}
1702
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703static int __init piix_init(void)
1704{
1705 int rc;
1706
Pavel Roskinb7887192006-08-10 18:13:18 +09001707 DPRINTK("pci_register_driver\n");
1708 rc = pci_register_driver(&piix_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709 if (rc)
1710 return rc;
1711
1712 in_module_init = 0;
1713
1714 DPRINTK("done\n");
1715 return 0;
1716}
1717
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718static void __exit piix_exit(void)
1719{
1720 pci_unregister_driver(&piix_pci_driver);
1721}
1722
1723module_init(piix_init);
1724module_exit(piix_exit);