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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparde294aedc2010-02-19 13:54:58 +00002 * Copyright (C) 2005 - 2010 ServerEngines
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
Sathya Perlab31c50a2009-09-17 10:30:13 -070064 MCC_STATUS_DMA_FAILED = 0x5,
Ajit Khaparde49643842009-10-05 02:22:05 +000065 MCC_STATUS_NOT_SUPPORTED = 66
Sathya Perla6b7c5b92009-03-11 23:32:03 -070066};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
Sathya Perlaf5209b42009-11-06 00:31:01 -080071#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070072
Sathya Perlaefd2e402009-07-27 22:53:10 +000073struct be_mcc_compl {
Sathya Perla6b7c5b92009-03-11 23:32:03 -070074 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
Sathya Perlaa8f447b2009-06-18 00:10:27 +000080/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
Somnath Koturcc4ce022010-10-21 07:11:14 -070085#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
86#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
Sathya Perlaa8f447b2009-06-18 00:10:27 +000087#define ASYNC_EVENT_CODE_LINK_STATE 0x1
Somnath Koturcc4ce022010-10-21 07:11:14 -070088#define ASYNC_EVENT_CODE_GRP_5 0x5
89#define ASYNC_EVENT_QOS_SPEED 0x1
90#define ASYNC_EVENT_COS_PRIORITY 0x2
Ajit Khaparde3968fa12011-02-20 11:41:53 +000091#define ASYNC_EVENT_PVID_STATE 0x3
Sathya Perlaa8f447b2009-06-18 00:10:27 +000092struct be_async_event_trailer {
93 u32 code;
94};
95
96enum {
97 ASYNC_EVENT_LINK_DOWN = 0x0,
98 ASYNC_EVENT_LINK_UP = 0x1
99};
100
101/* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112} __packed;
113
Somnath Koturcc4ce022010-10-21 07:11:14 -0700114/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123} __packed;
124
125/* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136} __packed;
137
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000138/* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148} __packed;
149
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700150struct be_mcc_mailbox {
151 struct be_mcc_wrb wrb;
Sathya Perlaefd2e402009-07-27 22:53:10 +0000152 struct be_mcc_compl compl;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700153};
154
155#define CMD_SUBSYSTEM_COMMON 0x1
156#define CMD_SUBSYSTEM_ETH 0x3
Suresh Rff33a6e2009-12-03 16:15:52 -0800157#define CMD_SUBSYSTEM_LOWLEVEL 0xb
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700158
159#define OPCODE_COMMON_NTWK_MAC_QUERY 1
160#define OPCODE_COMMON_NTWK_MAC_SET 2
161#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
162#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
163#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -0800164#define OPCODE_COMMON_READ_FLASHROM 6
Ajit Khaparde84517482009-09-04 03:12:16 +0000165#define OPCODE_COMMON_WRITE_FLASHROM 7
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700166#define OPCODE_COMMON_CQ_CREATE 12
167#define OPCODE_COMMON_EQ_CREATE 13
Somnath Koturcc4ce022010-10-21 07:11:14 -0700168#define OPCODE_COMMON_MCC_CREATE 21
Ajit Khapardee1d18732010-07-23 01:52:13 +0000169#define OPCODE_COMMON_SET_QOS 28
Somnath Koturcc4ce022010-10-21 07:11:14 -0700170#define OPCODE_COMMON_MCC_CREATE_EXT 90
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -0800171#define OPCODE_COMMON_SEEPROM_READ 30
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700172#define OPCODE_COMMON_NTWK_RX_FILTER 34
173#define OPCODE_COMMON_GET_FW_VERSION 35
174#define OPCODE_COMMON_SET_FLOW_CONTROL 36
175#define OPCODE_COMMON_GET_FLOW_CONTROL 37
176#define OPCODE_COMMON_SET_FRAME_SIZE 39
177#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
178#define OPCODE_COMMON_FIRMWARE_CONFIG 42
179#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
180#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
Sathya Perla5fb379e2009-06-18 00:02:59 +0000181#define OPCODE_COMMON_MCC_DESTROY 53
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700182#define OPCODE_COMMON_CQ_DESTROY 54
183#define OPCODE_COMMON_EQ_DESTROY 55
184#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
185#define OPCODE_COMMON_NTWK_PMAC_ADD 59
186#define OPCODE_COMMON_NTWK_PMAC_DEL 60
sarveshwarb14074ea2009-08-05 13:05:24 -0700187#define OPCODE_COMMON_FUNCTION_RESET 61
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -0700188#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
189#define OPCODE_COMMON_GET_BEACON_STATE 70
Sarveshwar Bandi0388f252009-10-28 04:15:20 -0700190#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000191#define OPCODE_COMMON_GET_PHY_DETAILS 102
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000192#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700193
Sathya Perla3abcded2010-10-03 22:12:27 -0700194#define OPCODE_ETH_RSS_CONFIG 1
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700195#define OPCODE_ETH_ACPI_CONFIG 2
196#define OPCODE_ETH_PROMISCUOUS 3
197#define OPCODE_ETH_GET_STATISTICS 4
198#define OPCODE_ETH_TX_CREATE 7
199#define OPCODE_ETH_RX_CREATE 8
200#define OPCODE_ETH_TX_DESTROY 9
201#define OPCODE_ETH_RX_DESTROY 10
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000202#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700203
Suresh Rff33a6e2009-12-03 16:15:52 -0800204#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
205#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
Sarveshwar Bandifced9992009-12-23 04:41:44 +0000206#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
Suresh Rff33a6e2009-12-03 16:15:52 -0800207
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700208struct be_cmd_req_hdr {
209 u8 opcode; /* dword 0 */
210 u8 subsystem; /* dword 0 */
211 u8 port_number; /* dword 0 */
212 u8 domain; /* dword 0 */
213 u32 timeout; /* dword 1 */
214 u32 request_length; /* dword 2 */
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000215 u8 version; /* dword 3 */
216 u8 rsvd[3]; /* dword 3 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700217};
218
219#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
220#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
221struct be_cmd_resp_hdr {
222 u32 info; /* dword 0 */
223 u32 status; /* dword 1 */
224 u32 response_length; /* dword 2 */
225 u32 actual_resp_len; /* dword 3 */
226};
227
228struct phys_addr {
229 u32 lo;
230 u32 hi;
231};
232
233/**************************
234 * BE Command definitions *
235 **************************/
236
237/* Pseudo amap definition in which each bit of the actual structure is defined
238 * as a byte: used to calculate offset/shift/mask of each field */
239struct amap_eq_context {
240 u8 cidx[13]; /* dword 0*/
241 u8 rsvd0[3]; /* dword 0*/
242 u8 epidx[13]; /* dword 0*/
243 u8 valid; /* dword 0*/
244 u8 rsvd1; /* dword 0*/
245 u8 size; /* dword 0*/
246 u8 pidx[13]; /* dword 1*/
247 u8 rsvd2[3]; /* dword 1*/
248 u8 pd[10]; /* dword 1*/
249 u8 count[3]; /* dword 1*/
250 u8 solevent; /* dword 1*/
251 u8 stalled; /* dword 1*/
252 u8 armed; /* dword 1*/
253 u8 rsvd3[4]; /* dword 2*/
254 u8 func[8]; /* dword 2*/
255 u8 rsvd4; /* dword 2*/
256 u8 delaymult[10]; /* dword 2*/
257 u8 rsvd5[2]; /* dword 2*/
258 u8 phase[2]; /* dword 2*/
259 u8 nodelay; /* dword 2*/
260 u8 rsvd6[4]; /* dword 2*/
261 u8 rsvd7[32]; /* dword 3*/
262} __packed;
263
264struct be_cmd_req_eq_create {
265 struct be_cmd_req_hdr hdr;
266 u16 num_pages; /* sword */
267 u16 rsvd0; /* sword */
268 u8 context[sizeof(struct amap_eq_context) / 8];
269 struct phys_addr pages[8];
270} __packed;
271
272struct be_cmd_resp_eq_create {
273 struct be_cmd_resp_hdr resp_hdr;
274 u16 eq_id; /* sword */
275 u16 rsvd0; /* sword */
276} __packed;
277
278/******************** Mac query ***************************/
279enum {
280 MAC_ADDRESS_TYPE_STORAGE = 0x0,
281 MAC_ADDRESS_TYPE_NETWORK = 0x1,
282 MAC_ADDRESS_TYPE_PD = 0x2,
283 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
284};
285
286struct mac_addr {
287 u16 size_of_struct;
288 u8 addr[ETH_ALEN];
289} __packed;
290
291struct be_cmd_req_mac_query {
292 struct be_cmd_req_hdr hdr;
293 u8 type;
294 u8 permanent;
295 u16 if_id;
296} __packed;
297
298struct be_cmd_resp_mac_query {
299 struct be_cmd_resp_hdr hdr;
300 struct mac_addr mac;
301};
302
303/******************** PMac Add ***************************/
304struct be_cmd_req_pmac_add {
305 struct be_cmd_req_hdr hdr;
306 u32 if_id;
307 u8 mac_address[ETH_ALEN];
308 u8 rsvd0[2];
309} __packed;
310
311struct be_cmd_resp_pmac_add {
312 struct be_cmd_resp_hdr hdr;
313 u32 pmac_id;
314};
315
316/******************** PMac Del ***************************/
317struct be_cmd_req_pmac_del {
318 struct be_cmd_req_hdr hdr;
319 u32 if_id;
320 u32 pmac_id;
321};
322
323/******************** Create CQ ***************************/
324/* Pseudo amap definition in which each bit of the actual structure is defined
325 * as a byte: used to calculate offset/shift/mask of each field */
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000326struct amap_cq_context_be {
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700327 u8 cidx[11]; /* dword 0*/
328 u8 rsvd0; /* dword 0*/
329 u8 coalescwm[2]; /* dword 0*/
330 u8 nodelay; /* dword 0*/
331 u8 epidx[11]; /* dword 0*/
332 u8 rsvd1; /* dword 0*/
333 u8 count[2]; /* dword 0*/
334 u8 valid; /* dword 0*/
335 u8 solevent; /* dword 0*/
336 u8 eventable; /* dword 0*/
337 u8 pidx[11]; /* dword 1*/
338 u8 rsvd2; /* dword 1*/
339 u8 pd[10]; /* dword 1*/
340 u8 eqid[8]; /* dword 1*/
341 u8 stalled; /* dword 1*/
342 u8 armed; /* dword 1*/
343 u8 rsvd3[4]; /* dword 2*/
344 u8 func[8]; /* dword 2*/
345 u8 rsvd4[20]; /* dword 2*/
346 u8 rsvd5[32]; /* dword 3*/
347} __packed;
348
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000349struct amap_cq_context_lancer {
350 u8 rsvd0[12]; /* dword 0*/
351 u8 coalescwm[2]; /* dword 0*/
352 u8 nodelay; /* dword 0*/
353 u8 rsvd1[12]; /* dword 0*/
354 u8 count[2]; /* dword 0*/
355 u8 valid; /* dword 0*/
356 u8 rsvd2; /* dword 0*/
357 u8 eventable; /* dword 0*/
358 u8 eqid[16]; /* dword 1*/
359 u8 rsvd3[15]; /* dword 1*/
360 u8 armed; /* dword 1*/
361 u8 rsvd4[32]; /* dword 2*/
362 u8 rsvd5[32]; /* dword 3*/
363} __packed;
364
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700365struct be_cmd_req_cq_create {
366 struct be_cmd_req_hdr hdr;
367 u16 num_pages;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000368 u8 page_size;
369 u8 rsvd0;
370 u8 context[sizeof(struct amap_cq_context_be) / 8];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700371 struct phys_addr pages[8];
372} __packed;
373
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000374
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700375struct be_cmd_resp_cq_create {
376 struct be_cmd_resp_hdr hdr;
377 u16 cq_id;
378 u16 rsvd0;
379} __packed;
380
Sathya Perla5fb379e2009-06-18 00:02:59 +0000381/******************** Create MCCQ ***************************/
382/* Pseudo amap definition in which each bit of the actual structure is defined
383 * as a byte: used to calculate offset/shift/mask of each field */
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000384struct amap_mcc_context_be {
Sathya Perla5fb379e2009-06-18 00:02:59 +0000385 u8 con_index[14];
386 u8 rsvd0[2];
387 u8 ring_size[4];
388 u8 fetch_wrb;
389 u8 fetch_r2t;
390 u8 cq_id[10];
391 u8 prod_index[14];
392 u8 fid[8];
393 u8 pdid[9];
394 u8 valid;
395 u8 rsvd1[32];
396 u8 rsvd2[32];
397} __packed;
398
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000399struct amap_mcc_context_lancer {
400 u8 async_cq_id[16];
401 u8 ring_size[4];
402 u8 rsvd0[12];
403 u8 rsvd1[31];
404 u8 valid;
405 u8 async_cq_valid[1];
406 u8 rsvd2[31];
407 u8 rsvd3[32];
408} __packed;
409
Sathya Perla5fb379e2009-06-18 00:02:59 +0000410struct be_cmd_req_mcc_create {
411 struct be_cmd_req_hdr hdr;
412 u16 num_pages;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000413 u16 cq_id;
Somnath Koturcc4ce022010-10-21 07:11:14 -0700414 u32 async_event_bitmap[1];
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000415 u8 context[sizeof(struct amap_mcc_context_be) / 8];
Sathya Perla5fb379e2009-06-18 00:02:59 +0000416 struct phys_addr pages[8];
417} __packed;
418
419struct be_cmd_resp_mcc_create {
420 struct be_cmd_resp_hdr hdr;
421 u16 id;
422 u16 rsvd0;
423} __packed;
424
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700425/******************** Create TxQ ***************************/
426#define BE_ETH_TX_RING_TYPE_STANDARD 2
427#define BE_ULP1_NUM 1
428
429/* Pseudo amap definition in which each bit of the actual structure is defined
430 * as a byte: used to calculate offset/shift/mask of each field */
431struct amap_tx_context {
432 u8 rsvd0[16]; /* dword 0 */
433 u8 tx_ring_size[4]; /* dword 0 */
434 u8 rsvd1[26]; /* dword 0 */
435 u8 pci_func_id[8]; /* dword 1 */
436 u8 rsvd2[9]; /* dword 1 */
437 u8 ctx_valid; /* dword 1 */
438 u8 cq_id_send[16]; /* dword 2 */
439 u8 rsvd3[16]; /* dword 2 */
440 u8 rsvd4[32]; /* dword 3 */
441 u8 rsvd5[32]; /* dword 4 */
442 u8 rsvd6[32]; /* dword 5 */
443 u8 rsvd7[32]; /* dword 6 */
444 u8 rsvd8[32]; /* dword 7 */
445 u8 rsvd9[32]; /* dword 8 */
446 u8 rsvd10[32]; /* dword 9 */
447 u8 rsvd11[32]; /* dword 10 */
448 u8 rsvd12[32]; /* dword 11 */
449 u8 rsvd13[32]; /* dword 12 */
450 u8 rsvd14[32]; /* dword 13 */
451 u8 rsvd15[32]; /* dword 14 */
452 u8 rsvd16[32]; /* dword 15 */
453} __packed;
454
455struct be_cmd_req_eth_tx_create {
456 struct be_cmd_req_hdr hdr;
457 u8 num_pages;
458 u8 ulp_num;
459 u8 type;
460 u8 bound_port;
461 u8 context[sizeof(struct amap_tx_context) / 8];
462 struct phys_addr pages[8];
463} __packed;
464
465struct be_cmd_resp_eth_tx_create {
466 struct be_cmd_resp_hdr hdr;
467 u16 cid;
468 u16 rsvd0;
469} __packed;
470
471/******************** Create RxQ ***************************/
472struct be_cmd_req_eth_rx_create {
473 struct be_cmd_req_hdr hdr;
474 u16 cq_id;
475 u8 frag_size;
476 u8 num_pages;
477 struct phys_addr pages[2];
478 u32 interface_id;
479 u16 max_frame_size;
480 u16 rsvd0;
481 u32 rss_queue;
482} __packed;
483
484struct be_cmd_resp_eth_rx_create {
485 struct be_cmd_resp_hdr hdr;
486 u16 id;
Sathya Perla3abcded2010-10-03 22:12:27 -0700487 u8 rss_id;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700488 u8 rsvd0;
489} __packed;
490
491/******************** Q Destroy ***************************/
492/* Type of Queue to be destroyed */
493enum {
494 QTYPE_EQ = 1,
495 QTYPE_CQ,
496 QTYPE_TXQ,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000497 QTYPE_RXQ,
498 QTYPE_MCCQ
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700499};
500
501struct be_cmd_req_q_destroy {
502 struct be_cmd_req_hdr hdr;
503 u16 id;
504 u16 bypass_flush; /* valid only for rx q destroy */
505} __packed;
506
507/************ I/f Create (it's actually I/f Config Create)**********/
508
509/* Capability flags for the i/f */
510enum be_if_flags {
511 BE_IF_FLAGS_RSS = 0x4,
512 BE_IF_FLAGS_PROMISCUOUS = 0x8,
513 BE_IF_FLAGS_BROADCAST = 0x10,
514 BE_IF_FLAGS_UNTAGGED = 0x20,
515 BE_IF_FLAGS_ULP = 0x40,
516 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
517 BE_IF_FLAGS_VLAN = 0x100,
518 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
519 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
520 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
521};
522
523/* An RX interface is an object with one or more MAC addresses and
524 * filtering capabilities. */
525struct be_cmd_req_if_create {
526 struct be_cmd_req_hdr hdr;
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200527 u32 version; /* ignore currently */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700528 u32 capability_flags;
529 u32 enable_flags;
530 u8 mac_addr[ETH_ALEN];
531 u8 rsvd0;
532 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
533 u32 vlan_tag; /* not used currently */
534} __packed;
535
536struct be_cmd_resp_if_create {
537 struct be_cmd_resp_hdr hdr;
538 u32 interface_id;
539 u32 pmac_id;
540};
541
542/****** I/f Destroy(it's actually I/f Config Destroy )**********/
543struct be_cmd_req_if_destroy {
544 struct be_cmd_req_hdr hdr;
545 u32 interface_id;
546};
547
548/*************** HW Stats Get **********************************/
549struct be_port_rxf_stats {
550 u32 rx_bytes_lsd; /* dword 0*/
551 u32 rx_bytes_msd; /* dword 1*/
552 u32 rx_total_frames; /* dword 2*/
553 u32 rx_unicast_frames; /* dword 3*/
554 u32 rx_multicast_frames; /* dword 4*/
555 u32 rx_broadcast_frames; /* dword 5*/
556 u32 rx_crc_errors; /* dword 6*/
557 u32 rx_alignment_symbol_errors; /* dword 7*/
558 u32 rx_pause_frames; /* dword 8*/
559 u32 rx_control_frames; /* dword 9*/
560 u32 rx_in_range_errors; /* dword 10*/
561 u32 rx_out_range_errors; /* dword 11*/
562 u32 rx_frame_too_long; /* dword 12*/
563 u32 rx_address_match_errors; /* dword 13*/
564 u32 rx_vlan_mismatch; /* dword 14*/
565 u32 rx_dropped_too_small; /* dword 15*/
566 u32 rx_dropped_too_short; /* dword 16*/
567 u32 rx_dropped_header_too_small; /* dword 17*/
568 u32 rx_dropped_tcp_length; /* dword 18*/
569 u32 rx_dropped_runt; /* dword 19*/
570 u32 rx_64_byte_packets; /* dword 20*/
571 u32 rx_65_127_byte_packets; /* dword 21*/
572 u32 rx_128_256_byte_packets; /* dword 22*/
573 u32 rx_256_511_byte_packets; /* dword 23*/
574 u32 rx_512_1023_byte_packets; /* dword 24*/
575 u32 rx_1024_1518_byte_packets; /* dword 25*/
576 u32 rx_1519_2047_byte_packets; /* dword 26*/
577 u32 rx_2048_4095_byte_packets; /* dword 27*/
578 u32 rx_4096_8191_byte_packets; /* dword 28*/
579 u32 rx_8192_9216_byte_packets; /* dword 29*/
580 u32 rx_ip_checksum_errs; /* dword 30*/
581 u32 rx_tcp_checksum_errs; /* dword 31*/
582 u32 rx_udp_checksum_errs; /* dword 32*/
583 u32 rx_non_rss_packets; /* dword 33*/
584 u32 rx_ipv4_packets; /* dword 34*/
585 u32 rx_ipv6_packets; /* dword 35*/
586 u32 rx_ipv4_bytes_lsd; /* dword 36*/
587 u32 rx_ipv4_bytes_msd; /* dword 37*/
588 u32 rx_ipv6_bytes_lsd; /* dword 38*/
589 u32 rx_ipv6_bytes_msd; /* dword 39*/
590 u32 rx_chute1_packets; /* dword 40*/
591 u32 rx_chute2_packets; /* dword 41*/
592 u32 rx_chute3_packets; /* dword 42*/
593 u32 rx_management_packets; /* dword 43*/
594 u32 rx_switched_unicast_packets; /* dword 44*/
595 u32 rx_switched_multicast_packets; /* dword 45*/
596 u32 rx_switched_broadcast_packets; /* dword 46*/
597 u32 tx_bytes_lsd; /* dword 47*/
598 u32 tx_bytes_msd; /* dword 48*/
599 u32 tx_unicastframes; /* dword 49*/
600 u32 tx_multicastframes; /* dword 50*/
601 u32 tx_broadcastframes; /* dword 51*/
602 u32 tx_pauseframes; /* dword 52*/
603 u32 tx_controlframes; /* dword 53*/
604 u32 tx_64_byte_packets; /* dword 54*/
605 u32 tx_65_127_byte_packets; /* dword 55*/
606 u32 tx_128_256_byte_packets; /* dword 56*/
607 u32 tx_256_511_byte_packets; /* dword 57*/
608 u32 tx_512_1023_byte_packets; /* dword 58*/
609 u32 tx_1024_1518_byte_packets; /* dword 59*/
610 u32 tx_1519_2047_byte_packets; /* dword 60*/
611 u32 tx_2048_4095_byte_packets; /* dword 61*/
612 u32 tx_4096_8191_byte_packets; /* dword 62*/
613 u32 tx_8192_9216_byte_packets; /* dword 63*/
614 u32 rx_fifo_overflow; /* dword 64*/
615 u32 rx_input_fifo_overflow; /* dword 65*/
616};
617
618struct be_rxf_stats {
619 struct be_port_rxf_stats port[2];
620 u32 rx_drops_no_pbuf; /* dword 132*/
621 u32 rx_drops_no_txpb; /* dword 133*/
622 u32 rx_drops_no_erx_descr; /* dword 134*/
623 u32 rx_drops_no_tpre_descr; /* dword 135*/
624 u32 management_rx_port_packets; /* dword 136*/
625 u32 management_rx_port_bytes; /* dword 137*/
626 u32 management_rx_port_pause_frames; /* dword 138*/
627 u32 management_rx_port_errors; /* dword 139*/
628 u32 management_tx_port_packets; /* dword 140*/
629 u32 management_tx_port_bytes; /* dword 141*/
630 u32 management_tx_port_pause; /* dword 142*/
631 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
632 u32 rx_drops_too_many_frags; /* dword 144*/
633 u32 rx_drops_invalid_ring; /* dword 145*/
634 u32 forwarded_packets; /* dword 146*/
635 u32 rx_drops_mtu; /* dword 147*/
Ajit Khapardef6c4bf32011-02-20 11:41:04 +0000636 u32 rsvd0[7];
637 u32 port0_jabber_events;
638 u32 port1_jabber_events;
639 u32 rsvd1[6];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700640};
641
642struct be_erx_stats {
643 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
644 u32 debug_wdma_sent_hold; /* dword 44*/
645 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
646 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
647 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
648};
649
Ajit Khapardef6c4bf32011-02-20 11:41:04 +0000650struct be_pmem_stats {
651 u32 eth_red_drops;
652 u32 rsvd[4];
653};
654
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700655struct be_hw_stats {
656 struct be_rxf_stats rxf;
657 u32 rsvd[48];
658 struct be_erx_stats erx;
Ajit Khapardef6c4bf32011-02-20 11:41:04 +0000659 struct be_pmem_stats pmem;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700660};
661
662struct be_cmd_req_get_stats {
663 struct be_cmd_req_hdr hdr;
664 u8 rsvd[sizeof(struct be_hw_stats)];
665};
666
667struct be_cmd_resp_get_stats {
668 struct be_cmd_resp_hdr hdr;
669 struct be_hw_stats hw_stats;
670};
671
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000672struct be_cmd_req_get_cntl_addnl_attribs {
673 struct be_cmd_req_hdr hdr;
674 u8 rsvd[8];
675};
676
677struct be_cmd_resp_get_cntl_addnl_attribs {
678 struct be_cmd_resp_hdr hdr;
679 u16 ipl_file_number;
680 u8 ipl_file_version;
681 u8 rsvd0;
682 u8 on_die_temperature; /* in degrees centigrade*/
683 u8 rsvd1[3];
684};
685
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700686struct be_cmd_req_vlan_config {
687 struct be_cmd_req_hdr hdr;
688 u8 interface_id;
689 u8 promiscuous;
690 u8 untagged;
691 u8 num_vlan;
692 u16 normal_vlan[64];
693} __packed;
694
695struct be_cmd_req_promiscuous_config {
696 struct be_cmd_req_hdr hdr;
697 u8 port0_promiscuous;
698 u8 port1_promiscuous;
699 u16 rsvd0;
700} __packed;
701
Sathya Perlae7b909a2009-11-22 22:01:10 +0000702/******************** Multicast MAC Config *******************/
703#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700704struct macaddr {
705 u8 byte[ETH_ALEN];
706};
707
708struct be_cmd_req_mcast_mac_config {
709 struct be_cmd_req_hdr hdr;
710 u16 num_mac;
711 u8 promiscuous;
712 u8 interface_id;
Sathya Perlae7b909a2009-11-22 22:01:10 +0000713 struct macaddr mac[BE_MAX_MC];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700714} __packed;
715
716static inline struct be_hw_stats *
717hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
718{
719 return &cmd->hw_stats;
720}
721
722/******************** Link Status Query *******************/
723struct be_cmd_req_link_status {
724 struct be_cmd_req_hdr hdr;
725 u32 rsvd;
726};
727
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700728enum {
729 PHY_LINK_DUPLEX_NONE = 0x0,
730 PHY_LINK_DUPLEX_HALF = 0x1,
731 PHY_LINK_DUPLEX_FULL = 0x2
732};
733
734enum {
735 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
736 PHY_LINK_SPEED_10MBPS = 0x1,
737 PHY_LINK_SPEED_100MBPS = 0x2,
738 PHY_LINK_SPEED_1GBPS = 0x3,
739 PHY_LINK_SPEED_10GBPS = 0x4
740};
741
742struct be_cmd_resp_link_status {
743 struct be_cmd_resp_hdr hdr;
744 u8 physical_port;
745 u8 mac_duplex;
746 u8 mac_speed;
747 u8 mac_fault;
748 u8 mgmt_mac_duplex;
749 u8 mgmt_mac_speed;
Sarveshwar Bandi0388f252009-10-28 04:15:20 -0700750 u16 link_speed;
751 u32 rsvd0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700752} __packed;
753
Sarveshwar Bandi0388f252009-10-28 04:15:20 -0700754/******************** Port Identification ***************************/
755/* Identifies the type of port attached to NIC */
756struct be_cmd_req_port_type {
757 struct be_cmd_req_hdr hdr;
758 u32 page_num;
759 u32 port;
760};
761
762enum {
763 TR_PAGE_A0 = 0xa0,
764 TR_PAGE_A2 = 0xa2
765};
766
767struct be_cmd_resp_port_type {
768 struct be_cmd_resp_hdr hdr;
769 u32 page_num;
770 u32 port;
771 struct data {
772 u8 identifier;
773 u8 identifier_ext;
774 u8 connector;
775 u8 transceiver[8];
776 u8 rsvd0[3];
777 u8 length_km;
778 u8 length_hm;
779 u8 length_om1;
780 u8 length_om2;
781 u8 length_cu;
782 u8 length_cu_m;
783 u8 vendor_name[16];
784 u8 rsvd;
785 u8 vendor_oui[3];
786 u8 vendor_pn[16];
787 u8 vendor_rev[4];
788 } data;
789};
790
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700791/******************** Get FW Version *******************/
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700792struct be_cmd_req_get_fw_version {
793 struct be_cmd_req_hdr hdr;
794 u8 rsvd0[FW_VER_LEN];
795 u8 rsvd1[FW_VER_LEN];
796} __packed;
797
798struct be_cmd_resp_get_fw_version {
799 struct be_cmd_resp_hdr hdr;
800 u8 firmware_version_string[FW_VER_LEN];
801 u8 fw_on_flash_version_string[FW_VER_LEN];
802} __packed;
803
804/******************** Set Flow Contrl *******************/
805struct be_cmd_req_set_flow_control {
806 struct be_cmd_req_hdr hdr;
807 u16 tx_flow_control;
808 u16 rx_flow_control;
809} __packed;
810
811/******************** Get Flow Contrl *******************/
812struct be_cmd_req_get_flow_control {
813 struct be_cmd_req_hdr hdr;
814 u32 rsvd;
815};
816
817struct be_cmd_resp_get_flow_control {
818 struct be_cmd_resp_hdr hdr;
819 u16 tx_flow_control;
820 u16 rx_flow_control;
821} __packed;
822
823/******************** Modify EQ Delay *******************/
824struct be_cmd_req_modify_eq_delay {
825 struct be_cmd_req_hdr hdr;
826 u32 num_eq;
827 struct {
828 u32 eq_id;
829 u32 phase;
830 u32 delay_multiplier;
831 } delay[8];
832} __packed;
833
834struct be_cmd_resp_modify_eq_delay {
835 struct be_cmd_resp_hdr hdr;
836 u32 rsvd0;
837} __packed;
838
839/******************** Get FW Config *******************/
Sathya Perla3abcded2010-10-03 22:12:27 -0700840#define BE_FUNCTION_CAPS_RSS 0x2
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700841struct be_cmd_req_query_fw_cfg {
842 struct be_cmd_req_hdr hdr;
Sathya Perla3abcded2010-10-03 22:12:27 -0700843 u32 rsvd[31];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700844};
845
846struct be_cmd_resp_query_fw_cfg {
847 struct be_cmd_resp_hdr hdr;
848 u32 be_config_number;
849 u32 asic_revision;
850 u32 phys_port;
Ajit Khaparde3486be22010-07-23 02:04:54 +0000851 u32 function_mode;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700852 u32 rsvd[26];
Sathya Perla3abcded2010-10-03 22:12:27 -0700853 u32 function_caps;
854};
855
856/******************** RSS Config *******************/
857/* RSS types */
858#define RSS_ENABLE_NONE 0x0
859#define RSS_ENABLE_IPV4 0x1
860#define RSS_ENABLE_TCP_IPV4 0x2
861#define RSS_ENABLE_IPV6 0x4
862#define RSS_ENABLE_TCP_IPV6 0x8
863
864struct be_cmd_req_rss_config {
865 struct be_cmd_req_hdr hdr;
866 u32 if_id;
867 u16 enable_rss;
868 u16 cpu_table_size_log2;
869 u32 hash[10];
870 u8 cpu_table[128];
871 u8 flush;
872 u8 rsvd0[3];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700873};
874
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -0700875/******************** Port Beacon ***************************/
876
877#define BEACON_STATE_ENABLED 0x1
878#define BEACON_STATE_DISABLED 0x0
879
880struct be_cmd_req_enable_disable_beacon {
881 struct be_cmd_req_hdr hdr;
882 u8 port_num;
883 u8 beacon_state;
884 u8 beacon_duration;
885 u8 status_duration;
886} __packed;
887
888struct be_cmd_resp_enable_disable_beacon {
889 struct be_cmd_resp_hdr resp_hdr;
890 u32 rsvd0;
891} __packed;
892
893struct be_cmd_req_get_beacon_state {
894 struct be_cmd_req_hdr hdr;
895 u8 port_num;
896 u8 rsvd0;
897 u16 rsvd1;
898} __packed;
899
900struct be_cmd_resp_get_beacon_state {
901 struct be_cmd_resp_hdr resp_hdr;
902 u8 beacon_state;
903 u8 rsvd0[3];
904} __packed;
905
Ajit Khaparde84517482009-09-04 03:12:16 +0000906/****************** Firmware Flash ******************/
907struct flashrom_params {
908 u32 op_code;
909 u32 op_type;
910 u32 data_buf_size;
911 u32 offset;
912 u8 data_buf[4];
913};
914
915struct be_cmd_write_flashrom {
916 struct be_cmd_req_hdr hdr;
917 struct flashrom_params params;
918};
919
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000920/************************ WOL *******************************/
921struct be_cmd_req_acpi_wol_magic_config{
922 struct be_cmd_req_hdr hdr;
923 u32 rsvd0[145];
924 u8 magic_mac[6];
925 u8 rsvd2[2];
926} __packed;
927
Suresh Rff33a6e2009-12-03 16:15:52 -0800928/********************** LoopBack test *********************/
929struct be_cmd_req_loopback_test {
930 struct be_cmd_req_hdr hdr;
931 u32 loopback_type;
932 u32 num_pkts;
933 u64 pattern;
934 u32 src_port;
935 u32 dest_port;
936 u32 pkt_size;
937};
938
939struct be_cmd_resp_loopback_test {
940 struct be_cmd_resp_hdr resp_hdr;
941 u32 status;
942 u32 num_txfer;
943 u32 num_rx;
944 u32 miscomp_off;
945 u32 ticks_compl;
946};
947
Sarveshwar Bandifced9992009-12-23 04:41:44 +0000948struct be_cmd_req_set_lmode {
949 struct be_cmd_req_hdr hdr;
950 u8 src_port;
951 u8 dest_port;
952 u8 loopback_type;
953 u8 loopback_state;
954};
955
956struct be_cmd_resp_set_lmode {
957 struct be_cmd_resp_hdr resp_hdr;
958 u8 rsvd0[4];
959};
960
Suresh Rff33a6e2009-12-03 16:15:52 -0800961/********************** DDR DMA test *********************/
962struct be_cmd_req_ddrdma_test {
963 struct be_cmd_req_hdr hdr;
964 u64 pattern;
965 u32 byte_count;
966 u32 rsvd0;
967 u8 snd_buff[4096];
968 u8 rsvd1[4096];
969};
970
971struct be_cmd_resp_ddrdma_test {
972 struct be_cmd_resp_hdr hdr;
973 u64 pattern;
974 u32 byte_cnt;
975 u32 snd_err;
976 u8 rsvd0[4096];
977 u8 rcv_buff[4096];
978};
979
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -0800980/*********************** SEEPROM Read ***********************/
981
982#define BE_READ_SEEPROM_LEN 1024
983struct be_cmd_req_seeprom_read {
984 struct be_cmd_req_hdr hdr;
985 u8 rsvd0[BE_READ_SEEPROM_LEN];
986};
987
988struct be_cmd_resp_seeprom_read {
989 struct be_cmd_req_hdr hdr;
990 u8 seeprom_data[BE_READ_SEEPROM_LEN];
991};
992
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000993enum {
994 PHY_TYPE_CX4_10GB = 0,
995 PHY_TYPE_XFP_10GB,
996 PHY_TYPE_SFP_1GB,
997 PHY_TYPE_SFP_PLUS_10GB,
998 PHY_TYPE_KR_10GB,
999 PHY_TYPE_KX4_10GB,
1000 PHY_TYPE_BASET_10GB,
1001 PHY_TYPE_BASET_1GB,
1002 PHY_TYPE_DISABLED = 255
1003};
1004
1005struct be_cmd_req_get_phy_info {
1006 struct be_cmd_req_hdr hdr;
1007 u8 rsvd0[24];
1008};
1009struct be_cmd_resp_get_phy_info {
1010 struct be_cmd_req_hdr hdr;
1011 u16 phy_type;
1012 u16 interface_type;
1013 u32 misc_params;
1014 u32 future_use[4];
1015};
1016
Ajit Khapardee1d18732010-07-23 01:52:13 +00001017/*********************** Set QOS ***********************/
1018
1019#define BE_QOS_BITS_NIC 1
1020
1021struct be_cmd_req_set_qos {
1022 struct be_cmd_req_hdr hdr;
1023 u32 valid_bits;
1024 u32 max_bps_nic;
1025 u32 rsvd[7];
1026};
1027
1028struct be_cmd_resp_set_qos {
1029 struct be_cmd_resp_hdr hdr;
1030 u32 rsvd;
1031};
1032
Sathya Perla8788fdc2009-07-27 22:52:03 +00001033extern int be_pci_fnum_get(struct be_adapter *adapter);
1034extern int be_cmd_POST(struct be_adapter *adapter);
1035extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001036 u8 type, bool permanent, u32 if_handle);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001037extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
Ajit Khapardef8617e02011-02-11 13:36:37 +00001038 u32 if_id, u32 *pmac_id, u32 domain);
1039extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1040 u32 pmac_id, u32 domain);
Sathya Perla73d540f2009-10-14 20:20:42 +00001041extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1042 u32 en_flags, u8 *mac, bool pmac_invalid,
Sarveshwar Bandiba343c72010-03-31 02:56:12 +00001043 u32 *if_handle, u32 *pmac_id, u32 domain);
Ajit Khaparde658681f2011-02-11 13:34:46 +00001044extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1045 u32 domain);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001046extern int be_cmd_eq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001047 struct be_queue_info *eq, int eq_delay);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001048extern int be_cmd_cq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001049 struct be_queue_info *cq, struct be_queue_info *eq,
1050 bool sol_evts, bool no_delay,
1051 int num_cqe_dma_coalesce);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001052extern int be_cmd_mccq_create(struct be_adapter *adapter,
Sathya Perla5fb379e2009-06-18 00:02:59 +00001053 struct be_queue_info *mccq,
1054 struct be_queue_info *cq);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001055extern int be_cmd_txq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001056 struct be_queue_info *txq,
1057 struct be_queue_info *cq);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001058extern int be_cmd_rxq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001059 struct be_queue_info *rxq, u16 cq_id,
1060 u16 frag_size, u16 max_frame_size, u32 if_id,
Sathya Perla3abcded2010-10-03 22:12:27 -07001061 u32 rss, u8 *rss_id);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001062extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001063 int type);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001064extern int be_cmd_link_status_query(struct be_adapter *adapter,
Sarveshwar Bandi0388f252009-10-28 04:15:20 -07001065 bool *link_up, u8 *mac_speed, u16 *link_speed);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001066extern int be_cmd_reset(struct be_adapter *adapter);
1067extern int be_cmd_get_stats(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001068 struct be_dma_mem *nonemb_cmd);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001069extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001070
Sathya Perla8788fdc2009-07-27 22:52:03 +00001071extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1072extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001073 u16 *vtag_array, u32 num, bool untagged,
1074 bool promiscuous);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001075extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001076 u8 port_num, bool en);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001077extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
Jiri Pirko0ddf4772010-02-20 00:13:58 +00001078 struct net_device *netdev, struct be_dma_mem *mem);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001079extern int be_cmd_set_flow_control(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001080 u32 tx_fc, u32 rx_fc);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001081extern int be_cmd_get_flow_control(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001082 u32 *tx_fc, u32 *rx_fc);
Ajit Khapardedcb9b562009-09-30 21:58:22 -07001083extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
Sathya Perla3abcded2010-10-03 22:12:27 -07001084 u32 *port_num, u32 *function_mode, u32 *function_caps);
sarveshwarb14074ea2009-08-05 13:05:24 -07001085extern int be_cmd_reset_function(struct be_adapter *adapter);
Sathya Perla3abcded2010-10-03 22:12:27 -07001086extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1087 u16 table_size);
Sathya Perlaf31e50a2010-03-02 03:56:39 -08001088extern int be_process_mcc(struct be_adapter *adapter, int *status);
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001089extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1090 u8 port_num, u8 beacon, u8 status, u8 state);
1091extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1092 u8 port_num, u32 *state);
Ajit Khaparde84517482009-09-04 03:12:16 +00001093extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1094 struct be_dma_mem *cmd, u32 flash_oper,
1095 u32 flash_opcode, u32 buf_size);
Ajit Khaparde3f0d4562010-02-09 01:30:35 +00001096int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1097 int offset);
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001098extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1099 struct be_dma_mem *nonemb_cmd);
Sathya Perla2243e2e2009-11-22 22:02:03 +00001100extern int be_cmd_fw_init(struct be_adapter *adapter);
1101extern int be_cmd_fw_clean(struct be_adapter *adapter);
Sathya Perla7a1e9b22010-02-17 01:35:11 +00001102extern void be_async_mcc_enable(struct be_adapter *adapter);
1103extern void be_async_mcc_disable(struct be_adapter *adapter);
Suresh Rff33a6e2009-12-03 16:15:52 -08001104extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1105 u32 loopback_type, u32 pkt_size,
1106 u32 num_pkts, u64 pattern);
1107extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1108 u32 byte_cnt, struct be_dma_mem *cmd);
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08001109extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1110 struct be_dma_mem *nonemb_cmd);
Sarveshwar Bandifced9992009-12-23 04:41:44 +00001111extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1112 u8 loopback_type, u8 enable);
Ajit Khapardeee3cb622010-07-01 03:51:00 +00001113extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1114 struct be_dma_mem *cmd);
Ajit Khapardee1d18732010-07-23 01:52:13 +00001115extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
Ajit Khaparded053de92010-09-03 06:23:30 +00001116extern void be_detect_dump_ue(struct be_adapter *adapter);
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001117extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
David S. Millerd4a66e72010-01-10 22:55:03 -08001118