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review.evervolv.com / android_kernel_oneplus_msm8996 / 64a6bd6a570c53f1955eaedf3952dcbe9b62da1d / . / drivers / video / via / share.h
blob: 7f0de7f006ad65e1b317e759f15d3ad155a9bef3 [file] [log] [blame]
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __SHARE_H__
23#define __SHARE_H__
24
25/* Define Return Value */
26#define FAIL -1
27#define OK 1
28
29#ifndef NULL
30#define NULL 0
31#endif
32
33/* Define Bit Field */
34#define BIT0 0x01
35#define BIT1 0x02
36#define BIT2 0x04
37#define BIT3 0x08
38#define BIT4 0x10
39#define BIT5 0x20
40#define BIT6 0x40
41#define BIT7 0x80
42
43/* Video Memory Size */
44#define VIDEO_MEMORY_SIZE_16M 0x1000000
45
Jonathan Corbet64a6bd62010-05-05 13:42:49 -0600[diff] [blame^]46/*
47 * Lengths of the VPIT structure arrays.
48 */
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]49#define StdCR 0x19
50#define StdSR 0x04
51#define StdGR 0x09
52#define StdAR 0x14
53
54#define PatchCR 11
55
56/* Display path */
57#define IGA1 1
58#define IGA2 2
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]59
60/* Define Color Depth */
61#define MODE_8BPP 1
62#define MODE_16BPP 2
63#define MODE_32BPP 4
64
65#define GR20 0x20
66#define GR21 0x21
67#define GR22 0x22
68
69/* Sequencer Registers */
70#define SR01 0x01
71#define SR10 0x10
72#define SR12 0x12
73#define SR15 0x15
74#define SR16 0x16
75#define SR17 0x17
76#define SR18 0x18
77#define SR1B 0x1B
78#define SR1A 0x1A
79#define SR1C 0x1C
80#define SR1D 0x1D
81#define SR1E 0x1E
82#define SR1F 0x1F
83#define SR20 0x20
84#define SR21 0x21
85#define SR22 0x22
86#define SR2A 0x2A
87#define SR2D 0x2D
88#define SR2E 0x2E
89
90#define SR30 0x30
91#define SR39 0x39
92#define SR3D 0x3D
93#define SR3E 0x3E
94#define SR3F 0x3F
95#define SR40 0x40
96#define SR43 0x43
97#define SR44 0x44
98#define SR45 0x45
99#define SR46 0x46
100#define SR47 0x47
101#define SR48 0x48
102#define SR49 0x49
103#define SR4A 0x4A
104#define SR4B 0x4B
105#define SR4C 0x4C
106#define SR52 0x52
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]107#define SR57 0x57
108#define SR58 0x58
109#define SR59 0x59
110#define SR5D 0x5D
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]111#define SR5E 0x5E
112#define SR65 0x65
113
114/* CRT Controller Registers */
115#define CR00 0x00
116#define CR01 0x01
117#define CR02 0x02
118#define CR03 0x03
119#define CR04 0x04
120#define CR05 0x05
121#define CR06 0x06
122#define CR07 0x07
123#define CR08 0x08
124#define CR09 0x09
125#define CR0A 0x0A
126#define CR0B 0x0B
127#define CR0C 0x0C
128#define CR0D 0x0D
129#define CR0E 0x0E
130#define CR0F 0x0F
131#define CR10 0x10
132#define CR11 0x11
133#define CR12 0x12
134#define CR13 0x13
135#define CR14 0x14
136#define CR15 0x15
137#define CR16 0x16
138#define CR17 0x17
139#define CR18 0x18
140
141/* Extend CRT Controller Registers */
142#define CR30 0x30
143#define CR31 0x31
144#define CR32 0x32
145#define CR33 0x33
146#define CR34 0x34
147#define CR35 0x35
148#define CR36 0x36
149#define CR37 0x37
150#define CR38 0x38
151#define CR39 0x39
152#define CR3A 0x3A
153#define CR3B 0x3B
154#define CR3C 0x3C
155#define CR3D 0x3D
156#define CR3E 0x3E
157#define CR3F 0x3F
158#define CR40 0x40
159#define CR41 0x41
160#define CR42 0x42
161#define CR43 0x43
162#define CR44 0x44
163#define CR45 0x45
164#define CR46 0x46
165#define CR47 0x47
166#define CR48 0x48
167#define CR49 0x49
168#define CR4A 0x4A
169#define CR4B 0x4B
170#define CR4C 0x4C
171#define CR4D 0x4D
172#define CR4E 0x4E
173#define CR4F 0x4F
174#define CR50 0x50
175#define CR51 0x51
176#define CR52 0x52
177#define CR53 0x53
178#define CR54 0x54
179#define CR55 0x55
180#define CR56 0x56
181#define CR57 0x57
182#define CR58 0x58
183#define CR59 0x59
184#define CR5A 0x5A
185#define CR5B 0x5B
186#define CR5C 0x5C
187#define CR5D 0x5D
188#define CR5E 0x5E
189#define CR5F 0x5F
190#define CR60 0x60
191#define CR61 0x61
192#define CR62 0x62
193#define CR63 0x63
194#define CR64 0x64
195#define CR65 0x65
196#define CR66 0x66
197#define CR67 0x67
198#define CR68 0x68
199#define CR69 0x69
200#define CR6A 0x6A
201#define CR6B 0x6B
202#define CR6C 0x6C
203#define CR6D 0x6D
204#define CR6E 0x6E
205#define CR6F 0x6F
206#define CR70 0x70
207#define CR71 0x71
208#define CR72 0x72
209#define CR73 0x73
210#define CR74 0x74
211#define CR75 0x75
212#define CR76 0x76
213#define CR77 0x77
214#define CR78 0x78
215#define CR79 0x79
216#define CR7A 0x7A
217#define CR7B 0x7B
218#define CR7C 0x7C
219#define CR7D 0x7D
220#define CR7E 0x7E
221#define CR7F 0x7F
222#define CR80 0x80
223#define CR81 0x81
224#define CR82 0x82
225#define CR83 0x83
226#define CR84 0x84
227#define CR85 0x85
228#define CR86 0x86
229#define CR87 0x87
230#define CR88 0x88
231#define CR89 0x89
232#define CR8A 0x8A
233#define CR8B 0x8B
234#define CR8C 0x8C
235#define CR8D 0x8D
236#define CR8E 0x8E
237#define CR8F 0x8F
238#define CR90 0x90
239#define CR91 0x91
240#define CR92 0x92
241#define CR93 0x93
242#define CR94 0x94
243#define CR95 0x95
244#define CR96 0x96
245#define CR97 0x97
246#define CR98 0x98
247#define CR99 0x99
248#define CR9A 0x9A
249#define CR9B 0x9B
250#define CR9C 0x9C
251#define CR9D 0x9D
252#define CR9E 0x9E
253#define CR9F 0x9F
254#define CRA0 0xA0
255#define CRA1 0xA1
256#define CRA2 0xA2
257#define CRA3 0xA3
258#define CRD2 0xD2
259#define CRD3 0xD3
260#define CRD4 0xD4
261
262/* LUT Table*/
263#define LUT_DATA 0x3C9 /* DACDATA */
264#define LUT_INDEX_READ 0x3C7 /* DACRX */
265#define LUT_INDEX_WRITE 0x3C8 /* DACWX */
266#define DACMASK 0x3C6
267
268/* Definition Device */
269#define DEVICE_CRT 0x01
270#define DEVICE_DVI 0x03
271#define DEVICE_LCD 0x04
272
273/* Device output interface */
274#define INTERFACE_NONE 0x00
275#define INTERFACE_ANALOG_RGB 0x01
276#define INTERFACE_DVP0 0x02
277#define INTERFACE_DVP1 0x03
278#define INTERFACE_DFP_HIGH 0x04
279#define INTERFACE_DFP_LOW 0x05
280#define INTERFACE_DFP 0x06
281#define INTERFACE_LVDS0 0x07
282#define INTERFACE_LVDS1 0x08
283#define INTERFACE_LVDS0LVDS1 0x09
284#define INTERFACE_TMDS 0x0A
285
286#define HW_LAYOUT_LCD_ONLY 0x01
287#define HW_LAYOUT_DVI_ONLY 0x02
288#define HW_LAYOUT_LCD_DVI 0x03
289#define HW_LAYOUT_LCD1_LCD2 0x04
290#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
291
292/* Definition Refresh Rate */
293#define REFRESH_50 50
294#define REFRESH_60 60
295#define REFRESH_75 75
296#define REFRESH_85 85
297#define REFRESH_100 100
298#define REFRESH_120 120
299
300/* Definition Sync Polarity*/
301#define NEGATIVE 1
302#define POSITIVE 0
303
304/*480x640@60 Sync Polarity (GTF)
305*/
306#define M480X640_R60_HSP NEGATIVE
307#define M480X640_R60_VSP POSITIVE
308
309/*640x480@60 Sync Polarity (VESA Mode)
310*/
311#define M640X480_R60_HSP NEGATIVE
312#define M640X480_R60_VSP NEGATIVE
313
314/*640x480@75 Sync Polarity (VESA Mode)
315*/
316#define M640X480_R75_HSP NEGATIVE
317#define M640X480_R75_VSP NEGATIVE
318
319/*640x480@85 Sync Polarity (VESA Mode)
320*/
321#define M640X480_R85_HSP NEGATIVE
322#define M640X480_R85_VSP NEGATIVE
323
324/*640x480@100 Sync Polarity (GTF Mode)
325*/
326#define M640X480_R100_HSP NEGATIVE
327#define M640X480_R100_VSP POSITIVE
328
329/*640x480@120 Sync Polarity (GTF Mode)
330*/
331#define M640X480_R120_HSP NEGATIVE
332#define M640X480_R120_VSP POSITIVE
333
334/*720x480@60 Sync Polarity (GTF Mode)
335*/
336#define M720X480_R60_HSP NEGATIVE
337#define M720X480_R60_VSP POSITIVE
338
339/*720x576@60 Sync Polarity (GTF Mode)
340*/
341#define M720X576_R60_HSP NEGATIVE
342#define M720X576_R60_VSP POSITIVE
343
344/*800x600@60 Sync Polarity (VESA Mode)
345*/
346#define M800X600_R60_HSP POSITIVE
347#define M800X600_R60_VSP POSITIVE
348
349/*800x600@75 Sync Polarity (VESA Mode)
350*/
351#define M800X600_R75_HSP POSITIVE
352#define M800X600_R75_VSP POSITIVE
353
354/*800x600@85 Sync Polarity (VESA Mode)
355*/
356#define M800X600_R85_HSP POSITIVE
357#define M800X600_R85_VSP POSITIVE
358
359/*800x600@100 Sync Polarity (GTF Mode)
360*/
361#define M800X600_R100_HSP NEGATIVE
362#define M800X600_R100_VSP POSITIVE
363
364/*800x600@120 Sync Polarity (GTF Mode)
365*/
366#define M800X600_R120_HSP NEGATIVE
367#define M800X600_R120_VSP POSITIVE
368
369/*800x480@60 Sync Polarity (CVT Mode)
370*/
371#define M800X480_R60_HSP NEGATIVE
372#define M800X480_R60_VSP POSITIVE
373
374/*848x480@60 Sync Polarity (CVT Mode)
375*/
376#define M848X480_R60_HSP NEGATIVE
377#define M848X480_R60_VSP POSITIVE
378
379/*852x480@60 Sync Polarity (GTF Mode)
380*/
381#define M852X480_R60_HSP NEGATIVE
382#define M852X480_R60_VSP POSITIVE
383
384/*1024x512@60 Sync Polarity (GTF Mode)
385*/
386#define M1024X512_R60_HSP NEGATIVE
387#define M1024X512_R60_VSP POSITIVE
388
389/*1024x600@60 Sync Polarity (GTF Mode)
390*/
391#define M1024X600_R60_HSP NEGATIVE
392#define M1024X600_R60_VSP POSITIVE
393
394/*1024x768@60 Sync Polarity (VESA Mode)
395*/
396#define M1024X768_R60_HSP NEGATIVE
397#define M1024X768_R60_VSP NEGATIVE
398
399/*1024x768@75 Sync Polarity (VESA Mode)
400*/
401#define M1024X768_R75_HSP POSITIVE
402#define M1024X768_R75_VSP POSITIVE
403
404/*1024x768@85 Sync Polarity (VESA Mode)
405*/
406#define M1024X768_R85_HSP POSITIVE
407#define M1024X768_R85_VSP POSITIVE
408
409/*1024x768@100 Sync Polarity (GTF Mode)
410*/
411#define M1024X768_R100_HSP NEGATIVE
412#define M1024X768_R100_VSP POSITIVE
413
414/*1152x864@75 Sync Polarity (VESA Mode)
415*/
416#define M1152X864_R75_HSP POSITIVE
417#define M1152X864_R75_VSP POSITIVE
418
419/*1280x720@60 Sync Polarity (GTF Mode)
420*/
421#define M1280X720_R60_HSP NEGATIVE
422#define M1280X720_R60_VSP POSITIVE
423
424/* 1280x768@50 Sync Polarity (GTF Mode) */
425#define M1280X768_R50_HSP NEGATIVE
426#define M1280X768_R50_VSP POSITIVE
427
428/*1280x768@60 Sync Polarity (GTF Mode)
429*/
430#define M1280X768_R60_HSP NEGATIVE
431#define M1280X768_R60_VSP POSITIVE
432
433/*1280x800@60 Sync Polarity (CVT Mode)
434*/
435#define M1280X800_R60_HSP NEGATIVE
436#define M1280X800_R60_VSP POSITIVE
437
438/*1280x960@60 Sync Polarity (VESA Mode)
439*/
440#define M1280X960_R60_HSP POSITIVE
441#define M1280X960_R60_VSP POSITIVE
442
443/*1280x1024@60 Sync Polarity (VESA Mode)
444*/
445#define M1280X1024_R60_HSP POSITIVE
446#define M1280X1024_R60_VSP POSITIVE
447
448/* 1360x768@60 Sync Polarity (CVT Mode) */
449#define M1360X768_R60_HSP POSITIVE
450#define M1360X768_R60_VSP POSITIVE
451
452/* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
453#define M1360X768_RB_R60_HSP POSITIVE
454#define M1360X768_RB_R60_VSP NEGATIVE
455
456/* 1368x768@50 Sync Polarity (GTF Mode) */
457#define M1368X768_R50_HSP NEGATIVE
458#define M1368X768_R50_VSP POSITIVE
459
460/* 1368x768@60 Sync Polarity (VESA Mode) */
461#define M1368X768_R60_HSP NEGATIVE
462#define M1368X768_R60_VSP POSITIVE
463
464/*1280x1024@75 Sync Polarity (VESA Mode)
465*/
466#define M1280X1024_R75_HSP POSITIVE
467#define M1280X1024_R75_VSP POSITIVE
468
469/*1280x1024@85 Sync Polarity (VESA Mode)
470*/
471#define M1280X1024_R85_HSP POSITIVE
472#define M1280X1024_R85_VSP POSITIVE
473
474/*1440x1050@60 Sync Polarity (GTF Mode)
475*/
476#define M1440X1050_R60_HSP NEGATIVE
477#define M1440X1050_R60_VSP POSITIVE
478
479/*1600x1200@60 Sync Polarity (VESA Mode)
480*/
481#define M1600X1200_R60_HSP POSITIVE
482#define M1600X1200_R60_VSP POSITIVE
483
484/*1600x1200@75 Sync Polarity (VESA Mode)
485*/
486#define M1600X1200_R75_HSP POSITIVE
487#define M1600X1200_R75_VSP POSITIVE
488
489/* 1680x1050@60 Sync Polarity (CVT Mode) */
490#define M1680x1050_R60_HSP NEGATIVE
491#define M1680x1050_R60_VSP NEGATIVE
492
493/* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
494#define M1680x1050_RB_R60_HSP POSITIVE
495#define M1680x1050_RB_R60_VSP NEGATIVE
496
497/* 1680x1050@75 Sync Polarity (CVT Mode) */
498#define M1680x1050_R75_HSP NEGATIVE
499#define M1680x1050_R75_VSP POSITIVE
500
501/*1920x1080@60 Sync Polarity (CVT Mode)
502*/
503#define M1920X1080_R60_HSP NEGATIVE
504#define M1920X1080_R60_VSP POSITIVE
505
506/* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
507#define M1920X1080_RB_R60_HSP POSITIVE
508#define M1920X1080_RB_R60_VSP NEGATIVE
509
510/*1920x1440@60 Sync Polarity (VESA Mode)
511*/
512#define M1920X1440_R60_HSP NEGATIVE
513#define M1920X1440_R60_VSP POSITIVE
514
515/*1920x1440@75 Sync Polarity (VESA Mode)
516*/
517#define M1920X1440_R75_HSP NEGATIVE
518#define M1920X1440_R75_VSP POSITIVE
519
520#if 0
521/* 1400x1050@60 Sync Polarity (VESA Mode) */
522#define M1400X1050_R60_HSP NEGATIVE
523#define M1400X1050_R60_VSP NEGATIVE
524#endif
525
526/* 1400x1050@60 Sync Polarity (CVT Mode) */
527#define M1400X1050_R60_HSP NEGATIVE
528#define M1400X1050_R60_VSP POSITIVE
529
530/* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
531#define M1400X1050_RB_R60_HSP POSITIVE
532#define M1400X1050_RB_R60_VSP NEGATIVE
533
534/* 1400x1050@75 Sync Polarity (CVT Mode) */
535#define M1400X1050_R75_HSP NEGATIVE
536#define M1400X1050_R75_VSP POSITIVE
537
538/* 960x600@60 Sync Polarity (CVT Mode) */
539#define M960X600_R60_HSP NEGATIVE
540#define M960X600_R60_VSP POSITIVE
541
542/* 1000x600@60 Sync Polarity (GTF Mode) */
543#define M1000X600_R60_HSP NEGATIVE
544#define M1000X600_R60_VSP POSITIVE
545
546/* 1024x576@60 Sync Polarity (GTF Mode) */
547#define M1024X576_R60_HSP NEGATIVE
548#define M1024X576_R60_VSP POSITIVE
549
550/*1024x600@60 Sync Polarity (GTF Mode)*/
551#define M1024X600_R60_HSP NEGATIVE
552#define M1024X600_R60_VSP POSITIVE
553
554/* 1088x612@60 Sync Polarity (CVT Mode) */
555#define M1088X612_R60_HSP NEGATIVE
556#define M1088X612_R60_VSP POSITIVE
557
558/* 1152x720@60 Sync Polarity (CVT Mode) */
559#define M1152X720_R60_HSP NEGATIVE
560#define M1152X720_R60_VSP POSITIVE
561
562/* 1200x720@60 Sync Polarity (GTF Mode) */
563#define M1200X720_R60_HSP NEGATIVE
564#define M1200X720_R60_VSP POSITIVE
565
Chris Ballc205d932009-06-07 13:59:51 -0400[diff] [blame]566/* 1200x900@60 Sync Polarity (DCON) */
567#define M1200X900_R60_HSP NEGATIVE
568#define M1200X900_R60_VSP NEGATIVE
569
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]570/* 1280x600@60 Sync Polarity (GTF Mode) */
571#define M1280x600_R60_HSP NEGATIVE
572#define M1280x600_R60_VSP POSITIVE
573
574/* 1280x720@50 Sync Polarity (GTF Mode) */
575#define M1280X720_R50_HSP NEGATIVE
576#define M1280X720_R50_VSP POSITIVE
577
578/* 1280x720@60 Sync Polarity (CEA Mode) */
579#define M1280X720_CEA_R60_HSP POSITIVE
580#define M1280X720_CEA_R60_VSP POSITIVE
581
582/* 1440x900@60 Sync Polarity (CVT Mode) */
583#define M1440X900_R60_HSP NEGATIVE
584#define M1440X900_R60_VSP POSITIVE
585
586/* 1440x900@75 Sync Polarity (CVT Mode) */
587#define M1440X900_R75_HSP NEGATIVE
588#define M1440X900_R75_VSP POSITIVE
589
590/* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
591#define M1440X900_RB_R60_HSP POSITIVE
592#define M1440X900_RB_R60_VSP NEGATIVE
593
594/* 1600x900@60 Sync Polarity (CVT Mode) */
595#define M1600X900_R60_HSP NEGATIVE
596#define M1600X900_R60_VSP POSITIVE
597
598/* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
599#define M1600X900_RB_R60_HSP POSITIVE
600#define M1600X900_RB_R60_VSP NEGATIVE
601
602/* 1600x1024@60 Sync Polarity (GTF Mode) */
603#define M1600X1024_R60_HSP NEGATIVE
604#define M1600X1024_R60_VSP POSITIVE
605
606/* 1792x1344@60 Sync Polarity (DMT Mode) */
607#define M1792x1344_R60_HSP NEGATIVE
608#define M1792x1344_R60_VSP POSITIVE
609
610/* 1856x1392@60 Sync Polarity (DMT Mode) */
611#define M1856x1392_R60_HSP NEGATIVE
612#define M1856x1392_R60_VSP POSITIVE
613
614/* 1920x1200@60 Sync Polarity (CVT Mode) */
615#define M1920X1200_R60_HSP NEGATIVE
616#define M1920X1200_R60_VSP POSITIVE
617
618/* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
619#define M1920X1200_RB_R60_HSP POSITIVE
620#define M1920X1200_RB_R60_VSP NEGATIVE
621
622/* 1920x1080@60 Sync Polarity (CEA Mode) */
623#define M1920X1080_CEA_R60_HSP POSITIVE
624#define M1920X1080_CEA_R60_VSP POSITIVE
625
626/* 2048x1536@60 Sync Polarity (CVT Mode) */
627#define M2048x1536_R60_HSP NEGATIVE
628#define M2048x1536_R60_VSP POSITIVE
629
630/* define PLL index: */
631#define CLK_25_175M 25175000
632#define CLK_26_880M 26880000
633#define CLK_29_581M 29581000
634#define CLK_31_490M 31490000
635#define CLK_31_500M 31500000
636#define CLK_31_728M 31728000
637#define CLK_32_668M 32688000
638#define CLK_36_000M 36000000
639#define CLK_40_000M 40000000
640#define CLK_41_291M 41291000
641#define CLK_43_163M 43163000
642#define CLK_45_250M 45250000 /* 45.46MHz */
643#define CLK_46_000M 46000000
644#define CLK_46_996M 46996000
645#define CLK_48_000M 48000000
646#define CLK_48_875M 48875000
647#define CLK_49_500M 49500000
648#define CLK_52_406M 52406000
649#define CLK_52_977M 52977000
650#define CLK_56_250M 56250000
Chris Ballc205d932009-06-07 13:59:51 -0400[diff] [blame]651#define CLK_57_275M 57275000
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]652#define CLK_60_466M 60466000
653#define CLK_61_500M 61500000
654#define CLK_65_000M 65000000
655#define CLK_65_178M 65178000
656#define CLK_66_750M 66750000 /* 67.116MHz */
657#define CLK_68_179M 68179000
658#define CLK_69_924M 69924000
659#define CLK_70_159M 70159000
660#define CLK_72_000M 72000000
661#define CLK_74_270M 74270000
662#define CLK_78_750M 78750000
663#define CLK_80_136M 80136000
664#define CLK_83_375M 83375000
665#define CLK_83_950M 83950000
666#define CLK_84_750M 84750000 /* 84.537Mhz */
667#define CLK_85_860M 85860000
668#define CLK_88_750M 88750000
669#define CLK_94_500M 94500000
670#define CLK_97_750M 97750000
671#define CLK_101_000M 101000000
672#define CLK_106_500M 106500000
673#define CLK_108_000M 108000000
674#define CLK_113_309M 113309000
675#define CLK_118_840M 118840000
676#define CLK_119_000M 119000000
677#define CLK_121_750M 121750000 /* 121.704MHz */
678#define CLK_125_104M 125104000
679#define CLK_133_308M 133308000
680#define CLK_135_000M 135000000
681#define CLK_136_700M 136700000
682#define CLK_138_400M 138400000
683#define CLK_146_760M 146760000
684#define CLK_148_500M 148500000
685
686#define CLK_153_920M 153920000
687#define CLK_156_000M 156000000
688#define CLK_157_500M 157500000
689#define CLK_162_000M 162000000
690#define CLK_187_000M 187000000
691#define CLK_193_295M 193295000
692#define CLK_202_500M 202500000
693#define CLK_204_000M 204000000
694#define CLK_218_500M 218500000
695#define CLK_234_000M 234000000
696#define CLK_267_250M 267250000
697#define CLK_297_500M 297500000
698#define CLK_74_481M 74481000
699#define CLK_172_798M 172798000
700#define CLK_122_614M 122614000
701
702/* CLE266 PLL value
703*/
704#define CLE266_PLL_25_175M 0x0000C763
705#define CLE266_PLL_26_880M 0x0000440F
706#define CLE266_PLL_29_581M 0x00008421
707#define CLE266_PLL_31_490M 0x00004721
708#define CLE266_PLL_31_500M 0x0000C3B5
709#define CLE266_PLL_31_728M 0x0000471F
710#define CLE266_PLL_32_668M 0x0000C449
711#define CLE266_PLL_36_000M 0x0000C5E5
712#define CLE266_PLL_40_000M 0x0000C459
713#define CLE266_PLL_41_291M 0x00004417
714#define CLE266_PLL_43_163M 0x0000C579
715#define CLE266_PLL_45_250M 0x0000C57F /* 45.46MHz */
716#define CLE266_PLL_46_000M 0x0000875A
717#define CLE266_PLL_46_996M 0x0000C4E9
718#define CLE266_PLL_48_000M 0x00001443
719#define CLE266_PLL_48_875M 0x00001D63
720#define CLE266_PLL_49_500M 0x00008653
721#define CLE266_PLL_52_406M 0x0000C475
722#define CLE266_PLL_52_977M 0x00004525
723#define CLE266_PLL_56_250M 0x000047B7
724#define CLE266_PLL_60_466M 0x0000494C
725#define CLE266_PLL_61_500M 0x00001456
726#define CLE266_PLL_65_000M 0x000086ED
727#define CLE266_PLL_65_178M 0x0000855B
728#define CLE266_PLL_66_750M 0x0000844B /* 67.116MHz */
729#define CLE266_PLL_68_179M 0x00000413
730#define CLE266_PLL_69_924M 0x00001153
731#define CLE266_PLL_70_159M 0x00001462
732#define CLE266_PLL_72_000M 0x00001879
733#define CLE266_PLL_74_270M 0x00004853
734#define CLE266_PLL_78_750M 0x00004321
735#define CLE266_PLL_80_136M 0x0000051C
736#define CLE266_PLL_83_375M 0x0000C25D
737#define CLE266_PLL_83_950M 0x00000729
738#define CLE266_PLL_84_750M 0x00008576 /* 84.537MHz */
739#define CLE266_PLL_85_860M 0x00004754
740#define CLE266_PLL_88_750M 0x0000051F
741#define CLE266_PLL_94_500M 0x00000521
742#define CLE266_PLL_97_750M 0x00004652
743#define CLE266_PLL_101_000M 0x0000497F
744#define CLE266_PLL_106_500M 0x00008477 /* 106.491463 MHz */
745#define CLE266_PLL_108_000M 0x00008479
746#define CLE266_PLL_113_309M 0x00000C5F
747#define CLE266_PLL_118_840M 0x00004553
748#define CLE266_PLL_119_000M 0x00000D6C
749#define CLE266_PLL_121_750M 0x00004555 /* 121.704MHz */
750#define CLE266_PLL_125_104M 0x000006B5
751#define CLE266_PLL_133_308M 0x0000465F
752#define CLE266_PLL_135_000M 0x0000455E
753#define CLE266_PLL_136_700M 0x00000C73
754#define CLE266_PLL_138_400M 0x00000957
755#define CLE266_PLL_146_760M 0x00004567
756#define CLE266_PLL_148_500M 0x00000853
757#define CLE266_PLL_153_920M 0x00000856
758#define CLE266_PLL_156_000M 0x0000456D
759#define CLE266_PLL_157_500M 0x000005B7
760#define CLE266_PLL_162_000M 0x00004571
761#define CLE266_PLL_187_000M 0x00000976
762#define CLE266_PLL_193_295M 0x0000086C
763#define CLE266_PLL_202_500M 0x00000763
764#define CLE266_PLL_204_000M 0x00000764
765#define CLE266_PLL_218_500M 0x0000065C
766#define CLE266_PLL_234_000M 0x00000662
767#define CLE266_PLL_267_250M 0x00000670
768#define CLE266_PLL_297_500M 0x000005E6
769#define CLE266_PLL_74_481M 0x0000051A
770#define CLE266_PLL_172_798M 0x00004579
771#define CLE266_PLL_122_614M 0x0000073C
772
773/* K800 PLL value
774*/
775#define K800_PLL_25_175M 0x00539001
776#define K800_PLL_26_880M 0x001C8C80
777#define K800_PLL_29_581M 0x00409080
778#define K800_PLL_31_490M 0x006F9001
779#define K800_PLL_31_500M 0x008B9002
780#define K800_PLL_31_728M 0x00AF9003
781#define K800_PLL_32_668M 0x00909002
782#define K800_PLL_36_000M 0x009F9002
783#define K800_PLL_40_000M 0x00578C02
784#define K800_PLL_41_291M 0x00438C01
785#define K800_PLL_43_163M 0x00778C03
786#define K800_PLL_45_250M 0x007D8C83 /* 45.46MHz */
787#define K800_PLL_46_000M 0x00658C02
788#define K800_PLL_46_996M 0x00818C83
789#define K800_PLL_48_000M 0x00848C83
790#define K800_PLL_48_875M 0x00508C81
791#define K800_PLL_49_500M 0x00518C01
792#define K800_PLL_52_406M 0x00738C02
793#define K800_PLL_52_977M 0x00928C83
794#define K800_PLL_56_250M 0x007C8C02
795#define K800_PLL_60_466M 0x00A78C83
796#define K800_PLL_61_500M 0x00AA8C83
797#define K800_PLL_65_000M 0x006B8C01
798#define K800_PLL_65_178M 0x00B48C83
799#define K800_PLL_66_750M 0x00948C82 /* 67.116MHz */
800#define K800_PLL_68_179M 0x00708C01
801#define K800_PLL_69_924M 0x00C18C83
802#define K800_PLL_70_159M 0x00C28C83
803#define K800_PLL_72_000M 0x009F8C82
804#define K800_PLL_74_270M 0x00ce0c03
805#define K800_PLL_78_750M 0x00408801
806#define K800_PLL_80_136M 0x00428801
807#define K800_PLL_83_375M 0x005B0882
808#define K800_PLL_83_950M 0x00738803
809#define K800_PLL_84_750M 0x00748883 /* 84.477MHz */
810#define K800_PLL_85_860M 0x00768883
811#define K800_PLL_88_750M 0x007A8883
812#define K800_PLL_94_500M 0x00828803
813#define K800_PLL_97_750M 0x00878883
814#define K800_PLL_101_000M 0x008B8883
815#define K800_PLL_106_500M 0x00758882 /* 106.491463 MHz */
816#define K800_PLL_108_000M 0x00778882
817#define K800_PLL_113_309M 0x005D8881
818#define K800_PLL_118_840M 0x00A48883
819#define K800_PLL_119_000M 0x00838882
820#define K800_PLL_121_750M 0x00A88883 /* 121.704MHz */
821#define K800_PLL_125_104M 0x00688801
822#define K800_PLL_133_308M 0x005D8801
823#define K800_PLL_135_000M 0x001A4081
824#define K800_PLL_136_700M 0x00BD8883
825#define K800_PLL_138_400M 0x00728881
826#define K800_PLL_146_760M 0x00CC8883
827#define K800_PLL_148_500M 0x00ce0803
828#define K800_PLL_153_920M 0x00548482
829#define K800_PLL_156_000M 0x006B8483
830#define K800_PLL_157_500M 0x00142080
831#define K800_PLL_162_000M 0x006F8483
832#define K800_PLL_187_000M 0x00818483
833#define K800_PLL_193_295M 0x004F8481
834#define K800_PLL_202_500M 0x00538481
835#define K800_PLL_204_000M 0x008D8483
836#define K800_PLL_218_500M 0x00978483
837#define K800_PLL_234_000M 0x00608401
838#define K800_PLL_267_250M 0x006E8481
839#define K800_PLL_297_500M 0x00A48402
840#define K800_PLL_74_481M 0x007B8C81
841#define K800_PLL_172_798M 0x00778483
842#define K800_PLL_122_614M 0x00878882
843
844/* PLL for VT3324 */
845#define CX700_25_175M 0x008B1003
846#define CX700_26_719M 0x00931003
847#define CX700_26_880M 0x00941003
848#define CX700_29_581M 0x00A49003
849#define CX700_31_490M 0x00AE1003
850#define CX700_31_500M 0x00AE1003
851#define CX700_31_728M 0x00AF1003
852#define CX700_32_668M 0x00B51003
853#define CX700_36_000M 0x00C81003
854#define CX700_40_000M 0x006E0C03
855#define CX700_41_291M 0x00710C03
856#define CX700_43_163M 0x00770C03
857#define CX700_45_250M 0x007D0C03 /* 45.46MHz */
858#define CX700_46_000M 0x007F0C03
859#define CX700_46_996M 0x00818C83
860#define CX700_48_000M 0x00840C03
861#define CX700_48_875M 0x00508C81
862#define CX700_49_500M 0x00880C03
863#define CX700_52_406M 0x00730C02
864#define CX700_52_977M 0x00920C03
865#define CX700_56_250M 0x009B0C03
866#define CX700_60_466M 0x00460C00
867#define CX700_61_500M 0x00AA0C03
868#define CX700_65_000M 0x006B0C01
869#define CX700_65_178M 0x006B0C01
870#define CX700_66_750M 0x00940C02 /*67.116MHz */
871#define CX700_68_179M 0x00BC0C03
872#define CX700_69_924M 0x00C10C03
873#define CX700_70_159M 0x00C20C03
874#define CX700_72_000M 0x009F0C02
875#define CX700_74_270M 0x00CE0C03
876#define CX700_74_481M 0x00CE0C03
877#define CX700_78_750M 0x006C0803
878#define CX700_80_136M 0x006E0803
879#define CX700_83_375M 0x005B0882
880#define CX700_83_950M 0x00730803
881#define CX700_84_750M 0x00740803 /* 84.537Mhz */
882#define CX700_85_860M 0x00760803
883#define CX700_88_750M 0x00AC8885
884#define CX700_94_500M 0x00820803
885#define CX700_97_750M 0x00870803
886#define CX700_101_000M 0x008B0803
887#define CX700_106_500M 0x00750802
888#define CX700_108_000M 0x00950803
889#define CX700_113_309M 0x005D0801
890#define CX700_118_840M 0x00A40803
891#define CX700_119_000M 0x00830802
892#define CX700_121_750M 0x00420800 /* 121.704MHz */
893#define CX700_125_104M 0x00AD0803
894#define CX700_133_308M 0x00930802
895#define CX700_135_000M 0x00950802
896#define CX700_136_700M 0x00BD0803
897#define CX700_138_400M 0x00720801
898#define CX700_146_760M 0x00CC0803
899#define CX700_148_500M 0x00a40802
900#define CX700_153_920M 0x00540402
901#define CX700_156_000M 0x006B0403
902#define CX700_157_500M 0x006C0403
903#define CX700_162_000M 0x006F0403
904#define CX700_172_798M 0x00770403
905#define CX700_187_000M 0x00810403
906#define CX700_193_295M 0x00850403
907#define CX700_202_500M 0x008C0403
908#define CX700_204_000M 0x008D0403
909#define CX700_218_500M 0x00970403
910#define CX700_234_000M 0x00600401
911#define CX700_267_250M 0x00B90403
912#define CX700_297_500M 0x00CE0403
913#define CX700_122_614M 0x00870802
914
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]915/* PLL for VX855 */
916#define VX855_22_000M 0x007B1005
917#define VX855_25_175M 0x008D1005
918#define VX855_26_719M 0x00961005
919#define VX855_26_880M 0x00961005
920#define VX855_27_000M 0x00971005
921#define VX855_29_581M 0x00A51005
922#define VX855_29_829M 0x00641003
923#define VX855_31_490M 0x00B01005
924#define VX855_31_500M 0x00B01005
925#define VX855_31_728M 0x008E1004
926#define VX855_32_668M 0x00921004
927#define VX855_36_000M 0x00A11004
928#define VX855_40_000M 0x00700C05
929#define VX855_41_291M 0x00730C05
930#define VX855_43_163M 0x00790C05
931#define VX855_45_250M 0x007F0C05 /* 45.46MHz */
932#define VX855_46_000M 0x00670C04
933#define VX855_46_996M 0x00690C04
934#define VX855_48_000M 0x00860C05
935#define VX855_48_875M 0x00890C05
936#define VX855_49_500M 0x00530C03
937#define VX855_52_406M 0x00580C03
938#define VX855_52_977M 0x00940C05
939#define VX855_56_250M 0x009D0C05
Chris Ballc205d932009-06-07 13:59:51 -0400[diff] [blame]940#define VX855_57_275M 0x009D8C85 /* Used by XO panel */
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]941#define VX855_60_466M 0x00A90C05
942#define VX855_61_500M 0x00AC0C05
943#define VX855_65_000M 0x006D0C03
944#define VX855_65_178M 0x00B60C05
945#define VX855_66_750M 0x00700C03 /*67.116MHz */
946#define VX855_67_295M 0x00BC0C05
947#define VX855_68_179M 0x00BF0C05
948#define VX855_68_369M 0x00BF0C05
949#define VX855_69_924M 0x00C30C05
950#define VX855_70_159M 0x00C30C05
951#define VX855_72_000M 0x00A10C04
952#define VX855_73_023M 0x00CC0C05
953#define VX855_74_481M 0x00D10C05
954#define VX855_78_750M 0x006E0805
955#define VX855_79_466M 0x006F0805
956#define VX855_80_136M 0x00700805
957#define VX855_81_627M 0x00720805
958#define VX855_83_375M 0x00750805
959#define VX855_83_527M 0x00750805
960#define VX855_83_950M 0x00750805
961#define VX855_84_537M 0x00760805
962#define VX855_84_750M 0x00760805 /* 84.537Mhz */
963#define VX855_85_500M 0x00760805 /* 85.909080 MHz*/
964#define VX855_85_860M 0x00760805
965#define VX855_85_909M 0x00760805
966#define VX855_88_750M 0x007C0805
967#define VX855_89_489M 0x007D0805
968#define VX855_94_500M 0x00840805
969#define VX855_96_648M 0x00870805
970#define VX855_97_750M 0x00890805
971#define VX855_101_000M 0x008D0805
972#define VX855_106_500M 0x00950805
973#define VX855_108_000M 0x00970805
974#define VX855_110_125M 0x00990805
975#define VX855_112_000M 0x009D0805
976#define VX855_113_309M 0x009F0805
977#define VX855_115_000M 0x00A10805
978#define VX855_118_840M 0x00A60805
979#define VX855_119_000M 0x00A70805
980#define VX855_121_750M 0x00AA0805 /* 121.704MHz */
981#define VX855_122_614M 0x00AC0805
982#define VX855_126_266M 0x00B10805
983#define VX855_130_250M 0x00B60805 /* 130.250 */
984#define VX855_135_000M 0x00BD0805
985#define VX855_136_700M 0x00BF0805
986#define VX855_137_750M 0x00C10805
987#define VX855_138_400M 0x00C20805
988#define VX855_144_300M 0x00CA0805
989#define VX855_146_760M 0x00CE0805
990#define VX855_148_500M 0x00D00805
991#define VX855_153_920M 0x00540402
992#define VX855_156_000M 0x006C0405
993#define VX855_156_867M 0x006E0405
994#define VX855_157_500M 0x006E0405
995#define VX855_162_000M 0x00710405
996#define VX855_172_798M 0x00790405
997#define VX855_187_000M 0x00830405
998#define VX855_193_295M 0x00870405
999#define VX855_202_500M 0x008E0405
1000#define VX855_204_000M 0x008F0405
1001#define VX855_218_500M 0x00990405
1002#define VX855_229_500M 0x00A10405
1003#define VX855_234_000M 0x00A40405
1004#define VX855_267_250M 0x00BB0405
1005#define VX855_297_500M 0x00D00405
1006#define VX855_339_500M 0x00770005
1007#define VX855_340_772M 0x00770005
1008
1009
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]1010/* Definition CRTC Timing Index */
1011#define H_TOTAL_INDEX 0
1012#define H_ADDR_INDEX 1
1013#define H_BLANK_START_INDEX 2
1014#define H_BLANK_END_INDEX 3
1015#define H_SYNC_START_INDEX 4
1016#define H_SYNC_END_INDEX 5
1017#define V_TOTAL_INDEX 6
1018#define V_ADDR_INDEX 7
1019#define V_BLANK_START_INDEX 8
1020#define V_BLANK_END_INDEX 9
1021#define V_SYNC_START_INDEX 10
1022#define V_SYNC_END_INDEX 11
1023#define H_TOTAL_SHADOW_INDEX 12
1024#define H_BLANK_END_SHADOW_INDEX 13
1025#define V_TOTAL_SHADOW_INDEX 14
1026#define V_ADDR_SHADOW_INDEX 15
1027#define V_BLANK_SATRT_SHADOW_INDEX 16
1028#define V_BLANK_END_SHADOW_INDEX 17
1029#define V_SYNC_SATRT_SHADOW_INDEX 18
1030#define V_SYNC_END_SHADOW_INDEX 19
1031
1032/* Definition Video Mode Pixel Clock (picoseconds)
1033*/
1034#define RES_480X640_60HZ_PIXCLOCK 39722
1035#define RES_640X480_60HZ_PIXCLOCK 39722
1036#define RES_640X480_75HZ_PIXCLOCK 31747
1037#define RES_640X480_85HZ_PIXCLOCK 27777
1038#define RES_640X480_100HZ_PIXCLOCK 23168
1039#define RES_640X480_120HZ_PIXCLOCK 19081
1040#define RES_720X480_60HZ_PIXCLOCK 37020
1041#define RES_720X576_60HZ_PIXCLOCK 30611
1042#define RES_800X600_60HZ_PIXCLOCK 25000
1043#define RES_800X600_75HZ_PIXCLOCK 20203
1044#define RES_800X600_85HZ_PIXCLOCK 17777
1045#define RES_800X600_100HZ_PIXCLOCK 14667
1046#define RES_800X600_120HZ_PIXCLOCK 11912
1047#define RES_800X480_60HZ_PIXCLOCK 33805
1048#define RES_848X480_60HZ_PIXCLOCK 31756
1049#define RES_856X480_60HZ_PIXCLOCK 31518
1050#define RES_1024X512_60HZ_PIXCLOCK 24218
1051#define RES_1024X600_60HZ_PIXCLOCK 20460
1052#define RES_1024X768_60HZ_PIXCLOCK 15385
1053#define RES_1024X768_75HZ_PIXCLOCK 12699
1054#define RES_1024X768_85HZ_PIXCLOCK 10582
1055#define RES_1024X768_100HZ_PIXCLOCK 8825
1056#define RES_1152X864_75HZ_PIXCLOCK 9259
1057#define RES_1280X768_60HZ_PIXCLOCK 12480
1058#define RES_1280X800_60HZ_PIXCLOCK 11994
1059#define RES_1280X960_60HZ_PIXCLOCK 9259
1060#define RES_1280X1024_60HZ_PIXCLOCK 9260
1061#define RES_1280X1024_75HZ_PIXCLOCK 7408
1062#define RES_1280X768_85HZ_PIXCLOCK 6349
1063#define RES_1440X1050_60HZ_PIXCLOCK 7993
1064#define RES_1600X1200_60HZ_PIXCLOCK 6172
1065#define RES_1600X1200_75HZ_PIXCLOCK 4938
1066#define RES_1280X720_60HZ_PIXCLOCK 13426
Chris Ballc205d932009-06-07 13:59:51 -0400[diff] [blame]1067#define RES_1200X900_60HZ_PIXCLOCK 17459
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]1068#define RES_1920X1080_60HZ_PIXCLOCK 5787
1069#define RES_1400X1050_60HZ_PIXCLOCK 8214
1070#define RES_1400X1050_75HZ_PIXCLOCK 6410
1071#define RES_1368X768_60HZ_PIXCLOCK 11647
1072#define RES_960X600_60HZ_PIXCLOCK 22099
1073#define RES_1000X600_60HZ_PIXCLOCK 20834
1074#define RES_1024X576_60HZ_PIXCLOCK 21278
1075#define RES_1088X612_60HZ_PIXCLOCK 18877
1076#define RES_1152X720_60HZ_PIXCLOCK 14981
1077#define RES_1200X720_60HZ_PIXCLOCK 14253
1078#define RES_1280X600_60HZ_PIXCLOCK 16260
1079#define RES_1280X720_50HZ_PIXCLOCK 16538
1080#define RES_1280X768_50HZ_PIXCLOCK 15342
1081#define RES_1366X768_50HZ_PIXCLOCK 14301
1082#define RES_1366X768_60HZ_PIXCLOCK 11646
1083#define RES_1360X768_60HZ_PIXCLOCK 11799
1084#define RES_1440X900_60HZ_PIXCLOCK 9390
1085#define RES_1440X900_75HZ_PIXCLOCK 7315
1086#define RES_1600X900_60HZ_PIXCLOCK 8415
1087#define RES_1600X1024_60HZ_PIXCLOCK 7315
1088#define RES_1680X1050_60HZ_PIXCLOCK 6814
1089#define RES_1680X1050_75HZ_PIXCLOCK 5348
1090#define RES_1792X1344_60HZ_PIXCLOCK 4902
1091#define RES_1856X1392_60HZ_PIXCLOCK 4577
1092#define RES_1920X1200_60HZ_PIXCLOCK 5173
1093#define RES_1920X1440_60HZ_PIXCLOCK 4274
1094#define RES_1920X1440_75HZ_PIXCLOCK 3367
1095#define RES_2048X1536_60HZ_PIXCLOCK 3742
1096
1097#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
1098#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
1099#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
1100#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
1101#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
1102#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
1103#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
1104
1105/* LCD display method
1106*/
1107#define LCD_EXPANDSION 0x00
1108#define LCD_CENTERING 0x01
1109
1110/* LCD mode
1111*/
1112#define LCD_OPENLDI 0x00
1113#define LCD_SPWG 0x01
1114
1115/* Define display timing
1116*/
1117struct display_timing {
1118 u16 hor_total;
1119 u16 hor_addr;
1120 u16 hor_blank_start;
1121 u16 hor_blank_end;
1122 u16 hor_sync_start;
1123 u16 hor_sync_end;
1124 u16 ver_total;
1125 u16 ver_addr;
1126 u16 ver_blank_start;
1127 u16 ver_blank_end;
1128 u16 ver_sync_start;
1129 u16 ver_sync_end;
1130};
1131
1132struct crt_mode_table {
1133 int refresh_rate;
1134 unsigned long clk;
1135 int h_sync_polarity;
1136 int v_sync_polarity;
1137 struct display_timing crtc;
1138};
1139
1140struct io_reg {
1141 int port;
1142 u8 index;
1143 u8 mask;
1144 u8 value;
1145};
1146
1147#endif /* __SHARE_H__ */