blob: b2ae730c7c3293b6b03efe98e61da7d85d864a82 [file] [log] [blame]
Heiko Schocher33085b32012-08-30 14:21:04 +05301/*
2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10/include/ "skeleton.dtsi"
11
12/ {
13 arm {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17 intc: interrupt-controller {
18 compatible = "ti,cp-intc";
19 interrupt-controller;
20 #interrupt-cells = <1>;
21 ti,intc-size = <100>;
22 reg = <0xfffee000 0x2000>;
23 };
24 };
25 soc {
26 compatible = "simple-bus";
27 model = "da850";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges = <0x0 0x01c00000 0x400000>;
Lad, Prabhakarc57ff582013-01-25 16:48:44 +053031 interrupt-parent = <&intc>;
Heiko Schocher33085b32012-08-30 14:21:04 +053032
Kumar, Anil1faaba32013-01-16 14:37:39 +053033 pmx_core: pinmux@1c14120 {
34 compatible = "pinctrl-single";
35 reg = <0x14120 0x50>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 pinctrl-single,bit-per-mux;
39 pinctrl-single,register-width = <32>;
40 pinctrl-single,function-mask = <0xffffffff>;
41 status = "disabled";
Kumar, Anil99b88002013-01-16 14:37:41 +053042
43 nand_cs3_pins: pinmux_nand_pins {
44 pinctrl-single,bits = <
45 /* EMA_OE, EMA_WE */
46 0x1c 0x00110000 0x00ff0000
47 /* EMA_CS[4],EMA_CS[3]*/
48 0x1c 0x00000110 0x00000ff0
49 /*
50 * EMA_D[0], EMA_D[1], EMA_D[2],
51 * EMA_D[3], EMA_D[4], EMA_D[5],
52 * EMA_D[6], EMA_D[7]
53 */
54 0x24 0x11111111 0xffffffff
55 /* EMA_A[1], EMA_A[2] */
56 0x30 0x01100000 0x0ff00000
57 >;
58 };
Vishwanathrao Badarkhe, Manish01729cc2013-02-06 15:06:22 +053059 i2c0_pins: pinmux_i2c0_pins {
60 pinctrl-single,bits = <
61 /* I2C0_SDA,I2C0_SCL */
62 0x10 0x00002200 0x0000ff00
63 >;
64 };
Manjunathappa, Prakash88df4122013-03-28 18:42:01 +053065 mmc0_pins: pinmux_mmc_pins {
66 pinctrl-single,bits = <
67 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
68 * MMCSD0_DAT[1] MMCSD0_DAT[0]
69 * MMCSD0_CMD MMCSD0_CLK
70 */
71 0x28 0x00222222 0x00ffffff
72 >;
73 };
Philip Avinash64fa59c2013-04-10 17:42:41 +053074 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
75 pinctrl-single,bits = <
76 /* EPWM0A */
77 0xc 0x00000002 0x0000000f
78 >;
79 };
80 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
81 pinctrl-single,bits = <
82 /* EPWM0B */
83 0xc 0x00000020 0x000000f0
84 >;
85 };
86 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
87 pinctrl-single,bits = <
88 /* EPWM1A */
89 0x14 0x00000002 0x0000000f
90 >;
91 };
92 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
93 pinctrl-single,bits = <
94 /* EPWM1B */
95 0x14 0x00000020 0x000000f0
96 >;
97 };
98 ecap0_pins: pinmux_ecap0_pins {
99 pinctrl-single,bits = <
100 /* ECAP0_APWM0 */
101 0x8 0x20000000 0xf0000000
102 >;
103 };
104 ecap1_pins: pinmux_ecap1_pins {
105 pinctrl-single,bits = <
106 /* ECAP1_APWM1 */
107 0x4 0x40000000 0xf0000000
108 >;
109 };
110 ecap2_pins: pinmux_ecap2_pins {
111 pinctrl-single,bits = <
112 /* ECAP2_APWM2 */
113 0x4 0x00000004 0x0000000f
114 >;
115 };
116
Kumar, Anil1faaba32013-01-16 14:37:39 +0530117 };
Heiko Schocher33085b32012-08-30 14:21:04 +0530118 serial0: serial@1c42000 {
119 compatible = "ns16550a";
120 reg = <0x42000 0x100>;
121 clock-frequency = <150000000>;
122 reg-shift = <2>;
123 interrupts = <25>;
Heiko Schocher33085b32012-08-30 14:21:04 +0530124 status = "disabled";
125 };
126 serial1: serial@1d0c000 {
127 compatible = "ns16550a";
128 reg = <0x10c000 0x100>;
129 clock-frequency = <150000000>;
130 reg-shift = <2>;
131 interrupts = <53>;
Heiko Schocher33085b32012-08-30 14:21:04 +0530132 status = "disabled";
133 };
134 serial2: serial@1d0d000 {
135 compatible = "ns16550a";
136 reg = <0x10d000 0x100>;
137 clock-frequency = <150000000>;
138 reg-shift = <2>;
139 interrupts = <61>;
Heiko Schocher33085b32012-08-30 14:21:04 +0530140 status = "disabled";
141 };
Mrugesh Katepallewar16616362013-01-28 13:17:48 +0530142 rtc0: rtc@1c23000 {
143 compatible = "ti,da830-rtc";
144 reg = <0x23000 0x1000>;
145 interrupts = <19
146 19>;
147 status = "disabled";
148 };
Vishwanathrao Badarkhe, Manish01729cc2013-02-06 15:06:22 +0530149 i2c0: i2c@1c22000 {
150 compatible = "ti,davinci-i2c";
151 reg = <0x22000 0x1000>;
152 interrupts = <15>;
153 #address-cells = <1>;
154 #size-cells = <0>;
155 status = "disabled";
156 };
Kumar, Anil518f97d2013-02-06 09:30:03 +0530157 wdt: wdt@1c21000 {
158 compatible = "ti,davinci-wdt";
159 reg = <0x21000 0x1000>;
160 status = "disabled";
161 };
Manjunathappa, Prakash88df4122013-03-28 18:42:01 +0530162 mmc0: mmc@1c40000 {
163 compatible = "ti,da830-mmc";
164 reg = <0x40000 0x1000>;
165 interrupts = <16>;
166 status = "disabled";
167 };
Philip Avinash64fa59c2013-04-10 17:42:41 +0530168 ehrpwm0: ehrpwm@01f00000 {
169 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
170 #pwm-cells = <3>;
171 reg = <0x300000 0x2000>;
172 status = "disabled";
173 };
174 ehrpwm1: ehrpwm@01f02000 {
175 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
176 #pwm-cells = <3>;
177 reg = <0x302000 0x2000>;
178 status = "disabled";
179 };
180 ecap0: ecap@01f06000 {
181 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
182 #pwm-cells = <3>;
183 reg = <0x306000 0x80>;
184 status = "disabled";
185 };
186 ecap1: ecap@01f07000 {
187 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
188 #pwm-cells = <3>;
189 reg = <0x307000 0x80>;
190 status = "disabled";
191 };
192 ecap2: ecap@01f08000 {
193 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
194 #pwm-cells = <3>;
195 reg = <0x308000 0x80>;
196 status = "disabled";
197 };
Heiko Schocher33085b32012-08-30 14:21:04 +0530198 };
Kumar, Anil99b88002013-01-16 14:37:41 +0530199 nand_cs3@62000000 {
200 compatible = "ti,davinci-nand";
201 reg = <0x62000000 0x807ff
202 0x68000000 0x8000>;
203 ti,davinci-chipselect = <1>;
204 ti,davinci-mask-ale = <0>;
205 ti,davinci-mask-cle = <0>;
206 ti,davinci-mask-chipsel = <0>;
207 ti,davinci-ecc-mode = "hw";
208 ti,davinci-ecc-bits = <4>;
209 ti,davinci-nand-use-bbt;
210 status = "disabled";
211 };
Heiko Schocher33085b32012-08-30 14:21:04 +0530212};