blob: 7f428272fee646980bea4e3d5d745eecbe6983ab [file] [log] [blame]
Tomasz Figa0f7238a2012-11-06 15:09:04 +09001/*
2 * Samsung's Exynos4412 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4412";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x4000>;
27 };
Thomas Abrahambbd9700a2013-03-09 16:12:35 +090028
29 mct@10050000 {
30 compatible = "samsung,exynos4412-mct";
31 reg = <0x10050000 0x800>;
32 interrupt-controller;
33 #interrups-cells = <2>;
34 interrupt-parent = <&mct_map>;
35 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
36 <4 0>, <5 0>, <6 0>, <7 0>;
Thomas Abraham7ad34332013-03-09 17:11:38 +090037 clocks = <&clock 3>, <&clock 344>;
38 clock-names = "fin_pll", "mct";
Thomas Abrahambbd9700a2013-03-09 16:12:35 +090039
40 mct_map: mct-map {
41 #interrupt-cells = <2>;
42 #address-cells = <0>;
43 #size-cells = <0>;
44 interrupt-map = <0x0 0 &gic 0 57 0>,
45 <0x1 0 &combiner 12 5>,
46 <0x2 0 &combiner 12 6>,
47 <0x3 0 &combiner 12 7>,
48 <0x4 0 &gic 1 12 0>,
49 <0x5 0 &gic 1 12 0>,
50 <0x6 0 &gic 1 12 0>,
51 <0x7 0 &gic 1 12 0>;
52 };
53 };
Thomas Abraham662478d2013-04-10 17:51:32 +090054
55 mshc@12550000 {
56 compatible = "samsung,exynos4412-dw-mshc";
57 reg = <0x12550000 0x1000>;
58 interrupts = <0 77 0>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 };
Tomasz Figa0f7238a2012-11-06 15:09:04 +090062};