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review.evervolv.com / android_kernel_oneplus_msm8996 / 670ee03ccc29b3a14c6cbe04241c903342442c23 / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 7eef88f00fea9532d91f81648554f97a9cb5f11d [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 };
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]11 intc: interrupt-controller {
12 compatible = "marvell,orion-intc", "marvell,intc";
13 interrupt-controller;
14 #interrupt-cells = <1>;
15 reg = <0xf1020204 0x04>,
16 <0xf1020214 0x04>;
17 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]18
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]19 ocp@f1000000 {
20 compatible = "simple-bus";
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]21 ranges = <0x00000000 0xf1000000 0x4000000
Thomas Petazzoni670ee032013-05-15 15:36:56 +0200[diff] [blame^]22 0xe0000000 0xe0000000 0x8100000 /* PCIE */
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]23 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]24 #address-cells = <1>;
25 #size-cells = <1>;
26
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]27 core_clk: core-clocks@10030 {
28 compatible = "marvell,kirkwood-core-clock";
29 reg = <0x10030 0x4>;
30 #clock-cells = <1>;
31 };
32
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]33 gpio0: gpio@10100 {
34 compatible = "marvell,orion-gpio";
35 #gpio-cells = <2>;
36 gpio-controller;
37 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]38 ngpios = <32>;
39 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]40 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]41 interrupts = <35>, <36>, <37>, <38>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]42 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]43 };
44
45 gpio1: gpio@10140 {
46 compatible = "marvell,orion-gpio";
47 #gpio-cells = <2>;
48 gpio-controller;
49 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]50 ngpios = <18>;
51 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]52 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]53 interrupts = <39>, <40>, <41>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]54 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]55 };
56
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]57 serial@12000 {
58 compatible = "ns16550a";
59 reg = <0x12000 0x100>;
60 reg-shift = <2>;
61 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]62 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]63 status = "disabled";
64 };
65
66 serial@12100 {
67 compatible = "ns16550a";
68 reg = <0x12100 0x100>;
69 reg-shift = <2>;
70 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]71 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]72 status = "disabled";
73 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]74
75 rtc@10300 {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]76 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]77 reg = <0x10300 0x20>;
78 interrupts = <53>;
Andrew Lunn89c58c12013-02-03 12:32:06 +0100[diff] [blame]79 clocks = <&gate_clk 7>;
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]80 };
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]81
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]82 spi@10600 {
83 compatible = "marvell,orion-spi";
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 interrupts = <23>;
88 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]89 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]90 status = "disabled";
91 };
92
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]93 gate_clk: clock-gating-control@2011c {
94 compatible = "marvell,kirkwood-gating-clock";
95 reg = <0x2011c 0x4>;
96 clocks = <&core_clk 0>;
97 #clock-cells = <1>;
98 };
99
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]100 wdt@20300 {
101 compatible = "marvell,orion-wdt";
102 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]103 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]104 status = "okay";
105 };
106
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame]107 xor@60800 {
108 compatible = "marvell,orion-xor";
109 reg = <0x60800 0x100
110 0x60A00 0x100>;
111 status = "okay";
112 clocks = <&gate_clk 8>;
113
114 xor00 {
115 interrupts = <5>;
116 dmacap,memcpy;
117 dmacap,xor;
118 };
119 xor01 {
120 interrupts = <6>;
121 dmacap,memcpy;
122 dmacap,xor;
123 dmacap,memset;
124 };
125 };
126
127 xor@60900 {
128 compatible = "marvell,orion-xor";
129 reg = <0x60900 0x100
130 0xd0B00 0x100>;
131 status = "okay";
132 clocks = <&gate_clk 16>;
133
134 xor00 {
135 interrupts = <7>;
136 dmacap,memcpy;
137 dmacap,xor;
138 };
139 xor01 {
140 interrupts = <8>;
141 dmacap,memcpy;
142 dmacap,xor;
143 dmacap,memset;
144 };
145 };
146
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]147 ehci@50000 {
148 compatible = "marvell,orion-ehci";
149 reg = <0x50000 0x1000>;
150 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100[diff] [blame]151 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]152 status = "okay";
153 };
154
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]155 sata@80000 {
156 compatible = "marvell,orion-sata";
157 reg = <0x80000 0x5000>;
158 interrupts = <21>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]159 clocks = <&gate_clk 14>, <&gate_clk 15>;
160 clock-names = "0", "1";
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]161 status = "disabled";
162 };
163
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]164 nand@3000000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 cle = <0>;
168 ale = <1>;
169 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]170 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]171 reg = <0x3000000 0x400>;
172 chip-delay = <25>;
173 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]174 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]175 status = "disabled";
176 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]177
178 i2c@11000 {
179 compatible = "marvell,mv64xxx-i2c";
180 reg = <0x11000 0x20>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 interrupts = <29>;
184 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]185 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]186 status = "disabled";
187 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]188
189 crypto@30000 {
190 compatible = "marvell,orion-crypto";
191 reg = <0x30000 0x10000>,
192 <0xf5000000 0x800>;
193 reg-names = "regs", "sram";
194 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]195 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]196 status = "okay";
197 };
Thomas Petazzoniec05fcf2012-12-21 15:49:10 +0100[diff] [blame]198
199 mvsdio@90000 {
200 compatible = "marvell,orion-sdio";
201 reg = <0x90000 0x200>;
202 interrupts = <28>;
203 clocks = <&gate_clk 4>;
204 status = "disabled";
205 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]206 };
207};