blob: e4eff878123d5efda65295b3abbcb73d4923ff5a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* cpu.c: Dinky routines to look for the kind of Sparc cpu
2 * we are on.
3 *
David S. Miller68c9f9f2007-08-07 19:09:29 -07004 * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 */
6
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/sched.h>
10#include <linux/smp.h>
11#include <asm/asi.h>
12#include <asm/system.h>
13#include <asm/fpumacro.h>
14#include <asm/cpudata.h>
David S. Miller12816ab2006-02-09 03:00:00 -080015#include <asm/spitfire.h>
David S. Miller68c9f9f2007-08-07 19:09:29 -070016#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
18DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
19
20struct cpu_iu_info {
21 short manuf;
22 short impl;
23 char* cpu_name; /* should be enough I hope... */
24};
25
26struct cpu_fp_info {
27 short manuf;
28 short impl;
29 char fpu_vers;
30 char* fp_name;
31};
32
33struct cpu_fp_info linux_sparc_fpu[] = {
34 { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
35 { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
36 { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
37 { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
38 { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
39 { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
40 { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
41 { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
42 { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
David S. Millerd2212bc2005-09-27 22:50:06 -070043 { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
44 { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
Linus Torvalds1da177e2005-04-16 15:20:36 -070045};
46
Tobias Klauser84c1a132005-11-09 12:03:42 -080047#define NSPARCFPU ARRAY_SIZE(linux_sparc_fpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49struct cpu_iu_info linux_sparc_chips[] = {
50 { 0x17, 0x10, "TI UltraSparc I (SpitFire)"},
51 { 0x22, 0x10, "TI UltraSparc I (SpitFire)"},
52 { 0x17, 0x11, "TI UltraSparc II (BlackBird)"},
53 { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
54 { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
55 { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
56 { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
57 { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
58 { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
David S. Millerd2212bc2005-09-27 22:50:06 -070059 { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
60 { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
Linus Torvalds1da177e2005-04-16 15:20:36 -070061};
62
Tobias Klauser84c1a132005-11-09 12:03:42 -080063#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
David S. Miller68c9f9f2007-08-07 19:09:29 -070065char *sparc_cpu_type;
66char *sparc_fpu_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
68unsigned int fsr_storage;
69
David S. Miller68c9f9f2007-08-07 19:09:29 -070070static void __init sun4v_cpu_probe(void)
71{
72 struct device_node *dp;
73 const char *compat;
74 int len;
75
76 dp = of_find_node_by_name(NULL, "cpu");
77 if (!dp)
78 goto no_compat;
79
80 compat = of_get_property(dp, "compatible", &len);
81 if (!compat)
82 goto no_compat;
83
84 if (of_find_in_proplist(compat, "SUNW,UltraSPARC-T1", len)) {
85 sparc_cpu_type = "UltraSparc T1 (Niagara)";
86 sparc_fpu_type = "UltraSparc T1 integrated FPU";
87 } else if (of_find_in_proplist(compat, "SUNW,UltraSPARC-T2", len)) {
88 sparc_cpu_type = "UltraSparc T2 (Niagara2)";
89 sparc_fpu_type = "UltraSparc T2 integrated FPU";
90 } else
91 goto unknown;
92
93 return;
94
95no_compat:
96 compat = "no property";
97
98unknown:
99 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n", compat);
100 sparc_cpu_type = "Unknown SUN4V CPU";
101 sparc_fpu_type = "Unknown SUN4V FPU";
102}
103
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104void __init cpu_probe(void)
105{
106 unsigned long ver, fpu_vers, manuf, impl, fprs;
107 int i;
108
David S. Miller68c9f9f2007-08-07 19:09:29 -0700109 if (tlb_type == hypervisor)
110 return sun4v_cpu_probe();
David S. Millerd82ace72006-02-09 02:52:44 -0800111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 fprs = fprs_read();
113 fprs_write(FPRS_FEF);
114 __asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
115 : "=&r" (ver)
116 : "r" (&fpu_vers));
117 fprs_write(fprs);
118
119 manuf = ((ver >> 48) & 0xffff);
120 impl = ((ver >> 32) & 0xffff);
121
122 fpu_vers = ((fpu_vers >> 17) & 0x7);
123
124retry:
125 for (i = 0; i < NSPARCCHIPS; i++) {
126 if (linux_sparc_chips[i].manuf == manuf) {
127 if (linux_sparc_chips[i].impl == impl) {
128 sparc_cpu_type =
129 linux_sparc_chips[i].cpu_name;
130 break;
131 }
132 }
133 }
134
135 if (i == NSPARCCHIPS) {
136 /* Maybe it is a cheetah+ derivative, report it as cheetah+
137 * in that case until we learn the real names.
138 */
139 if (manuf == 0x3e &&
140 impl > 0x15) {
141 impl = 0x15;
142 goto retry;
143 } else {
144 printk("DEBUG: manuf[%lx] impl[%lx]\n",
145 manuf, impl);
146 }
147 sparc_cpu_type = "Unknown CPU";
148 }
149
150 for (i = 0; i < NSPARCFPU; i++) {
151 if (linux_sparc_fpu[i].manuf == manuf &&
152 linux_sparc_fpu[i].impl == impl) {
153 if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
154 sparc_fpu_type =
155 linux_sparc_fpu[i].fp_name;
156 break;
157 }
158 }
159 }
160
161 if (i == NSPARCFPU) {
162 printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
163 manuf, impl, fpu_vers);
164 sparc_fpu_type = "Unknown FPU";
165 }
166}