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review.evervolv.com / android_kernel_oneplus_msm8996 / 6b60393e08f9263c7b129d54eeb261e8f970175c / . / Documentation / devicetree / bindings / net / cpsw.txt
blob: dba014fc5e7b99d56326e886b7265eb696559b90 [file] [log] [blame]
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]1TI SoC Ethernet Switch Controller Device Tree Bindings
2------------------------------------------------------
3
4Required properties:
5- compatible : Should be "ti,cpsw"
6- reg : physical base address and size of the cpsw
7 registers map
8- interrupts : property with a value describing the interrupt
9 number
10- interrupt-parent : The parent interrupt controller
11- cpdma_channels : Specifies number of channels in CPDMA
12- host_port_no : Specifies host port shift
13- cpdma_reg_ofs : Specifies CPDMA submodule register offset
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]14- cpdma_sram_ofs : Specifies CPDMA SRAM offset
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]15- ale_reg_ofs : Specifies ALE submodule register offset
16- ale_entries : Specifies No of entries ALE can hold
17- host_port_reg_ofs : Specifies host port register offset
18- hw_stats_reg_ofs : Specifies hardware statistics register offset
Richard Cochran6b603932012-10-29 08:45:17 +0000[diff] [blame^]19- cpts_reg_ofs : Specifies the offset of the CPTS registers
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]20- bd_ram_ofs : Specifies internal desciptor RAM offset
21- bd_ram_size : Specifies internal descriptor RAM size
22- rx_descs : Specifies number of Rx descriptors
23- mac_control : Specifies Default MAC control register content
24 for the specific platform
25- slaves : Specifies number for slaves
26- slave_reg_ofs : Specifies slave register offset
27- sliver_reg_ofs : Specifies slave sliver register offset
28- phy_id : Specifies slave phy id
29- mac-address : Specifies slave MAC address
30
31Optional properties:
32- ti,hwmods : Must be "cpgmac0"
33- no_bd_ram : Must be 0 or 1
34
35Note: "ti,hwmods" field is used to fetch the base address and irq
36resources from TI, omap hwmod data base during device registration.
37Future plan is to migrate hwmod data base contents into device tree
38blob so that, all the required data will be used from device tree dts
39file.
40
41Examples:
42
43 mac: ethernet@4A100000 {
44 compatible = "ti,cpsw";
45 reg = <0x4A100000 0x1000>;
46 interrupts = <55 0x4>;
47 interrupt-parent = <&intc>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]48 cpdma_channels = <8>;
49 host_port_no = <0>;
50 cpdma_reg_ofs = <0x800>;
51 cpdma_sram_ofs = <0xa00>;
52 ale_reg_ofs = <0xd00>;
53 ale_entries = <1024>;
54 host_port_reg_ofs = <0x108>;
55 hw_stats_reg_ofs = <0x900>;
Richard Cochran6b603932012-10-29 08:45:17 +0000[diff] [blame^]56 cpts_reg_ofs = <0xc00>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]57 bd_ram_ofs = <0x2000>;
58 bd_ram_size = <0x2000>;
59 no_bd_ram = <0>;
60 rx_descs = <64>;
61 mac_control = <0x20>;
62 slaves = <2>;
63 cpsw_emac0: slave@0 {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000[diff] [blame]64 slave_reg_ofs = <0x200>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]65 sliver_reg_ofs = <0xd80>;
66 phy_id = "davinci_mdio.16:00";
67 /* Filled in by U-Boot */
68 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]69 };
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]70 cpsw_emac1: slave@1 {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000[diff] [blame]71 slave_reg_ofs = <0x300>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]72 sliver_reg_ofs = <0xdc0>;
73 phy_id = "davinci_mdio.16:01";
74 /* Filled in by U-Boot */
75 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]76 };
77 };
78
79(or)
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]80 mac: ethernet@4A100000 {
81 compatible = "ti,cpsw";
82 ti,hwmods = "cpgmac0";
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]83 cpdma_channels = <8>;
84 host_port_no = <0>;
85 cpdma_reg_ofs = <0x800>;
86 cpdma_sram_ofs = <0xa00>;
87 ale_reg_ofs = <0xd00>;
88 ale_entries = <1024>;
89 host_port_reg_ofs = <0x108>;
90 hw_stats_reg_ofs = <0x900>;
Richard Cochran6b603932012-10-29 08:45:17 +0000[diff] [blame^]91 cpts_reg_ofs = <0xc00>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]92 bd_ram_ofs = <0x2000>;
93 bd_ram_size = <0x2000>;
94 no_bd_ram = <0>;
95 rx_descs = <64>;
96 mac_control = <0x20>;
97 slaves = <2>;
98 cpsw_emac0: slave@0 {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000[diff] [blame]99 slave_reg_ofs = <0x200>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]100 sliver_reg_ofs = <0xd80>;
101 phy_id = "davinci_mdio.16:00";
102 /* Filled in by U-Boot */
103 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]104 };
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]105 cpsw_emac1: slave@1 {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000[diff] [blame]106 slave_reg_ofs = <0x300>;
Mugunthan V Ne07b94f2012-08-06 05:05:58 +0000[diff] [blame]107 sliver_reg_ofs = <0xdc0>;
108 phy_id = "davinci_mdio.16:01";
109 /* Filled in by U-Boot */
110 mac-address = [ 00 00 00 00 00 00 ];
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]111 };
Mugunthan V N2eb32b02012-07-30 10:17:14 +0000[diff] [blame]112 };